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charset="utf-8" As everything is in place, we can use a new system property to advertise which stage is supported and remove bad_ste from STE stage2 config. The property added arm-smmuv3.stage can have 3 values: - "1": Stage-1 only is advertised. - "2": Stage-2 only is advertised. - "all": Stage-1 + Stage-2 are supported, which is not implemented in this patch series. If not passed or an unsupported value is passed, it will default to stage-1. Advertise VMID16. Don't try to decode CD, if stage-2 is configured. Signed-off-by: Mostafa Saleh --- Changes in v2: - Squash knob patch with stage-2 enable patch. - Don't try to decode CD, if stage-2 is configured. --- hw/arm/smmuv3.c | 34 +++++++++++++++++++++++++--------- include/hw/arm/smmuv3.h | 1 + 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bc4ec202f4..ebffc7e5f5 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -21,6 +21,7 @@ #include "hw/irq.h" #include "hw/sysbus.h" #include "migration/vmstate.h" +#include "hw/qdev-properties.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "cpu.h" @@ -245,14 +246,20 @@ static void smmuv3_init_regs(SMMUv3State *s) ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(0)); uint8_t oas =3D FIELD_EX64(armcpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PA= RANGE); =20 - /** - * IDR0: stage1 only, AArch64 only, coherent access, 16b ASID, - * multi-level stream table + /* + * Based on sys property, the stages supported in smmu will be adverti= sed. + * At the moment "all" is not supported and default to stage-1. */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); /* stage 1 supporte= d */ + if (s->stage && !strcmp("2", s->stage)) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S2P, 1); + } else { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, S1P, 1); + } + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTF, 2); /* AArch64 PTW only= */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, COHACC, 1); /* IO coherent */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ASID16, 1); /* 16-bit ASID */ + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, VMID16, 1); /* 16-bit VMID */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, TTENDIAN, 2); /* little endi= an */ s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, STALL_MODEL, 1); /* No stall= */ /* terminated transaction will always be aborted/error returned */ @@ -508,10 +515,6 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cf= g, qemu_log_mask(LOG_UNIMP, "SMMUv3 Stall not implemented!\n"); goto bad_ste; } - - /* This is still here as stage 2 has not been fully enabled yet. */ - qemu_log_mask(LOG_UNIMP, "SMMUv3 does not support stage 2 yet\n"); - goto bad_ste; } =20 if (STE_S1CDMAX(ste) !=3D 0) { @@ -739,7 +742,7 @@ static int smmuv3_decode_config(IOMMUMemoryRegion *mr, = SMMUTransCfg *cfg, return ret; } =20 - if (cfg->aborted || cfg->bypassed) { + if (cfg->aborted || cfg->bypassed || (cfg->stage =3D=3D 2)) { return 0; } =20 @@ -1801,6 +1804,18 @@ static const VMStateDescription vmstate_smmuv3 =3D { } }; =20 +static Property smmuv3_properties[] =3D { + /* + * Stages of translation advertised. + * "1": Stage 1 + * "2": Stage 2 + * "all": Stage 1 + Stage 2 + * Defaults to stage 1 + */ + DEFINE_PROP_STRING("stage", SMMUv3State, stage), + DEFINE_PROP_END_OF_LIST() +}; + static void smmuv3_instance_init(Object *obj) { /* Nothing much to do here as of now */ @@ -1817,6 +1832,7 @@ static void smmuv3_class_init(ObjectClass *klass, voi= d *data) &c->parent_phases); c->parent_realize =3D dc->realize; dc->realize =3D smmu_realize; + device_class_set_props(dc, smmuv3_properties); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 6031d7d325..d183a62766 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -62,6 +62,7 @@ struct SMMUv3State { =20 qemu_irq irq[4]; QemuMutex mutex; + char *stage; }; =20 typedef enum { --=20 2.39.2.637.g21b0678d19-goog