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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.25.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:25:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N6B+a0N7tu/9UM+UAFolg4I0Ga2IK7hy9mNAOGH/dPg=; b=gJdK7aZt1u6+wWiGl1LYeNpXxYb3+8ND4VW+6DB/lxPFH0LVS6lgzwz+RFBEiHXDUl Wx2ksEBy+GIjAR169yqfWsXAjZYVB61RHCH7cLovDFZB1rJDBdyJ0o5FfnzEBFS04Rmf lFGGSpMDTEG+EE4r0UNGtEPiKMKRgDPWInM6ydpKkxodp8A5JCxMtD63h1JsW/q+t64K jES4lFteJg0Bfg4wg8/8GyrGSQLbNpP0lMZGLod1oj7nsCVVUjf8Ite/a4ZoIMZX1w11 dYGqwUgs/3b5ztfOruJmJ/gXoIaYK8xTqnjSlkgA29mdz+gULKHNYb43CBlMLSO7oqPE HbBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N6B+a0N7tu/9UM+UAFolg4I0Ga2IK7hy9mNAOGH/dPg=; b=f3nd93L05by2NUqa76OdP3OxbEO/PyyDUpT+jvWckQaJ6DbNLIjcQbj7jCs0nSfCrP 2SGOjUNXhiSsR19wkt/eACLtmk8nWT89fPL6l8tGP4wvirH4PTcgXuHHiWOwR93jCWIQ 07v+6QhW5ZzZcoEp3i9O5ZWZuXnmUPqJz7cznqqPCFW1B2EYQJFDXAj3MRGXTqjwnlsX HhuCgrFfdfIoUR03dDUQ7jbAcfIa0IeK/S4wnxN26eR6oTr06Mn9Zpsk7ftbGUerqFLh 4FanaaMM+LA/TpO/2w8rorZXM3uhTs3+HHKUeBbs8tTbzfn6SCUqesshbP34VTrVoYgk T54Q== X-Gm-Message-State: AO0yUKXEprLnNezN0Zhbu9a3TPe48durm8efe4D4Wq3FFsnjECphi/BA ytuP5CbS24yHYNsy7pFJ8RRD4wVowcn0jytwH4VFZQ== X-Google-Smtp-Source: AK7set8Sw6LABw9Um0lgl6lAMOhowI/V18JbvsWtqZmUH5YmEIdK18hPklc2kIMXOHerBA5iAHTTZQ== X-Received: by 2002:a17:902:fb90:b0:19c:d97f:5d20 with SMTP id lg16-20020a170902fb9000b0019cd97f5d20mr8882982plb.38.1677475540543; Sun, 26 Feb 2023 21:25:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 11/76] target/arm: Drop tcg_temp_free from translator-m-nocp.c Date: Sun, 26 Feb 2023 19:24:00 -1000 Message-Id: <20230227052505.352889-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677475913709100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-m-nocp.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 5df7d46120..9a89aab785 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -91,7 +91,6 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_= VLSTM *a) } else { gen_helper_v7m_vlstm(cpu_env, fptr); } - tcg_temp_free_i32(fptr); =20 clear_eci_state(s); =20 @@ -303,8 +302,6 @@ static void gen_branch_fpInactive(DisasContext *s, TCGC= ond cond, tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); tcg_gen_or_i32(fpca, fpca, aspen); tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); - tcg_temp_free_i32(aspen); - tcg_temp_free_i32(fpca); } =20 static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, @@ -328,7 +325,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, case ARM_VFP_FPSCR: tmp =3D loadfn(s, opaque, true); gen_helper_vfp_set_fpscr(cpu_env, tmp); - tcg_temp_free_i32(tmp); gen_lookup_tb(s); break; case ARM_VFP_FPSCR_NZCVQC: @@ -351,7 +347,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); tcg_gen_or_i32(fpscr, fpscr, tmp); store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); - tcg_temp_free_i32(tmp); break; } case ARM_VFP_FPCXT_NS: @@ -400,8 +395,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); gen_helper_vfp_set_fpscr(cpu_env, tmp); s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(sfpa); break; } case ARM_VFP_VPR: @@ -423,7 +416,6 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); store_cpu_field(vpr, v7m.vpr); s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; - tcg_temp_free_i32(tmp); break; } default: @@ -491,7 +483,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); tcg_gen_or_i32(tmp, tmp, sfpa); - tcg_temp_free_i32(sfpa); /* * Store result before updating FPSCR etc, in case * it is a memory write which causes an exception. @@ -505,7 +496,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, store_cpu_field(control, v7m.control[M_REG_S]); fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(fpscr); lookup_tb =3D true; break; } @@ -546,7 +536,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); tcg_gen_or_i32(tmp, tmp, sfpa); - tcg_temp_free_i32(control); /* Store result before updating FPSCR, in case it faults */ storefn(s, opaque, tmp, true); /* If SFPA is zero then set FPSCR from FPDSCR_NS */ @@ -554,9 +543,6 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), fpdscr, fpscr); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(sfpa); - tcg_temp_free_i32(fpdscr); - tcg_temp_free_i32(fpscr); break; } case ARM_VFP_VPR: @@ -598,7 +584,6 @@ static void fp_sysreg_to_gpr(DisasContext *s, void *opa= que, TCGv_i32 value, if (a->rt =3D=3D 15) { /* Set the 4 flag bits in the CPSR */ gen_set_nzcv(value); - tcg_temp_free_i32(value); } else { store_reg(s, a->rt, value); } @@ -666,7 +651,6 @@ static void fp_sysreg_to_memory(DisasContext *s, void *= opaque, TCGv_i32 value, if (do_access) { gen_aa32_st_i32(s, value, addr, get_mem_index(s), MO_UL | MO_ALIGN | s->be_data); - tcg_temp_free_i32(value); } =20 if (a->w) { @@ -675,8 +659,6 @@ static void fp_sysreg_to_memory(DisasContext *s, void *= opaque, TCGv_i32 value, tcg_gen_addi_i32(addr, addr, offset); } store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } } =20 @@ -717,8 +699,6 @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, vo= id *opaque, tcg_gen_addi_i32(addr, addr, offset); } store_reg(s, a->rn, addr); - } else { - tcg_temp_free_i32(addr); } return value; } --=20 2.34.1