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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id a14-20020a170902ecce00b0019a837be977sm3513341plh.271.2023.02.26.21.26.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:26:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZO7UItfQReoklgOJZJKKMMXCbbFRvVQBOxOhYteWFwg=; b=x3YWh6Y8Wl9/jAeHHhmj/GKXBMc51EvKKX4aGi4uIn72yLNZtdWJOVJCCJAptV0Uxo r0lQnej5CCFxIhIG6qG3fjPL0npmnXoRPI0kAFti/DkWRHDf+GJCO6ZJaIPQQdCJ8fGg sFmZ2CunPaqtp7P5iIEPbQ7Jfm3rxcrV1NOyiuid+xti+A1P5ewJvXM3m4Ly1SjTObcp VYaBD1qyS8eg8VYvC9Vnq1O5zr37YA4B8D1bK2zwsVKfkSCJd4qHivfds3RST5WQ3HYR rL3qaWmLAoN6cww96aybEDg1T+QBpg8EmWY6AQ53CLotbXzv2lN6+XlrNxjmiqq4RZjP HWMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZO7UItfQReoklgOJZJKKMMXCbbFRvVQBOxOhYteWFwg=; b=IQxckE0uH6usIm80T77npMVIsLZGQUGPV9tPuqC6QGjpgfn+GuiMWgSNcdgFPa2oSM epmkgMk0z+arf9hHFfohun6UrokHbbxI0pAwc/OidCgqZEyhVW+JGoatOOC3/b74dJjo YJ2r9wWCedg1/fsFpPRPITx/duzGY0x2yBQnw82qtWXNiI0jhlb+CBbskOv3H196C0L1 aKXM1cccQcHLA862U6sE8OY+eJf2WOfC3b/WZHAJsdGPG2Z75F42IQrbNeOV0zVqCaZY mOsPe+vX7lo4dxsFju0dDpjPHp8QGo9DjCBILfFTJ2lYGyRYKbIcnY8bOsy1n7EjehXt 45vg== X-Gm-Message-State: AO0yUKW3djFm3/aUC5NQN2vNEtdZEnfclshIuf+HeLF/0cl/Ugj38sHr vhFFfssUbEFSxEBun2JCJIJKvFqTjQ+P6uz1SkXb/w== X-Google-Smtp-Source: AK7set+LdMZViO7yFhYVGG002xPX4u26b6zxx8vsWM5QbembImHEOUoX2p7r/02oYGVotuZu6DnvGg== X-Received: by 2002:a17:902:f544:b0:19d:138b:7c4a with SMTP id h4-20020a170902f54400b0019d138b7c4amr3042423plf.3.1677475603333; Sun, 26 Feb 2023 21:26:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH v2 34/76] target/m68k: Drop free_cond Date: Sun, 26 Feb 2023 19:24:23 -1000 Message-Id: <20230227052505.352889-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1044; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1044.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476393998100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Remove the g1 and g2 members of DisasCompare, as they were used to track which temps needed to be freed. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/m68k/translate.c | 40 ---------------------------------------- 1 file changed, 40 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index b3cd3e87e1..d7237b6a99 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1249,8 +1249,6 @@ static int gen_ea_fp(CPUM68KState *env, DisasContext = *s, uint16_t insn, =20 typedef struct { TCGCond tcond; - bool g1; - bool g2; TCGv v1; TCGv v2; } DisasCompare; @@ -1263,7 +1261,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) =20 /* The CC_OP_CMP form can handle most normal comparisons directly. */ if (op =3D=3D CC_OP_CMPB || op =3D=3D CC_OP_CMPW || op =3D=3D CC_OP_CM= PL) { - c->g1 =3D c->g2 =3D 1; c->v1 =3D QREG_CC_N; c->v2 =3D QREG_CC_V; switch (cond) { @@ -1281,7 +1278,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) goto done; case 10: /* PL */ case 11: /* MI */ - c->g1 =3D c->g2 =3D 0; c->v2 =3D tcg_const_i32(0); c->v1 =3D tmp =3D tcg_temp_new(); tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V); @@ -1298,8 +1294,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) } } =20 - c->g1 =3D 1; - c->g2 =3D 0; c->v2 =3D tcg_const_i32(0); =20 switch (cond) { @@ -1383,7 +1377,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext= *s, int cond) case 2: /* HI (!C && !Z) -> !(C || Z)*/ case 3: /* LS (C || Z) */ c->v1 =3D tmp =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); tcg_gen_or_i32(tmp, tmp, QREG_CC_C); tcond =3D TCG_COND_NE; @@ -1411,14 +1404,12 @@ static void gen_cc_cond(DisasCompare *c, DisasConte= xt *s, int cond) case 12: /* GE (!(N ^ V)) */ case 13: /* LT (N ^ V) */ c->v1 =3D tmp =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V); tcond =3D TCG_COND_LT; break; case 14: /* GT (!(Z || (N ^ V))) */ case 15: /* LE (Z || (N ^ V)) */ c->v1 =3D tmp =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); tcg_gen_neg_i32(tmp, tmp); tmp2 =3D tcg_temp_new(); @@ -1436,16 +1427,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContex= t *s, int cond) c->tcond =3D tcond; } =20 -static void free_cond(DisasCompare *c) -{ - if (!c->g1) { - tcg_temp_free(c->v1); - } - if (!c->g2) { - tcg_temp_free(c->v2); - } -} - static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1) { DisasCompare c; @@ -1453,7 +1434,6 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGL= abel *l1) gen_cc_cond(&c, s, cond); update_cc_op(s); tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); - free_cond(&c); } =20 /* Force a TB lookup after an instruction that changes the CPU state. */ @@ -1512,7 +1492,6 @@ DISAS_INSN(scc) =20 tmp =3D tcg_temp_new(); tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); - free_cond(&c); =20 tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); @@ -4887,7 +4866,6 @@ static void do_trapcc(DisasContext *s, DisasCompare *= c) s->base.is_jmp =3D DISAS_NEXT; } } - free_cond(c); } =20 DISAS_INSN(trapcc) @@ -5383,9 +5361,7 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) { TCGv fpsr; =20 - c->g1 =3D 1; c->v2 =3D tcg_const_i32(0); - c->g2 =3D 0; /* TODO: Raise BSUN exception. */ fpsr =3D tcg_temp_new(); gen_load_fcr(s, fpsr, M68K_FPSR); @@ -5398,14 +5374,12 @@ static void gen_fcc_cond(DisasCompare *c, DisasCont= ext *s, int cond) case 1: /* EQual Z */ case 17: /* Signaling EQual Z */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); c->tcond =3D TCG_COND_NE; break; case 2: /* Ordered Greater Than !(A || Z || N) */ case 18: /* Greater Than !(A || Z || N) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); c->tcond =3D TCG_COND_EQ; @@ -5413,7 +5387,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 3: /* Ordered Greater than or Equal Z || !(A || N) */ case 19: /* Greater than or Equal Z || !(A || N) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A)= ); tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N); @@ -5424,7 +5397,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 4: /* Ordered Less Than !(!N || A || Z); */ case 20: /* Less Than !(!N || A || Z); */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N); tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z); c->tcond =3D TCG_COND_EQ; @@ -5432,7 +5404,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 5: /* Ordered Less than or Equal Z || (N && !A) */ case 21: /* Less than or Equal Z || (N && !A) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A)= ); tcg_gen_andc_i32(c->v1, fpsr, c->v1); @@ -5442,35 +5413,30 @@ static void gen_fcc_cond(DisasCompare *c, DisasCont= ext *s, int cond) case 6: /* Ordered Greater or Less than !(A || Z) */ case 22: /* Greater or Less than !(A || Z) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z); c->tcond =3D TCG_COND_EQ; break; case 7: /* Ordered !A */ case 23: /* Greater, Less or Equal !A */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); c->tcond =3D TCG_COND_EQ; break; case 8: /* Unordered A */ case 24: /* Not Greater, Less or Equal A */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A); c->tcond =3D TCG_COND_NE; break; case 9: /* Unordered or Equal A || Z */ case 25: /* Not Greater or Less then A || Z */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z); c->tcond =3D TCG_COND_NE; break; case 10: /* Unordered or Greater Than A || !(N || Z)) */ case 26: /* Not Less or Equal A || !(N || Z)) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z)= ); tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N); @@ -5481,7 +5447,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 11: /* Unordered or Greater or Equal A || Z || !N */ case 27: /* Not Less Than A || Z || !N */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N); c->tcond =3D TCG_COND_NE; @@ -5489,7 +5454,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContex= t *s, int cond) case 12: /* Unordered or Less Than A || (N && !Z) */ case 28: /* Not Greater than or Equal A || (N && !Z) */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z)= ); tcg_gen_andc_i32(c->v1, fpsr, c->v1); @@ -5499,14 +5463,12 @@ static void gen_fcc_cond(DisasCompare *c, DisasCont= ext *s, int cond) case 13: /* Unordered or Less or Equal A || Z || N */ case 29: /* Not Greater Than A || Z || N */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N); c->tcond =3D TCG_COND_NE; break; case 14: /* Not Equal !Z */ case 30: /* Signaling Not Equal !Z */ c->v1 =3D tcg_temp_new(); - c->g1 =3D 0; tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z); c->tcond =3D TCG_COND_EQ; break; @@ -5526,7 +5488,6 @@ static void gen_fjmpcc(DisasContext *s, int cond, TCG= Label *l1) gen_fcc_cond(&c, s, cond); update_cc_op(s); tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1); - free_cond(&c); } =20 DISAS_INSN(fbcc) @@ -5562,7 +5523,6 @@ DISAS_INSN(fscc) =20 tmp =3D tcg_temp_new(); tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); - free_cond(&c); =20 tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); --=20 2.34.1