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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id v4-20020a17090a520400b002369e16b276sm5172926pjh.32.2023.02.26.21.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:30:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=45/fsZysA6znj3lsxas/Rtz/1l3A7Tl30S+1TTOT2Q4=; b=PFFLnpxbx8LbgoBOnaYmvfylDgfKEq8qJvFnc61Ac5vnuc+KFESW5yehPGAzS0SCb1 1uNhcoP0PA/Yid2010p5BbVGL6pE2T4rRuAuBfToDjbkb3KLdmv7dUEF4G5NRCX7QbHY AIcfCjVDZhMnQYNtYsVeUkf/cLHar1qlVk/2l1n+2MrgqKnX/5/ywTBHePYMgmcHpNJm JLM1GSUOl4/pahTwhy7moFJ4ksNfdKNy74YPLnEC4xOTpukUggiBtRCoD6uHyWXIkuAa 2TaoYG3Iq/leG0RGi7i74aMDlxxS/WlpZ89HrgoQm8TwG7zUxl8YZFGs4PRI13Ed+DDT gGYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=45/fsZysA6znj3lsxas/Rtz/1l3A7Tl30S+1TTOT2Q4=; b=4oXDIFKfdm1rSlBHswwSsRO98/Iq8o5yzbQzxs5x3ayyXQ437dlFUi6lGkAPkFAbQ5 61RDNa7SKzU9ioecjmJhRcChom9YyPeDIkL8DGSfCvM4+QHSQkkgDmZMZ0ipv8LCbyKU Sk7BFu5Z3/pAea/QPB8k6D1GZxlyGOQVeKnshi7xyow/HzWtxICcoguCXpxDng3V9jad pbm2tKpmpj5qfBq8IeqbF1dvoQqZZ+01E2o+ed9nNoBs/cBEnl/30w7D15sZv5C3TW0k SKUoELsaM5eJlm3kICphsDkoCC0nSoN387oiVNwhYVDRwtdpMEVSGWreuX+kakvBS7X2 iQyA== X-Gm-Message-State: AO0yUKXhi30epRchKZpUvBIpu3r47oUFjEVXUugsc7RtGIyE1mHqDTkC 4nvliQb+9+zbqysfKWnMXySqc4lfD4a8gX2rWgc= X-Google-Smtp-Source: AK7set+somlgUi3q0x6Qx0HwGYYk5/XSvRGD3dHGUFlD2hy5tqzBeDzLfsXd+86nLtl8xXVNFy9UDQ== X-Received: by 2002:a17:90b:1e4d:b0:233:e1e6:33d4 with SMTP id pi13-20020a17090b1e4d00b00233e1e633d4mr24713361pjb.47.1677475848005; Sun, 26 Feb 2023 21:30:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v2 56/76] target/s390x: Use tcg_constant_* for DisasCompare Date: Sun, 26 Feb 2023 19:24:45 -1000 Message-Id: <20230227052505.352889-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227052505.352889-1-richard.henderson@linaro.org> References: <20230227052505.352889-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677476619062100003 The a and b fields are not modified by the consumer, and while we need not free a constant, tcg will quietly ignore such frees, so free_compare need not be changed. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3e3f685451..f2f2ea06eb 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -845,7 +845,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) c->is_64 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(c->u.s32.a, cc_dst); - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); break; case CC_OP_LTGT_32: case CC_OP_LTUGTU_32: @@ -860,7 +860,7 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_NZ: case CC_OP_FLOGR: c->u.s64.a =3D cc_dst; - c->u.s64.b =3D tcg_const_i64(0); + c->u.s64.b =3D tcg_constant_i64(0); c->g1 =3D true; break; case CC_OP_LTGT_64: @@ -874,14 +874,14 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) case CC_OP_TM_64: case CC_OP_ICM: c->u.s64.a =3D tcg_temp_new_i64(); - c->u.s64.b =3D tcg_const_i64(0); + c->u.s64.b =3D tcg_constant_i64(0); tcg_gen_and_i64(c->u.s64.a, cc_src, cc_dst); break; =20 case CC_OP_ADDU: case CC_OP_SUBU: c->is_64 =3D true; - c->u.s64.b =3D tcg_const_i64(0); + c->u.s64.b =3D tcg_constant_i64(0); c->g1 =3D true; switch (mask) { case 8 | 2: @@ -904,65 +904,65 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) switch (mask) { case 0x8 | 0x4 | 0x2: /* cc !=3D 3 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(3); + c->u.s32.b =3D tcg_constant_i32(3); break; case 0x8 | 0x4 | 0x1: /* cc !=3D 2 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(2); + c->u.s32.b =3D tcg_constant_i32(2); break; case 0x8 | 0x2 | 0x1: /* cc !=3D 1 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(1); + c->u.s32.b =3D tcg_constant_i32(1); break; case 0x8 | 0x2: /* cc =3D=3D 0 || cc =3D=3D 2 =3D> (cc & 1) =3D=3D= 0 */ cond =3D TCG_COND_EQ; c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x8 | 0x4: /* cc < 2 */ cond =3D TCG_COND_LTU; - c->u.s32.b =3D tcg_const_i32(2); + c->u.s32.b =3D tcg_constant_i32(2); break; case 0x8: /* cc =3D=3D 0 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); break; case 0x4 | 0x2 | 0x1: /* cc !=3D 0 */ cond =3D TCG_COND_NE; - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); break; case 0x4 | 0x1: /* cc =3D=3D 1 || cc =3D=3D 3 =3D> (cc & 1) !=3D 0= */ cond =3D TCG_COND_NE; c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); - c->u.s32.b =3D tcg_const_i32(0); + c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); break; case 0x4: /* cc =3D=3D 1 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(1); + c->u.s32.b =3D tcg_constant_i32(1); break; case 0x2 | 0x1: /* cc > 1 */ cond =3D TCG_COND_GTU; - c->u.s32.b =3D tcg_const_i32(1); + c->u.s32.b =3D tcg_constant_i32(1); break; case 0x2: /* cc =3D=3D 2 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(2); + c->u.s32.b =3D tcg_constant_i32(2); break; case 0x1: /* cc =3D=3D 3 */ cond =3D TCG_COND_EQ; - c->u.s32.b =3D tcg_const_i32(3); + c->u.s32.b =3D tcg_constant_i32(3); break; default: /* CC is masked by something else: (8 >> cc) & mask. */ cond =3D TCG_COND_NE; c->g1 =3D false; - c->u.s32.a =3D tcg_const_i32(8); - c->u.s32.b =3D tcg_const_i32(0); - tcg_gen_shr_i32(c->u.s32.a, c->u.s32.a, cc_op); + c->u.s32.a =3D tcg_temp_new_i32(); + c->u.s32.b =3D tcg_constant_i32(0); + tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); tcg_gen_andi_i32(c->u.s32.a, c->u.s32.a, mask); break; } @@ -1619,7 +1619,7 @@ static DisasJumpType op_bct32(DisasContext *s, DisasO= ps *o) tcg_gen_subi_i64(t, regs[r1], 1); store_reg32_i64(r1, t); c.u.s32.a =3D tcg_temp_new_i32(); - c.u.s32.b =3D tcg_const_i32(0); + c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); =20 @@ -1643,7 +1643,7 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOp= s *o) tcg_gen_subi_i64(t, t, 1); store_reg32h_i64(r1, t); c.u.s32.a =3D tcg_temp_new_i32(); - c.u.s32.b =3D tcg_const_i32(0); + c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_temp_free_i64(t); =20 @@ -1664,7 +1664,7 @@ static DisasJumpType op_bct64(DisasContext *s, DisasO= ps *o) =20 tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a =3D regs[r1]; - c.u.s64.b =3D tcg_const_i64(0); + c.u.s64.b =3D tcg_constant_i64(0); =20 return help_branch(s, &c, is_imm, imm, o->in2); } --=20 2.34.1