Since we're assigning to cpu_sr_t in the end,
use that as the intermediate temp as well.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ad6de41712..70a45c26e8 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1610,12 +1610,9 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
return;
case 0x401b: /* tas.b @Rn */
- {
- TCGv val = tcg_const_i32(0x80);
- tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val,
- ctx->memidx, MO_UB);
- tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
- }
+ tcg_gen_atomic_fetch_or_i32(cpu_sr_t, REG(B11_8),
+ tcg_constant_i32(0x80), ctx->memidx, MO_UB);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0);
return;
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
--
2.34.1