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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id d10-20020aa7868a000000b005cdc64a287dsm3317137pfo.115.2023.02.26.21.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:44:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/choyUiuVszNnrsokDt6HTpPjrDSeCtIo9k1KJDgu7s=; b=AF5C9Lmg0UhvnWdbZXvAZ+Lk7hBWs8CNaHQFImgWHxGk3E/5zvqoFakRYm42hjbT5M wqLwDp2G0QzETIHVUl4ILfTHqK7mGXlAaCT0EQ7j2yvEJLZDlaqlRvUMqahy9Oc5B9Gq LEK9etg0nY7f3RGVwiCSI/pix5QTYOBWqj8LYkNa6pSdAOO7H6kA9iBXs715hIfcVCja azdc7Fu2nDPdhGZMU5JwjwIjwjc9cNGOPWPxfemTPFS648vliLnRoPHqFJjKgbV0JHNT TZXmlhiA+l+Lwu/VnlOutczFHtP6AVMN3niAV2ybFJH3HnIbXh0co4e9SY2bb7b8a1H+ 7MPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/choyUiuVszNnrsokDt6HTpPjrDSeCtIo9k1KJDgu7s=; b=fPPtsRcS2uMR0F6zm8gtVIKvn4MqHbUvqUxMqLa7n7YK8pD+U14IlCEb/+nP8FeuXu B05GH6cR9NzU2llZa/ShJd5lg0IM2OZkRrnA95fCGKa+0j0ubWNTac0HYyKpuyWvOF/Y Q1hCK1kqeKwUO7+1DUN7ueQbp9KNuLcKsXX+28B1Gp2S3ZuXuL4ktCOLzLtPX7/YNK2P cusMksQY/cazzpUxUylHN+O228kEikH5eUYoO5K0W98ZZJHO6euh99cssk1b5/YeCIBF 07s2BSlFBsn8SFEOEgTGWTAZztJdGeRxOh0M6Uxnky5OeEo0kWQg9T6nejXPMp6hb53N S2/A== X-Gm-Message-State: AO0yUKX0bjk5bZKO8BckGjpxDEwA5wK3RB2Yec8IN0SuBz2CGNc//IDI BJDEY8fojATPboIPSnluoSqsRr4EQ6ZXY6Sq9b0= X-Google-Smtp-Source: AK7set9Mra0141Pwi3WsXNZkQW2rRwt/C/ZUmqdTWh5Ga1NZBGTnl8NhuZnHaALztXPyvaVIKNQ73A== X-Received: by 2002:aa7:960c:0:b0:5a0:c4b6:edd6 with SMTP id q12-20020aa7960c000000b005a0c4b6edd6mr21247336pfg.0.1677476666887; Sun, 26 Feb 2023 21:44:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH 39/70] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc Date: Sun, 26 Feb 2023 19:42:02 -1000 Message-Id: <20230227054233.390271-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227054233.390271-1-richard.henderson@linaro.org> References: <20230227054233.390271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677485250636100003 Content-Type: text/plain; charset="utf-8" All remaining uses are strictly read-only. Signed-off-by: Richard Henderson --- target/ppc/translate/vsx-impl.c.inc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx= -impl.c.inc index 9916784e64..0f5b0056f1 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -154,7 +154,7 @@ static void gen_lxvdsx(DisasContext *ctx) static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl, TCGv_i64 inh, TCGv_i64 inl) { - TCGv_i64 mask =3D tcg_const_i64(0x00FF00FF00FF00FF); + TCGv_i64 mask =3D tcg_constant_i64(0x00FF00FF00FF00FF); TCGv_i64 t0 =3D tcg_temp_new_i64(); TCGv_i64 t1 =3D tcg_temp_new_i64(); =20 @@ -825,7 +825,7 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_= rc *a) REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_VSX(ctx); =20 - ro =3D tcg_const_i32(a->rc); + ro =3D tcg_constant_i32(a->rc); =20 xt =3D gen_avr_ptr(a->rt); xb =3D gen_avr_ptr(a->rb); @@ -860,7 +860,7 @@ static void gen_##name(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VSXU); = \ return; = \ } = \ - opc =3D tcg_const_i32(ctx->opcode); = \ + opc =3D tcg_constant_i32(ctx->opcode); = \ gen_helper_##name(cpu_env, opc); = \ } =20 @@ -900,7 +900,7 @@ static void gen_##name(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VSXU); = \ return; = \ } = \ - opc =3D tcg_const_i32(ctx->opcode); = \ + opc =3D tcg_constant_i32(ctx->opcode); = \ xa =3D gen_vsr_ptr(xA(ctx->opcode)); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ gen_helper_##name(cpu_env, opc, xa, xb); = \ @@ -915,7 +915,7 @@ static void gen_##name(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VSXU); = \ return; = \ } = \ - opc =3D tcg_const_i32(ctx->opcode); = \ + opc =3D tcg_constant_i32(ctx->opcode); = \ xb =3D gen_vsr_ptr(xB(ctx->opcode)); = \ gen_helper_##name(cpu_env, opc, xb); = \ } @@ -929,7 +929,7 @@ static void gen_##name(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VSXU); = \ return; = \ } = \ - opc =3D tcg_const_i32(ctx->opcode); = \ + opc =3D tcg_constant_i32(ctx->opcode); = \ xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ @@ -945,7 +945,7 @@ static void gen_##name(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VSXU); = \ return; = \ } = \ - opc =3D tcg_const_i32(ctx->opcode); = \ + opc =3D tcg_constant_i32(ctx->opcode); = \ xt =3D gen_vsr_ptr(rD(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ gen_helper_##name(cpu_env, opc, xt, xb); = \ @@ -960,7 +960,7 @@ static void gen_##name(DisasContext *ctx) = \ gen_exception(ctx, POWERPC_EXCP_VSXU); = \ return; = \ } = \ - opc =3D tcg_const_i32(ctx->opcode); = \ + opc =3D tcg_constant_i32(ctx->opcode); = \ xa =3D gen_vsr_ptr(rA(ctx->opcode) + 32); = \ xb =3D gen_vsr_ptr(rB(ctx->opcode) + 32); = \ gen_helper_##name(cpu_env, opc, xa, xb); = \ @@ -1994,8 +1994,8 @@ static void gen_xsxsigdp(DisasContext *ctx) exp =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new_i64(); t1 =3D tcg_temp_new_i64(); - zr =3D tcg_const_i64(0); - nan =3D tcg_const_i64(2047); + zr =3D tcg_constant_i64(0); + nan =3D tcg_constant_i64(2047); =20 get_cpu_vsr(t1, xB(ctx->opcode), true); tcg_gen_extract_i64(exp, t1, 52, 11); @@ -2026,8 +2026,8 @@ static void gen_xsxsigqp(DisasContext *ctx) get_cpu_vsr(xbl, rB(ctx->opcode) + 32, false); exp =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new_i64(); - zr =3D tcg_const_i64(0); - nan =3D tcg_const_i64(32767); + zr =3D tcg_constant_i64(0); + nan =3D tcg_constant_i64(32767); =20 tcg_gen_extract_i64(exp, xbh, 48, 15); tcg_gen_movi_i64(t0, 0x0001000000000000); @@ -2193,8 +2193,8 @@ static void gen_xvxsigdp(DisasContext *ctx) get_cpu_vsr(xbl, xB(ctx->opcode), false); exp =3D tcg_temp_new_i64(); t0 =3D tcg_temp_new_i64(); - zr =3D tcg_const_i64(0); - nan =3D tcg_const_i64(2047); + zr =3D tcg_constant_i64(0); + nan =3D tcg_constant_i64(2047); =20 tcg_gen_extract_i64(exp, xbh, 52, 11); tcg_gen_movi_i64(t0, 0x0010000000000000); --=20 2.34.1