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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id im16-20020a170902bb1000b0019a983f0119sm3553986plb.307.2023.02.26.21.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:47:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rl72DxjHCuAt8m2JA2lIrs6gx/xD/HZtPB0tpD3hLcY=; b=oBtLo43qqmUNwIOXRSaS7NJqlCVxM5fCrvorXVyxsTZkmOn4w7SGih4Gxr6E9kd3mD ZnXDTTvf+F3KGVdAEZWgtFMZh9G0hPcuZ0xnoKECcHgrEM60rNqe3TYT+FXqzfJOIBrh Vmzwxr/RSW9SEeGR96aG3KwuD518lnpLcD46LPdVDHplR+SAL3JOG5iraVbplXMWM1J7 oxwsAmOkAGu8xBvR2GAKM4rdsvGVRsMetBh9IEuQeLWfDZZq+YgzktY8zDZ8goEMV2Xe zNR2o8QK7VMI01D3rj/pI3Fki0vxJxCbZyyh63ZT3eqjg2sJgQwdqPX6T1VWtNVJScVt MexQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rl72DxjHCuAt8m2JA2lIrs6gx/xD/HZtPB0tpD3hLcY=; b=cJ7wDpMeM/037kSgQTWQJysyfSWNhhQuzvK4VQhPRmTxIkA01aQu/W/zBRAtY2GTuG inIjGwnSWGUxRqBDjWINKUrehOAhkabnnNaoZC7QZVe968ATDdyizPVZv6F4O7xor9VI i+fEYHpWu1UNmsD2zn26HvDWFa0b6n46VhYyGKeTgo5wtblzYbv+GLKEiUI4XkNi2A47 my5XXiV21560VhcLvR/DdwiaDWOYfKfocx3cowiD5q/qpOQ0RzWcpy1D4vU9riRSuSX5 6k9/W7oT6OpZvAP0zZf4mf/ONmpxPpwa4lTP+aOIFPjHDPoa1Hh3UlhJHmxpa3qqR04P cMCw== X-Gm-Message-State: AO0yUKV3PwL7ls2IM4bC1o19uyhjLl+x42o8aAatVdXh2C7H/iqZUvF0 V4RnggTkuFHU1xumRT1wGhfjvhf2c6RY2Fk7C6c= X-Google-Smtp-Source: AK7set9zytKR5+kCKJCYMHIKy2yFPqVVftnZbkLN3BuP4qsaD307PwXYopPvTWpiixfmfexbOg2urg== X-Received: by 2002:a17:903:27c8:b0:19c:f232:21ca with SMTP id km8-20020a17090327c800b0019cf23221camr5679677plb.3.1677476869212; Sun, 26 Feb 2023 21:47:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH 47/70] target/rx: Use cpu_psw_z as temp in flags computation Date: Sun, 26 Feb 2023 19:42:10 -1000 Message-Id: <20230227054233.390271-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227054233.390271-1-richard.henderson@linaro.org> References: <20230227054233.390271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677477123743100010 Content-Type: text/plain; charset="utf-8" Since PSW_Z =3D PSW_S, we can move that assignment to the end and use PSW_Z as a temporary while computing PSW_O. Use tcg_constant_i32 instead of tcg_const_i32. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/translate.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 998e6e0b7e..c47aa26893 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -967,14 +967,13 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_r= r *a) /* ret =3D arg1 + arg2 + psw_c */ static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv z; - z =3D tcg_const_i32(0); + TCGv z =3D tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - tcg_gen_xor_i32(z, arg1, arg2); - tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_mov_i32(ret, cpu_psw_s); } =20 @@ -1006,13 +1005,12 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC= _mr *a) /* ret =3D arg1 + arg2 */ static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv z; - z =3D tcg_const_i32(0); + TCGv z =3D tcg_constant_i32(0); tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - tcg_gen_xor_i32(z, arg1, arg2); - tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_mov_i32(ret, cpu_psw_s); } =20 @@ -1042,23 +1040,23 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_AD= D_rrr *a) /* ret =3D arg1 - arg2 */ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) { - TCGv temp; tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); - tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); - temp =3D tcg_temp_new_i32(); - tcg_gen_xor_i32(temp, arg1, arg2); - tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); + tcg_gen_xor_i32(cpu_psw_z, arg1, arg2); + tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, cpu_psw_z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); /* CMP not required return */ if (ret) { tcg_gen_mov_i32(ret, cpu_psw_s); } } + static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) { rx_sub(NULL, arg1, arg2); } + /* ret =3D arg1 - arg2 - !psw_c */ /* -> ret =3D arg1 + ~arg2 + psw_c */ static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) --=20 2.34.1