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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id im16-20020a170902bb1000b0019a983f0119sm3553986plb.307.2023.02.26.21.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Feb 2023 21:48:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=476w+C7PuuVulk9A7rXUzrh5adLE+NiyBcTZuZG8peU=; b=Hm4tUAxNrMmlyFbhxyYjt/JqVZIK1EPmiEs45p6s3r9J14OpN5vhzDzjKSBE5szYqa k1o0S6SStX1RU68HHyWQrc5K+PtU27FnFq5E8mkKns1u3gTIecLml16GUPN90GWrOvjq Zm9p6PQZcGg6zfYdxOfimJ3BRwDSxAZ7l3h/apr7nQ32EGbOeOGIvjrMFC1kS7OyJY/s ci6w0dD+8vLQypypCpD7I+3KWWEPMQNSDWA4eFR5cL42/GC7ns4C3tSEc4vNEXMrAgSL 3xyj/1GPmha57pFfV7itRDjDb+EyHjIVuQxBgFVECb6FuxFb7ZKSWtHt7a0UFIPx+lWo rP8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=476w+C7PuuVulk9A7rXUzrh5adLE+NiyBcTZuZG8peU=; b=TsChwbkqfkcxbRdwvLdAduPiHDLHKNRvL7ip2kIILtZoYxe0SnLDYAcfiIcgSqRKie BcBJCXqo3Scg4QRujn5qzJcc2nRraAchyGcCG/uthSTMV+rEhAs/MkonLb2voRDnt6I7 Dlc5EgusRu0TomreLxiRlETmnFyW4prORb9c3sDa4bs0vVeppuQUVN4VqHx+eZX6pSHp +YMFvWXhLJ3M70AlMC5suBchVfVz2wfvcQglc9vnDfuA7tiTPKRDAUHrwDvhT/rnAcE1 4pibv9WIvMCQJQ6rv7EIcGOTyK5zWYtAnZ9SLanXfTa8y918+rQh5/3RJ5TNuVFPo+gA R2fQ== X-Gm-Message-State: AO0yUKU28E3ZjFtD+1iuA+8XaSVdV8Y+M3ZBE23QIAr4o5LQTZZbly8a S2tiLSxVvLf0B1lE6Fu8lxFcWPeGZYx4WrdaGDXLCg== X-Google-Smtp-Source: AK7set+wvXjr8pkNWyblauoxWYRackYkXrHSSOQIXOU8MXJdCoqPW+um8z+6XYParSva5ykT2jOdaQ== X-Received: by 2002:a17:902:ab0c:b0:19c:d316:309a with SMTP id ik12-20020a170902ab0c00b0019cd316309amr8515832plb.4.1677476890449; Sun, 26 Feb 2023 21:48:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, jcmvbkbc@gmail.com, kbastian@mail.uni-paderborn.de, ysato@users.sourceforge.jp, gaosong@loongson.cn, jiaxun.yang@flygoat.com, tsimpson@quicinc.com, ale@rev.ng, mrolnik@gmail.com, edgar.iglesias@gmail.com Subject: [PATCH 55/70] target/sparc: Avoid tcg_const_{tl,i32} Date: Sun, 26 Feb 2023 19:42:18 -1000 Message-Id: <20230227054233.390271-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227054233.390271-1-richard.henderson@linaro.org> References: <20230227054233.390271-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::642; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x642.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677486221538100003 Content-Type: text/plain; charset="utf-8" All remaining uses are strictly read-only. Signed-off-by: Richard Henderson Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/sparc/translate.c | 80 +++++++++++++++++++--------------------- 1 file changed, 38 insertions(+), 42 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 925023adef..137bdc5159 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -550,7 +550,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, T= CGv src2) if (!(env->y & 1)) T1 =3D 0; */ - zero =3D tcg_const_tl(0); + zero =3D tcg_constant_tl(0); tcg_gen_andi_tl(cpu_cc_src, src1, 0xffffffff); tcg_gen_andi_tl(r_temp, cpu_y, 0x1); tcg_gen_andi_tl(cpu_cc_src2, src2, 0xffffffff); @@ -928,8 +928,8 @@ static void gen_branch_n(DisasContext *dc, target_ulong= pc1) tcg_gen_mov_tl(cpu_pc, cpu_npc); =20 tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); - t =3D tcg_const_tl(pc1); - z =3D tcg_const_tl(0); + t =3D tcg_constant_tl(pc1); + z =3D tcg_constant_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, z, t, cpu_npc); =20 dc->pc =3D DYNAMIC_PC; @@ -938,9 +938,9 @@ static void gen_branch_n(DisasContext *dc, target_ulong= pc1) =20 static inline void gen_generic_branch(DisasContext *dc) { - TCGv npc0 =3D tcg_const_tl(dc->jump_pc[0]); - TCGv npc1 =3D tcg_const_tl(dc->jump_pc[1]); - TCGv zero =3D tcg_const_tl(0); + TCGv npc0 =3D tcg_constant_tl(dc->jump_pc[0]); + TCGv npc1 =3D tcg_constant_tl(dc->jump_pc[1]); + TCGv zero =3D tcg_constant_tl(0); =20 tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, cpu_cond, zero, npc0, npc1); } @@ -981,18 +981,14 @@ static inline void save_state(DisasContext *dc) =20 static void gen_exception(DisasContext *dc, int which) { - TCGv_i32 t; - save_state(dc); - t =3D tcg_const_i32(which); - gen_helper_raise_exception(cpu_env, t); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(which)); dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_check_align(TCGv addr, int mask) { - TCGv_i32 r_mask =3D tcg_const_i32(mask); - gen_helper_check_align(cpu_env, addr, r_mask); + gen_helper_check_align(cpu_env, addr, tcg_constant_i32(mask)); } =20 static inline void gen_mov_pc_npc(DisasContext *dc) @@ -1074,7 +1070,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, cmp->cond =3D logic_cond[cond]; do_compare_dst_0: cmp->is_bool =3D false; - cmp->c2 =3D tcg_const_tl(0); + cmp->c2 =3D tcg_constant_tl(0); #ifdef TARGET_SPARC64 if (!xcc) { cmp->c1 =3D tcg_temp_new(); @@ -1127,7 +1123,7 @@ static void gen_compare(DisasCompare *cmp, bool xcc, = unsigned int cond, cmp->cond =3D TCG_COND_NE; cmp->is_bool =3D true; cmp->c1 =3D r_dst =3D tcg_temp_new(); - cmp->c2 =3D tcg_const_tl(0); + cmp->c2 =3D tcg_constant_tl(0); =20 switch (cond) { case 0x0: @@ -1192,7 +1188,7 @@ static void gen_fcompare(DisasCompare *cmp, unsigned = int cc, unsigned int cond) cmp->cond =3D TCG_COND_NE; cmp->is_bool =3D true; cmp->c1 =3D r_dst =3D tcg_temp_new(); - cmp->c2 =3D tcg_const_tl(0); + cmp->c2 =3D tcg_constant_tl(0); =20 switch (cc) { default: @@ -1307,7 +1303,7 @@ static void gen_compare_reg(DisasCompare *cmp, int co= nd, TCGv r_src) cmp->cond =3D tcg_invert_cond(gen_tcg_cond_reg[cond]); cmp->is_bool =3D false; cmp->c1 =3D r_src; - cmp->c2 =3D tcg_const_tl(0); + cmp->c2 =3D tcg_constant_tl(0); } =20 static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) @@ -1908,7 +1904,7 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv= src, =20 static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) { - TCGv m1 =3D tcg_const_tl(0xff); + TCGv m1 =3D tcg_constant_tl(0xff); gen_address_mask(dc, addr); tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); } @@ -2163,8 +2159,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TC= Gv addr, break; default: { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(memop); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2217,7 +2213,7 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TC= Gv addr, { TCGv saddr =3D tcg_temp_new(); TCGv daddr =3D tcg_temp_new(); - TCGv four =3D tcg_const_tl(4); + TCGv four =3D tcg_constant_tl(4); TCGv_i32 tmp =3D tcg_temp_new_i32(); int i; =20 @@ -2236,8 +2232,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TC= Gv addr, #endif default: { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(memop & MO_SIZE); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(memop & MO_SIZE); =20 save_state(dc); #ifdef TARGET_SPARC64 @@ -2313,15 +2309,15 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv d= st, TCGv addr, int insn) if (tb_cflags(dc->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(cpu_env); } else { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(MO_UB); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(MO_UB); TCGv_i64 s64, t64; =20 save_state(dc); t64 =3D tcg_temp_new_i64(); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); =20 - s64 =3D tcg_const_i64(0xff); + s64 =3D tcg_constant_i64(0xff); gen_helper_st_asi(cpu_env, addr, s64, r_asi, r_mop); =20 tcg_gen_trunc_i64_tl(dst, t64); @@ -2382,7 +2378,7 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, =20 /* The first operation checks required alignment. */ memop =3D da.memop | MO_ALIGN_64; - eight =3D tcg_const_tl(8); + eight =3D tcg_constant_tl(8); for (i =3D 0; ; ++i) { tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da.mem_idx, memop); @@ -2409,8 +2405,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, =20 default: { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(da.memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); =20 save_state(dc); /* According to the table in the UA2011 manual, the only @@ -2491,7 +2487,7 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, =20 /* The first operation checks required alignment. */ memop =3D da.memop | MO_ALIGN_64; - eight =3D tcg_const_tl(8); + eight =3D tcg_constant_tl(8); for (i =3D 0; ; ++i) { tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da.mem_idx, memop); @@ -2566,8 +2562,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) real hardware allows others. This can be seen with e.g. FreeBSD 10.3 wrt ASI_IC_TAG. */ { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(da.memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 save_state(dc); @@ -2625,8 +2621,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(da.memop); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(da.memop); TCGv_i64 t64 =3D tcg_temp_new_i64(); =20 /* See above. */ @@ -2686,8 +2682,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr,= int insn, int rd) break; default: { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(MO_UQ); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ); =20 save_state(dc); gen_helper_ld_asi(t64, cpu_env, addr, r_asi, r_mop); @@ -2724,7 +2720,7 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, as a cacheline-style operation. */ { TCGv d_addr =3D tcg_temp_new(); - TCGv eight =3D tcg_const_tl(8); + TCGv eight =3D tcg_constant_tl(8); int i; =20 tcg_gen_andi_tl(d_addr, addr, -8); @@ -2736,8 +2732,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, T= CGv addr, break; default: { - TCGv_i32 r_asi =3D tcg_const_i32(da.asi); - TCGv_i32 r_mop =3D tcg_const_i32(MO_UQ); + TCGv_i32 r_asi =3D tcg_constant_i32(da.asi); + TCGv_i32 r_mop =3D tcg_constant_i32(MO_UQ); =20 save_state(dc); gen_helper_st_asi(cpu_env, addr, t64, r_asi, r_mop); @@ -2786,7 +2782,7 @@ static void gen_fmovs(DisasContext *dc, DisasCompare = *cmp, int rd, int rs) s1 =3D gen_load_fpr_F(dc, rs); s2 =3D gen_load_fpr_F(dc, rd); dst =3D gen_dest_fpr_F(dc); - zero =3D tcg_const_i32(0); + zero =3D tcg_constant_i32(0); =20 tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); =20 @@ -3215,7 +3211,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_i32 r_const; =20 r_tickptr =3D tcg_temp_new_ptr(); - r_const =3D tcg_const_i32(dc->mem_idx); + r_const =3D tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { @@ -3267,7 +3263,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_i32 r_const; =20 r_tickptr =3D tcg_temp_new_ptr(); - r_const =3D tcg_const_i32(dc->mem_idx); + r_const =3D tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { @@ -3397,7 +3393,7 @@ static void disas_sparc_insn(DisasContext * dc, unsig= ned int insn) TCGv_i32 r_const; =20 r_tickptr =3D tcg_temp_new_ptr(); - r_const =3D tcg_const_i32(dc->mem_idx); + r_const =3D tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { --=20 2.34.1