From nobody Fri May 3 19:16:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1677515558; cv=none; d=zohomail.com; s=zohoarc; b=H8qgEV2F/MSBWP+GX3PE/o1Rmn/IEm4I89V1aCjsMsPXZbNUZEe4DBbr0ORZ6dIEN246RwFrAmKnDMMeUG1Cvoj+KnoZsHmcyt7NS6i4jlh42r+TeG5nkSOaL4WKUUQorlJ5HBPSBctOPDU0czuGfuBeBUSDrD5vBhErBFjW2Vo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677515558; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YjBawQb3YszpKRJNAalsvZmRw7p5AW3SQ0HnCxU7MlU=; b=OizfALO7MGMqqGezPPUTB+Sybd5l5zR9IPnFJwZoqQfclFsOynWNYpAlVd6mbv3zlLXuGS1df8fuxop0fhK26YnbVmNg7AVyiVZCBhtvJVG/YkyTIFGp7rBSXvxhDlHzO1pthYopYh3SM9wpTeKtJuhHddS7XU+bz1iXM+kTp7c= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16775155588094.0953309305311905; Mon, 27 Feb 2023 08:32:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWgQU-0004WZ-0L; Mon, 27 Feb 2023 11:32:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWgQS-0004RU-8i for qemu-devel@nongnu.org; Mon, 27 Feb 2023 11:32:32 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWgQQ-0004s9-CO for qemu-devel@nongnu.org; Mon, 27 Feb 2023 11:32:32 -0500 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PQQvk2Kcvz67Zn3; Tue, 28 Feb 2023 00:30:10 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 27 Feb 2023 16:32:27 +0000 To: , Michael Tsirkin , Fan Ni CC: Ben Widawsky , , , Ira Weiny , Gregory Price , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mike Maslenkin , Dave Jiang Subject: [PATCH v4 1/2] tests/qtest/cxl-test: whitespace, line ending cleanup Date: Mon, 27 Feb 2023 16:31:56 +0000 Message-ID: <20230227163157.6621-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230227163157.6621-1-Jonathan.Cameron@huawei.com> References: <20230227163157.6621-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100006.china.huawei.com (7.191.160.224) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1677515559623100003 Content-Type: text/plain; charset="utf-8" From: Gregory Price Defines are starting to exceed line length limits, align them for cleanliness before making modifications. Signed-off-by: Gregory Price Signed-off-by: Jonathan Cameron Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/qtest/cxl-test.c | 84 +++++++++++++++++++++++------------------- 1 file changed, 46 insertions(+), 38 deletions(-) diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index 61f25a72b6..eda2bbbbe6 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -8,50 +8,58 @@ #include "qemu/osdep.h" #include "libqtest-single.h" =20 -#define QEMU_PXB_CMD "-machine q35,cxl=3Don " \ - "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52 = " \ - "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.size=3D4G " +#define QEMU_PXB_CMD \ + "-machine q35,cxl=3Don " \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52 " \ + "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.size=3D4G " =20 -#define QEMU_2PXB_CMD "-machine q35,cxl=3Don " \ - "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52= " \ - "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53= " \ - "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1= =3Dcxl.1,cxl-fmw.0.size=3D4G " +#define QEMU_2PXB_CMD \ + "-machine q35,cxl=3Don " \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52 " \ + "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53 " \ + "-M cxl-fmw.0.targets.0=3Dcxl.0,cxl-fmw.0.targets.1=3Dcxl.1,cxl-fmw.0.= size=3D4G " =20 -#define QEMU_RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " +#define QEMU_RP \ + "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " =20 /* Dual ports on first pxb */ -#define QEMU_2RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0= " \ - "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot=3D1= " +#define QEMU_2RP \ + "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " \ + "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot=3D1 " =20 /* Dual ports on each of the pxb instances */ -#define QEMU_4RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0= " \ - "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot=3D1= " \ - "-device cxl-rp,id=3Drp2,bus=3Dcxl.1,chassis=3D0,slot=3D2= " \ - "-device cxl-rp,id=3Drp3,bus=3Dcxl.1,chassis=3D0,slot=3D3= " - -#define QEMU_T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,= size=3D256M " \ - "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size= =3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0= ,id=3Dcxl-pmem0 " - -#define QEMU_2T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ - "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ - "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ - "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " - -#define QEMU_4T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ - "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ - "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ - "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " \ - "-object memory-backend-file,id=3Dcxl-mem2,mem-path=3D%s= ,size=3D256M " \ - "-object memory-backend-file,id=3Dlsa2,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp2,memdev=3Dcxl-mem2,lsa=3Dlsa= 2,id=3Dcxl-pmem2 " \ - "-object memory-backend-file,id=3Dcxl-mem3,mem-path=3D%s= ,size=3D256M " \ - "-object memory-backend-file,id=3Dlsa3,mem-path=3D%s,siz= e=3D256M " \ - "-device cxl-type3,bus=3Drp3,memdev=3Dcxl-mem3,lsa=3Dlsa= 3,id=3Dcxl-pmem3 " +#define QEMU_4RP \ + "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " \ + "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot=3D1 " \ + "-device cxl-rp,id=3Drp2,bus=3Dcxl.1,chassis=3D0,slot=3D2 " \ + "-device cxl-rp,id=3Drp3,bus=3Dcxl.1,chassis=3D0,slot=3D3 " + +#define QEMU_T3D \ + "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0,id=3Dcxl-pme= m0 " + +#define QEMU_2T3D \ + "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0,id=3Dcxl-pme= m0 " \ + "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa1,id=3Dcxl-pme= m1 " + +#define QEMU_4T3D \ + "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0,id=3Dcxl-pme= m0 " \ + "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa1,id=3Dcxl-pme= m1 " \ + "-object memory-backend-file,id=3Dcxl-mem2,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa2,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp2,memdev=3Dcxl-mem2,lsa=3Dlsa2,id=3Dcxl-pme= m2 " \ + "-object memory-backend-file,id=3Dcxl-mem3,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa3,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp3,memdev=3Dcxl-mem3,lsa=3Dlsa3,id=3Dcxl-pme= m3 " =20 static void cxl_basic_hb(void) { --=20 2.37.2 From nobody Fri May 3 19:16:22 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass 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for qemu-devel@nongnu.org; Mon, 27 Feb 2023 11:33:03 -0500 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.201]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PQQyt53kZz6J701; Tue, 28 Feb 2023 00:32:54 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 27 Feb 2023 16:32:58 +0000 To: , Michael Tsirkin , Fan Ni CC: Ben Widawsky , , , Ira Weiny , Gregory Price , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Mike Maslenkin , Dave Jiang Subject: [PATCH v4 2/2] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) Date: Mon, 27 Feb 2023 16:31:57 +0000 Message-ID: <20230227163157.6621-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230227163157.6621-1-Jonathan.Cameron@huawei.com> References: <20230227163157.6621-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100006.china.huawei.com (7.191.160.224) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1677515595849100003 Content-Type: text/plain; charset="utf-8" From: Gregory Price This commit enables each CXL Type-3 device to contain one volatile memory region and one persistent region. Two new properties have been added to cxl-type3 device initialization: [volatile-memdev] and [persistent-memdev] The existing [memdev] property has been deprecated and will default the memory region to a persistent memory region (although a user may assign the region to a ram or file backed region). It cannot be used in combination with the new [persistent-memdev] property. Partitioning volatile memory from persistent memory is not yet supported. Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info. Signed-off-by: Gregory Price Reviewed-by: Davidlohr Bueso Reviewed-by: Fan Ni Tested-by: Fan Ni Signed-off-by: Jonathan Cameron --- v4: - In the code that is being touched, add the missing little endian conversi= ons. Note that only little endian architectures are supported so far, so there= is no need to fix these urgently. However, it seems sensible to clean up wh= ilst we are here - Add entry to docs/about/deprecated.rst (Philippe) --- docs/about/deprecated.rst | 8 + docs/system/devices/cxl.rst | 49 ++++-- hw/cxl/cxl-mailbox-utils.c | 32 ++-- hw/mem/cxl_type3.c | 294 +++++++++++++++++++++++++-------- include/hw/cxl/cxl_device.h | 11 +- tests/qtest/bios-tables-test.c | 8 +- tests/qtest/cxl-test.c | 76 +++++++-- 7 files changed, 364 insertions(+), 114 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 15084f7bea..366d479498 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -273,6 +273,14 @@ from Intel that was not properly allocated. Since vers= ion 5.2, the controller has used a properly allocated identifier. Deprecate the ``use-intel-id`` machine compatibility parameter. =20 +``-device cxl-type3,memdev=3Dxxxx`` (since 8.0) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The ``cxl-type3`` device initially only used a single memory backend. With +the addition of volatile memory support, it is now necessary to distinguish +between persistent and volatile memory backends. As such, memdev is depre= cated +in favor of persistent-memdev. + =20 Block device options '''''''''''''''''''' diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index f25783a4ec..89a41cff73 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -300,7 +300,7 @@ Example topology involving a switch:: =20 Example command lines --------------------- -A very simple setup with just one directly attached CXL Type 3 device:: +A very simple setup with just one directly attached CXL Type 3 Persistent = Memory device:: =20 qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ ... @@ -308,7 +308,28 @@ A very simple setup with just one directly attached CX= L Type 3 device:: -object memory-backend-file,id=3Dcxl-lsa1,share=3Don,mem-path=3D/tmp/lsa= .raw,size=3D256M \ -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ - -device cxl-type3,bus=3Droot_port13,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id= =3Dcxl-pmem0 \ + -device cxl-type3,bus=3Droot_port13,persistent-memdev=3Dcxl-mem1,lsa=3Dc= xl-lsa1,id=3Dcxl-pmem0 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G + +A very simple setup with just one directly attached CXL Type 3 Volatile Me= mory device:: + + qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ + ... + -object memory-backend-ram,id=3Dvmem0,share=3Don,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ + -device cxl-type3,bus=3Droot_port13,volatile-memdev=3Dvmem0,id=3Dcxl-vme= m0 \ + -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G + +The same volatile setup may optionally include an LSA region:: + + qemu-system-aarch64 -M virt,gic-version=3D3,cxl=3Don -m 4g,maxmem=3D8G,s= lots=3D8 -cpu max \ + ... + -object memory-backend-ram,id=3Dvmem0,share=3Don,size=3D256M \ + -object memory-backend-file,id=3Dcxl-lsa0,share=3Don,mem-path=3D/tmp/lsa= .raw,size=3D256M \ + -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ + -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ + -device cxl-type3,bus=3Droot_port13,volatile-memdev=3Dvmem0,lsa=3Dcxl-ls= a0,id=3Dcxl-vmem0 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G =20 A setup suitable for 4 way interleave. Only one fixed window provided, to = enable 2 way @@ -328,13 +349,13 @@ the CXL Type3 device directly attached (no switches).= :: -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id=3Dcxl.1 \ -device pxb-cxl,bus_nr=3D222,bus=3Dpcie.0,id=3Dcxl.2 \ -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Droot_port13,chassis=3D0,slot=3D= 2 \ - -device cxl-type3,bus=3Droot_port13,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id= =3Dcxl-pmem0 \ + -device cxl-type3,bus=3Droot_port13,persistent-memdev=3Dcxl-mem1,lsa=3Dc= xl-lsa1,id=3Dcxl-pmem0 \ -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port14,chassis=3D0,slot=3D= 3 \ - -device cxl-type3,bus=3Droot_port14,memdev=3Dcxl-mem2,lsa=3Dcxl-lsa2,id= =3Dcxl-pmem1 \ + -device cxl-type3,bus=3Droot_port14,persistent-memdev=3Dcxl-mem2,lsa=3Dc= xl-lsa2,id=3Dcxl-pmem1 \ -device cxl-rp,port=3D0,bus=3Dcxl.2,id=3Droot_port15,chassis=3D0,slot=3D= 5 \ - -device cxl-type3,bus=3Droot_port15,memdev=3Dcxl-mem3,lsa=3Dcxl-lsa3,id= =3Dcxl-pmem2 \ + -device cxl-type3,bus=3Droot_port15,persistent-memdev=3Dcxl-mem3,lsa=3Dc= xl-lsa3,id=3Dcxl-pmem2 \ -device cxl-rp,port=3D1,bus=3Dcxl.2,id=3Droot_port16,chassis=3D0,slot=3D= 6 \ - -device cxl-type3,bus=3Droot_port16,memdev=3Dcxl-mem4,lsa=3Dcxl-lsa4,id= =3Dcxl-pmem3 \ + -device cxl-type3,bus=3Droot_port16,persistent-memdev=3Dcxl-mem4,lsa=3Dc= xl-lsa4,id=3Dcxl-pmem3 \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.targets.1=3Dcxl.2,cxl-fmw.0.siz= e=3D4G,cxl-fmw.0.interleave-granularity=3D8k =20 An example of 4 devices below a switch suitable for 1, 2 or 4 way interlea= ve:: @@ -354,15 +375,23 @@ An example of 4 devices below a switch suitable for 1= , 2 or 4 way interleave:: -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Droot_port1,chassis=3D0,slot=3D1= \ -device cxl-upstream,bus=3Droot_port0,id=3Dus0 \ -device cxl-downstream,port=3D0,bus=3Dus0,id=3Dswport0,chassis=3D0,slot= =3D4 \ - -device cxl-type3,bus=3Dswport0,memdev=3Dcxl-mem0,lsa=3Dcxl-lsa0,id=3Dcx= l-pmem0,size=3D256M \ + -device cxl-type3,bus=3Dswport0,persistent-memdev=3Dcxl-mem0,lsa=3Dcxl-l= sa0,id=3Dcxl-pmem0,size=3D256M \ -device cxl-downstream,port=3D1,bus=3Dus0,id=3Dswport1,chassis=3D0,slot= =3D5 \ - -device cxl-type3,bus=3Dswport1,memdev=3Dcxl-mem1,lsa=3Dcxl-lsa1,id=3Dcx= l-pmem1,size=3D256M \ + -device cxl-type3,bus=3Dswport1,persistent-memdev=3Dcxl-mem1,lsa=3Dcxl-l= sa1,id=3Dcxl-pmem1,size=3D256M \ -device cxl-downstream,port=3D2,bus=3Dus0,id=3Dswport2,chassis=3D0,slot= =3D6 \ - -device cxl-type3,bus=3Dswport2,memdev=3Dcxl-mem2,lsa=3Dcxl-lsa2,id=3Dcx= l-pmem2,size=3D256M \ + -device cxl-type3,bus=3Dswport2,persistent-memdev=3Dcxl-mem2,lsa=3Dcxl-l= sa2,id=3Dcxl-pmem2,size=3D256M \ -device cxl-downstream,port=3D3,bus=3Dus0,id=3Dswport3,chassis=3D0,slot= =3D7 \ - -device cxl-type3,bus=3Dswport3,memdev=3Dcxl-mem3,lsa=3Dcxl-lsa3,id=3Dcx= l-pmem3,size=3D256M \ + -device cxl-type3,bus=3Dswport3,persistent-memdev=3Dcxl-mem3,lsa=3Dcxl-l= sa3,id=3Dcxl-pmem3,size=3D256M \ -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.size=3D4G,cxl-fmw.0.interleave-= granularity=3D4k =20 +Deprecations +------------ + +The Type 3 device [memdev] attribute has been deprecated in favor of the +[persistent-memdev] attributes. [memdev] will default to a persistent memo= ry +device for backward compatibility and is incapable of being used in combin= ation +with [persistent-memdev]. + Kernel Configuration Options ---------------------------- =20 diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c index 206e04a4b8..ed663cc04a 100644 --- a/hw/cxl/cxl-mailbox-utils.c +++ b/hw/cxl/cxl-mailbox-utils.c @@ -141,7 +141,8 @@ static ret_code cmd_firmware_update_get_info(struct cxl= _cmd *cmd, } QEMU_PACKED *fw_info; QEMU_BUILD_BUG_ON(sizeof(*fw_info) !=3D 0x50); =20 - if (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER) { + if ((cxl_dstate->vmem_size < CXL_CAPACITY_MULTIPLIER) || + (cxl_dstate->pmem_size < CXL_CAPACITY_MULTIPLIER)) { return CXL_MBOX_INTERNAL_ERROR; } =20 @@ -288,21 +289,21 @@ static ret_code cmd_identify_memory_device(struct cxl= _cmd *cmd, =20 CXLType3Dev *ct3d =3D container_of(cxl_dstate, CXLType3Dev, cxl_dstate= ); CXLType3Class *cvc =3D CXL_TYPE3_GET_CLASS(ct3d); - uint64_t size =3D cxl_dstate->pmem_size; =20 - if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) { + if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER))= || + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= ) { return CXL_MBOX_INTERNAL_ERROR; } =20 id =3D (void *)cmd->payload; memset(id, 0, sizeof(*id)); =20 - /* PMEM only */ snprintf(id->fw_revision, 0x10, "BWFW VERSION %02d", 0); =20 - id->total_capacity =3D size / CXL_CAPACITY_MULTIPLIER; - id->persistent_capacity =3D size / CXL_CAPACITY_MULTIPLIER; - id->lsa_size =3D cvc->get_lsa_size(ct3d); + stq_le_p(&id->total_capacity, cxl_dstate->mem_size / CXL_CAPACITY_MULT= IPLIER); + stq_le_p(&id->persistent_capacity, cxl_dstate->pmem_size / CXL_CAPACIT= Y_MULTIPLIER); + stq_le_p(&id->volatile_capacity, cxl_dstate->vmem_size / CXL_CAPACITY_= MULTIPLIER); + stl_le_p(&id->lsa_size, cvc->get_lsa_size(ct3d)); =20 *len =3D sizeof(*id); return CXL_MBOX_SUCCESS; @@ -319,17 +320,20 @@ static ret_code cmd_ccls_get_partition_info(struct cx= l_cmd *cmd, uint64_t next_pmem; } QEMU_PACKED *part_info =3D (void *)cmd->payload; QEMU_BUILD_BUG_ON(sizeof(*part_info) !=3D 0x20); - uint64_t size =3D cxl_dstate->pmem_size; =20 - if (!QEMU_IS_ALIGNED(size, CXL_CAPACITY_MULTIPLIER)) { + if ((!QEMU_IS_ALIGNED(cxl_dstate->vmem_size, CXL_CAPACITY_MULTIPLIER))= || + (!QEMU_IS_ALIGNED(cxl_dstate->pmem_size, CXL_CAPACITY_MULTIPLIER))= ) { return CXL_MBOX_INTERNAL_ERROR; } =20 - /* PMEM only */ - part_info->active_vmem =3D 0; - part_info->next_vmem =3D 0; - part_info->active_pmem =3D size / CXL_CAPACITY_MULTIPLIER; - part_info->next_pmem =3D 0; + stq_le_p(&part_info->active_vmem, cxl_dstate->vmem_size / CXL_CAPACITY= _MULTIPLIER); + /* + * When both next_vmem and next_pmem are 0, there is no pending change= to + * partitioning. + */ + stq_le_p(&part_info->next_vmem, 0); + stq_le_p(&part_info->active_pmem, cxl_dstate->pmem_size / CXL_CAPACITY= _MULTIPLIER); + stq_le_p(&part_info->next_pmem, 0); =20 *len =3D sizeof(*part_info); return CXL_MBOX_SUCCESS; diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index abe60b362c..572ad47fa2 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -31,7 +31,8 @@ enum { }; =20 static int ct3_build_cdat_entries_for_mr(CDATSubHeader **cdat_table, - int dsmad_handle, MemoryRegion *m= r) + int dsmad_handle, MemoryRegion *m= r, + bool is_pmem, uint64_t dpa_base) { g_autofree CDATDsmas *dsmas =3D NULL; g_autofree CDATDslbis *dslbis0 =3D NULL; @@ -50,8 +51,8 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader **= cdat_table, .length =3D sizeof(*dsmas), }, .DSMADhandle =3D dsmad_handle, - .flags =3D CDAT_DSMAS_FLAG_NV, - .DPA_base =3D 0, + .flags =3D is_pmem ? CDAT_DSMAS_FLAG_NV : 0, + .DPA_base =3D dpa_base, .DPA_length =3D int128_get64(mr->size), }; =20 @@ -130,8 +131,11 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeader= **cdat_table, .length =3D sizeof(*dsemts), }, .DSMAS_handle =3D dsmad_handle, - /* Reserved - the non volatile from DSMAS matters */ - .EFI_memory_type_attr =3D 2, + /* + * NV: Reserved - the non volatile from DSMAS matters + * V: EFI_MEMORY_SP + */ + .EFI_memory_type_attr =3D is_pmem ? 2 : 1, .DPA_offset =3D 0, .DPA_length =3D int128_get64(mr->size), }; @@ -150,33 +154,66 @@ static int ct3_build_cdat_entries_for_mr(CDATSubHeade= r **cdat_table, static int ct3_build_cdat_table(CDATSubHeader ***cdat_table, void *priv) { g_autofree CDATSubHeader **table =3D NULL; - MemoryRegion *nonvolatile_mr; CXLType3Dev *ct3d =3D priv; + MemoryRegion *volatile_mr =3D NULL, *nonvolatile_mr =3D NULL; int dsmad_handle =3D 0; - int rc; + int cur_ent =3D 0; + int len =3D 0; + int rc, i; =20 - if (!ct3d->hostmem) { + if (!ct3d->hostpmem && !ct3d->hostvmem) { return 0; } =20 - nonvolatile_mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!nonvolatile_mr) { - return -EINVAL; + if (ct3d->hostvmem) { + volatile_mr =3D host_memory_backend_get_memory(ct3d->hostvmem); + if (!volatile_mr) { + return -EINVAL; + } + len +=3D CT3_CDAT_NUM_ENTRIES; + } + + if (ct3d->hostpmem) { + nonvolatile_mr =3D host_memory_backend_get_memory(ct3d->hostpmem); + if (!nonvolatile_mr) { + return -EINVAL; + } + len +=3D CT3_CDAT_NUM_ENTRIES; } =20 - table =3D g_malloc0(CT3_CDAT_NUM_ENTRIES * sizeof(*table)); + table =3D g_malloc0(len * sizeof(*table)); if (!table) { return -ENOMEM; } =20 - rc =3D ct3_build_cdat_entries_for_mr(table, dsmad_handle++, nonvolatil= e_mr); - if (rc < 0) { - return rc; + /* Now fill them in */ + if (volatile_mr) { + rc =3D ct3_build_cdat_entries_for_mr(table, dsmad_handle++, volati= le_mr, + false, 0); + if (rc < 0) { + return rc; + } + cur_ent =3D CT3_CDAT_NUM_ENTRIES; } =20 + if (nonvolatile_mr) { + rc =3D ct3_build_cdat_entries_for_mr(&(table[cur_ent]), dsmad_hand= le++, + nonvolatile_mr, true, (volatile_mr ? volatile_mr->size : 0= )); + if (rc < 0) { + goto error_cleanup; + } + cur_ent +=3D CT3_CDAT_NUM_ENTRIES; + } + assert(len =3D=3D cur_ent); + *cdat_table =3D g_steal_pointer(&table); =20 - return CT3_CDAT_NUM_ENTRIES; + return len; +error_cleanup: + for (i =3D 0; i < cur_ent; i++) { + g_free(table[i]); + } + return rc; } =20 static void ct3_free_cdat_table(CDATSubHeader **cdat_table, int num, void = *priv) @@ -264,16 +301,42 @@ static void build_dvsecs(CXLType3Dev *ct3d) { CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; uint8_t *dvsec; + uint32_t range1_size_hi, range1_size_lo, + range1_base_hi =3D 0, range1_base_lo =3D 0, + range2_size_hi =3D 0, range2_size_lo =3D 0, + range2_base_hi =3D 0, range2_base_lo =3D 0; + + /* + * Volatile memory is mapped as (0x0) + * Persistent memory is mapped at (volatile->size) + */ + if (ct3d->hostvmem) { + range1_size_hi =3D ct3d->hostvmem->size >> 32; + range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->hostvmem->size & 0xF0000000); + if (ct3d->hostpmem) { + range2_size_hi =3D ct3d->hostpmem->size >> 32; + range2_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->hostpmem->size & 0xF0000000); + } + } else { + range1_size_hi =3D ct3d->hostpmem->size >> 32; + range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | + (ct3d->hostpmem->size & 0xF0000000); + } =20 dvsec =3D (uint8_t *)&(CXLDVSECDevice){ .cap =3D 0x1e, .ctrl =3D 0x2, .status2 =3D 0x2, - .range1_size_hi =3D ct3d->hostmem->size >> 32, - .range1_size_lo =3D (2 << 5) | (2 << 2) | 0x3 | - (ct3d->hostmem->size & 0xF0000000), - .range1_base_hi =3D 0, - .range1_base_lo =3D 0, + .range1_size_hi =3D range1_size_hi, + .range1_size_lo =3D range1_size_lo, + .range1_base_hi =3D range1_base_hi, + .range1_base_lo =3D range1_base_lo, + .range2_size_hi =3D range2_size_hi, + .range2_size_lo =3D range2_size_lo, + .range2_base_hi =3D range2_base_hi, + .range2_base_lo =3D range2_base_lo, }; cxl_component_create_dvsec(cxl_cstate, CXL2_TYPE3_DEVICE, PCIE_CXL_DEVICE_DVSEC_LENGTH, @@ -492,36 +555,69 @@ static void ct3d_reg_write(void *opaque, hwaddr offse= t, uint64_t value, static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { DeviceState *ds =3D DEVICE(ct3d); - MemoryRegion *mr; - char *name; =20 - if (!ct3d->hostmem) { - error_setg(errp, "memdev property must be set"); + if (!ct3d->hostmem && !ct3d->hostvmem && !ct3d->hostpmem) { + error_setg(errp, "at least one memdev property must be set"); return false; + } else if (ct3d->hostmem && ct3d->hostpmem) { + error_setg(errp, "[memdev] cannot be used with new " + "[persistent-memdev] property"); + return false; + } else if (ct3d->hostmem) { + /* Use of hostmem property implies pmem */ + ct3d->hostpmem =3D ct3d->hostmem; + ct3d->hostmem =3D NULL; } =20 - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { - error_setg(errp, "memdev property must be set"); + if (ct3d->hostpmem && !ct3d->lsa) { + error_setg(errp, "lsa property must be set for persistent devices"= ); return false; } - memory_region_set_nonvolatile(mr, true); - memory_region_set_enabled(mr, true); - host_memory_backend_set_mapped(ct3d->hostmem, true); =20 - if (ds->id) { - name =3D g_strdup_printf("cxl-type3-dpa-space:%s", ds->id); - } else { - name =3D g_strdup("cxl-type3-dpa-space"); + if (ct3d->hostvmem) { + MemoryRegion *vmr; + char *v_name; + + vmr =3D host_memory_backend_get_memory(ct3d->hostvmem); + if (!vmr) { + error_setg(errp, "volatile memdev must have backing device"); + return false; + } + memory_region_set_nonvolatile(vmr, false); + memory_region_set_enabled(vmr, true); + host_memory_backend_set_mapped(ct3d->hostvmem, true); + if (ds->id) { + v_name =3D g_strdup_printf("cxl-type3-dpa-vmem-space:%s", ds->= id); + } else { + v_name =3D g_strdup("cxl-type3-dpa-vmem-space"); + } + address_space_init(&ct3d->hostvmem_as, vmr, v_name); + ct3d->cxl_dstate.vmem_size =3D vmr->size; + ct3d->cxl_dstate.mem_size +=3D vmr->size; + g_free(v_name); } - address_space_init(&ct3d->hostmem_as, mr, name); - g_free(name); =20 - ct3d->cxl_dstate.pmem_size =3D ct3d->hostmem->size; + if (ct3d->hostpmem) { + MemoryRegion *pmr; + char *p_name; =20 - if (!ct3d->lsa) { - error_setg(errp, "lsa property must be set"); - return false; + pmr =3D host_memory_backend_get_memory(ct3d->hostpmem); + if (!pmr) { + error_setg(errp, "persistent memdev must have backing device"); + return false; + } + memory_region_set_nonvolatile(pmr, true); + memory_region_set_enabled(pmr, true); + host_memory_backend_set_mapped(ct3d->hostpmem, true); + if (ds->id) { + p_name =3D g_strdup_printf("cxl-type3-dpa-pmem-space:%s", ds->= id); + } else { + p_name =3D g_strdup("cxl-type3-dpa-pmem-space"); + } + address_space_init(&ct3d->hostpmem_as, pmr, p_name); + ct3d->cxl_dstate.pmem_size =3D pmr->size; + ct3d->cxl_dstate.mem_size +=3D pmr->size; + g_free(p_name); } =20 return true; @@ -607,7 +703,12 @@ err_release_cdat: cxl_doe_cdat_release(cxl_cstate); g_free(regs->special_ops); err_address_space_free: - address_space_destroy(&ct3d->hostmem_as); + if (ct3d->hostpmem) { + address_space_destroy(&ct3d->hostpmem_as); + } + if (ct3d->hostvmem) { + address_space_destroy(&ct3d->hostvmem_as); + } return; } =20 @@ -620,7 +721,12 @@ static void ct3_exit(PCIDevice *pci_dev) pcie_aer_exit(pci_dev); cxl_doe_cdat_release(cxl_cstate); g_free(regs->special_ops); - address_space_destroy(&ct3d->hostmem_as); + if (ct3d->hostpmem) { + address_space_destroy(&ct3d->hostpmem_as); + } + if (ct3d->hostvmem) { + address_space_destroy(&ct3d->hostvmem_as); + } } =20 /* TODO: Support multiple HDM decoders and DPA skip */ @@ -655,51 +761,77 @@ static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr h= ost_addr, uint64_t *dpa) return true; } =20 -MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, - unsigned size, MemTxAttrs attrs) +static int cxl_type3_hpa_to_as_and_dpa(CXLType3Dev *ct3d, + hwaddr host_addr, + unsigned int size, + AddressSpace **as, + uint64_t *dpa_offset) { - CXLType3Dev *ct3d =3D CXL_TYPE3(d); - uint64_t dpa_offset; - MemoryRegion *mr; + MemoryRegion *vmr =3D NULL, *pmr =3D NULL; =20 - /* TODO support volatile region */ - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { - return MEMTX_ERROR; + if (ct3d->hostvmem) { + vmr =3D host_memory_backend_get_memory(ct3d->hostvmem); + } + if (ct3d->hostpmem) { + pmr =3D host_memory_backend_get_memory(ct3d->hostpmem); } =20 - if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) { - return MEMTX_ERROR; + if (!vmr && !pmr) { + return -ENODEV; + } + + if (!cxl_type3_dpa(ct3d, host_addr, dpa_offset)) { + return -EINVAL; + } + + if (*dpa_offset > int128_get64(ct3d->cxl_dstate.mem_size)) { + return -EINVAL; + } + + if (vmr) { + if (*dpa_offset < int128_get64(vmr->size)) { + *as =3D &ct3d->hostvmem_as; + } else { + *as =3D &ct3d->hostpmem_as; + *dpa_offset -=3D vmr->size; + } + } else { + *as =3D &ct3d->hostpmem_as; } =20 - if (dpa_offset > int128_get64(mr->size)) { + return 0; +} + +MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + uint64_t dpa_offset =3D 0; + AddressSpace *as =3D NULL; + int res; + + res =3D cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size, + &as, &dpa_offset); + if (res) { return MEMTX_ERROR; } =20 - return address_space_read(&ct3d->hostmem_as, dpa_offset, attrs, data, = size); + return address_space_read(as, dpa_offset, attrs, data, size); } =20 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, unsigned size, MemTxAttrs attrs) { - CXLType3Dev *ct3d =3D CXL_TYPE3(d); - uint64_t dpa_offset; - MemoryRegion *mr; - - mr =3D host_memory_backend_get_memory(ct3d->hostmem); - if (!mr) { - return MEMTX_OK; - } + uint64_t dpa_offset =3D 0; + AddressSpace *as =3D NULL; + int res; =20 - if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) { - return MEMTX_OK; + res =3D cxl_type3_hpa_to_as_and_dpa(CXL_TYPE3(d), host_addr, size, + &as, &dpa_offset); + if (res) { + return MEMTX_ERROR; } =20 - if (dpa_offset > int128_get64(mr->size)) { - return MEMTX_OK; - } - return address_space_write(&ct3d->hostmem_as, dpa_offset, attrs, - &data, size); + return address_space_write(as, dpa_offset, attrs, &data, size); } =20 static void ct3d_reset(DeviceState *dev) @@ -714,7 +846,11 @@ static void ct3d_reset(DeviceState *dev) =20 static Property ct3_props[] =3D { DEFINE_PROP_LINK("memdev", CXLType3Dev, hostmem, TYPE_MEMORY_BACKEND, - HostMemoryBackend *), + HostMemoryBackend *), /* for backward compatibility */ + DEFINE_PROP_LINK("persistent-memdev", CXLType3Dev, hostpmem, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), + DEFINE_PROP_LINK("volatile-memdev", CXLType3Dev, hostvmem, + TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_LINK("lsa", CXLType3Dev, lsa, TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_UINT64("sn", CXLType3Dev, sn, UI64_NULL), @@ -726,6 +862,10 @@ static uint64_t get_lsa_size(CXLType3Dev *ct3d) { MemoryRegion *mr; =20 + if (!ct3d->lsa) { + return 0; + } + mr =3D host_memory_backend_get_memory(ct3d->lsa); return memory_region_size(mr); } @@ -743,6 +883,10 @@ static uint64_t get_lsa(CXLType3Dev *ct3d, void *buf, = uint64_t size, MemoryRegion *mr; void *lsa; =20 + if (!ct3d->lsa) { + return 0; + } + mr =3D host_memory_backend_get_memory(ct3d->lsa); validate_lsa_access(mr, size, offset); =20 @@ -758,6 +902,10 @@ static void set_lsa(CXLType3Dev *ct3d, const void *buf= , uint64_t size, MemoryRegion *mr; void *lsa; =20 + if (!ct3d->lsa) { + return; + } + mr =3D host_memory_backend_get_memory(ct3d->lsa); validate_lsa_access(mr, size, offset); =20 @@ -929,7 +1077,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) pc->config_read =3D ct3d_config_read; =20 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); - dc->desc =3D "CXL PMEM Device (Type 3)"; + dc->desc =3D "CXL Memory Device (Type 3)"; dc->reset =3D ct3d_reset; device_class_set_props(dc, ct3_props); =20 diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index d589f78202..edb9791bab 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -119,8 +119,10 @@ typedef struct cxl_device_state { uint64_t host_set; } timestamp; =20 - /* memory region for persistent memory, HDM */ + /* memory region size, HDM */ + uint64_t mem_size; uint64_t pmem_size; + uint64_t vmem_size; } CXLDeviceState; =20 /* Initialize the register block for a device */ @@ -245,12 +247,15 @@ struct CXLType3Dev { PCIDevice parent_obj; =20 /* Properties */ - HostMemoryBackend *hostmem; + HostMemoryBackend *hostmem; /* deprecated */ + HostMemoryBackend *hostvmem; + HostMemoryBackend *hostpmem; HostMemoryBackend *lsa; uint64_t sn; =20 /* State */ - AddressSpace hostmem_as; + AddressSpace hostvmem_as; + AddressSpace hostpmem_as; CXLComponentState cxl_cstate; CXLDeviceState cxl_dstate; =20 diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index d29a4e47af..3fe418af63 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1922,13 +1922,13 @@ static void test_acpi_q35_cxl(void) " -device pxb-cxl,bus_nr=3D12,bus=3Dpcie.0,id= =3Dcxl.1" " -device pxb-cxl,bus_nr=3D222,bus=3Dpcie.0,i= d=3Dcxl.2" " -device cxl-rp,port=3D0,bus=3Dcxl.1,id=3Drp= 1,chassis=3D0,slot=3D2" - " -device cxl-type3,bus=3Drp1,memdev=3Dcxl-me= m1,lsa=3Dlsa1" + " -device cxl-type3,bus=3Drp1,persistent-memd= ev=3Dcxl-mem1,lsa=3Dlsa1" " -device cxl-rp,port=3D1,bus=3Dcxl.1,id=3Drp= 2,chassis=3D0,slot=3D3" - " -device cxl-type3,bus=3Drp2,memdev=3Dcxl-me= m2,lsa=3Dlsa2" + " -device cxl-type3,bus=3Drp2,persistent-memd= ev=3Dcxl-mem2,lsa=3Dlsa2" " -device cxl-rp,port=3D0,bus=3Dcxl.2,id=3Drp= 3,chassis=3D0,slot=3D5" - " -device cxl-type3,bus=3Drp3,memdev=3Dcxl-me= m3,lsa=3Dlsa3" + " -device cxl-type3,bus=3Drp3,persistent-memd= ev=3Dcxl-mem3,lsa=3Dlsa3" " -device cxl-rp,port=3D1,bus=3Dcxl.2,id=3Drp= 4,chassis=3D0,slot=3D6" - " -device cxl-type3,bus=3Drp4,memdev=3Dcxl-me= m4,lsa=3Dlsa4" + " -device cxl-type3,bus=3Drp4,persistent-memd= ev=3Dcxl-mem4,lsa=3Dlsa4" " -M cxl-fmw.0.targets.0=3Dcxl.1,cxl-fmw.0.si= ze=3D4G,cxl-fmw.0.interleave-granularity=3D8k," "cxl-fmw.1.targets.0=3Dcxl.1,cxl-fmw.1.target= s.1=3Dcxl.2,cxl-fmw.1.size=3D4G,cxl-fmw.1.interleave-granularity=3D8k", tmp_path, tmp_path, tmp_path, tmp_path, diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index eda2bbbbe6..edcad4a0ce 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -34,32 +34,46 @@ "-device cxl-rp,id=3Drp2,bus=3Dcxl.1,chassis=3D0,slot=3D2 " \ "-device cxl-rp,id=3Drp3,bus=3Dcxl.1,chassis=3D0,slot=3D3 " =20 -#define QEMU_T3D \ +#define QEMU_T3D_DEPRECATED \ "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M "= \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0,id=3Dcxl-pme= m0 " =20 +#define QEMU_T3D_PMEM \ + "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M "= \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,persistent-memdev=3Dcxl-mem0,lsa=3Dlsa0,i= d=3Dpmem0 " + +#define QEMU_T3D_VMEM \ + "-object memory-backend-ram,id=3Dcxl-mem0,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,volatile-memdev=3Dcxl-mem0,id=3Dmem0 " + +#define QEMU_T3D_VMEM_LSA \ + "-object memory-backend-ram,id=3Dcxl-mem0,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ + "-device cxl-type3,bus=3Drp0,volatile-memdev=3Dcxl-mem0,lsa=3Dlsa0,id= =3Dmem0 " + #define QEMU_2T3D \ "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M "= \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0,id=3Dcxl-pme= m0 " \ + "-device cxl-type3,bus=3Drp0,persistent-memdev=3Dcxl-mem0,lsa=3Dlsa0,i= d=3Dpmem0 " \ "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s,size=3D256M "= \ "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,size=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa1,id=3Dcxl-pme= m1 " + "-device cxl-type3,bus=3Drp1,persistent-memdev=3Dcxl-mem1,lsa=3Dlsa1,i= d=3Dpmem1 " =20 #define QEMU_4T3D \ "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,size=3D256M "= \ "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size=3D256M " \ - "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0,id=3Dcxl-pme= m0 " \ + "-device cxl-type3,bus=3Drp0,persistent-memdev=3Dcxl-mem0,lsa=3Dlsa0,i= d=3Dpmem0 " \ "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s,size=3D256M "= \ "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,size=3D256M " \ - "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa1,id=3Dcxl-pme= m1 " \ + "-device cxl-type3,bus=3Drp1,persistent-memdev=3Dcxl-mem1,lsa=3Dlsa1,i= d=3Dpmem1 " \ "-object memory-backend-file,id=3Dcxl-mem2,mem-path=3D%s,size=3D256M "= \ "-object memory-backend-file,id=3Dlsa2,mem-path=3D%s,size=3D256M " \ - "-device cxl-type3,bus=3Drp2,memdev=3Dcxl-mem2,lsa=3Dlsa2,id=3Dcxl-pme= m2 " \ + "-device cxl-type3,bus=3Drp2,persistent-memdev=3Dcxl-mem2,lsa=3Dlsa2,i= d=3Dpmem2 " \ "-object memory-backend-file,id=3Dcxl-mem3,mem-path=3D%s,size=3D256M "= \ "-object memory-backend-file,id=3Dlsa3,mem-path=3D%s,size=3D256M " \ - "-device cxl-type3,bus=3Drp3,memdev=3Dcxl-mem3,lsa=3Dlsa3,id=3Dcxl-pme= m3 " + "-device cxl-type3,bus=3Drp3,persistent-memdev=3Dcxl-mem3,lsa=3Dlsa3,i= d=3Dpmem3 " =20 static void cxl_basic_hb(void) { @@ -98,14 +112,53 @@ static void cxl_2root_port(void) } =20 #ifdef CONFIG_POSIX -static void cxl_t3d(void) +static void cxl_t3d_deprecated(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + g_autofree const char *tmpfs =3D NULL; + + tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_DEPRECATED, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_t3d_persistent(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + g_autofree const char *tmpfs =3D NULL; + + tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_PMEM, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_t3d_volatile(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_VMEM); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_t3d_volatile_lsa(void) { g_autoptr(GString) cmdline =3D g_string_new(NULL); g_autofree const char *tmpfs =3D NULL; =20 tmpfs =3D g_dir_make_tmp("cxl-test-XXXXXX", NULL); =20 - g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs, tmpfs); + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D_VMEM_LSA, + tmpfs); =20 qtest_start(cmdline->str); qtest_end(); @@ -155,7 +208,10 @@ int main(int argc, char **argv) qtest_add_func("/pci/cxl/rp", cxl_root_port); qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); #ifdef CONFIG_POSIX - qtest_add_func("/pci/cxl/type3_device", cxl_t3d); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d_deprecated); + qtest_add_func("/pci/cxl/type3_device_pmem", cxl_t3d_persistent); + qtest_add_func("/pci/cxl/type3_device_vmem", cxl_t3d_volatile); + qtest_add_func("/pci/cxl/type3_device_vmem_lsa", cxl_t3d_volatile_lsa); qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4= t3d); #endif --=20 2.37.2