From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677538931; cv=none; d=zohomail.com; s=zohoarc; b=P5xL5sPHfbLwsbR04xtz/QZULkMxs1zbEQlpHREvHQ0xdZhPMmF0oHglLCNEZGAEegcVTCYIiH86HxUDZRqiFeYRVj2+WiJYbvNvx/erWdWHqyz0RoauLwEk28IsIdhGCVHQ9gRiQLInPIxBYPs0ezwP7xOKsgqw9p+df6elMdk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677538931; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YTNMbTWIUFHY2u2ZLT0n2ZG7eWfkLXxJ/1KtgwAcDkA=; b=Nd9VRRCoFaPX4B3NIuM2tk9ahXN/+M+Gr24WthhXeyYGX0DeczyNKUHfsZ69G4m4y7+SNIKreSev5Sf8cej4r3R7xxdZ+cF5J+PhyYKxDOEFCYUufjkS6pGpwK+PaNW64KbuRBAee1Fj3JThHAsr+5QkNdLpU+uLpwzYKrzGwUo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167753893147565.30119277984988; Mon, 27 Feb 2023 15:02:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmUu-0007Hr-5Z; Mon, 27 Feb 2023 18:01:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmUs-0007GU-Hg for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:30 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmUq-0000x7-Qb for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:30 -0500 Received: by mail-pl1-x644.google.com with SMTP id i5so6806809pla.2 for ; Mon, 27 Feb 2023 15:01:28 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YTNMbTWIUFHY2u2ZLT0n2ZG7eWfkLXxJ/1KtgwAcDkA=; b=ZuJeYqWbal2zL5DnD/CMt8Z35P5rWhp+TxLrguhhMxcRDK2W0z4TAQc7fwp8w4SOth /2JJ30WZ+oGX5F9rXiej4WD8g3U30ZwMvxA7lGdNvUxgEYX7nN8Cm5uXWl5TEqMvWDLm 3yAWUpF6motFC4IT/IjaoqXMNZe40R2bY+06/907K6PhqVIbnqTMaQoTu8UR+ZWZPKJw 0QvaXGFgI9DNAa7q9cu6cyUwvHUu2t3oOQggKZzXj4Qsi1F0JKsD4aWy+MSJQ5n7GGxA Yo6lDW3Rtyc9mQQGnOXeAYc7vdLSmWMGF7P2zUEcBYdJSOTOL+2m5NIU2wIxxfAfHgJM UD4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YTNMbTWIUFHY2u2ZLT0n2ZG7eWfkLXxJ/1KtgwAcDkA=; b=Wju45FmhJ+Bg9/ZebiK0UI7YUcAXrkcnEcDM9nRXNoXL5OYmin7aT4iYQlmmFGpfVp oI7qcoGlQyvkgOMavV4SpRViY6nBOE6U3lN+RUtJzWh/wg/pikvdzEQuj8YdDethuhw7 3bD9soT/Fa+azvMJn9syW3vL9qYLIP5ZFppsqaAJ7Du9mkU57Uk+tuSsWEyJuuHMhngu mfvbFI/eFVNZo9jcuXQz1sECMpBLonp72KfQZDOa6UQKU/A6o/q/oVom/f8ub5TkCRXM cJdJ57xaSuKOtXf/mLD2m7i6wkBVPxJPotawkmpE9BZpMBROByts/A4ZuQp+aHAlhi9l vHQw== X-Gm-Message-State: AO0yUKW/9YIrZhDl+e8/rrWdmbX52f5PcLarTQ7hEsDz7UoCep9VnI7E xsMF7959HKXcFK8GFY3HJtP7sTbiENY/pjGyx3wsnQ== X-Google-Smtp-Source: AK7set9I/F+tJNtAe4m6kjwHN3MDDTEN9aoAEShEOXD1LiikJiYD4xCR5nLdK/RNsIeVDk5D2s0cSg== X-Received: by 2002:a05:6a20:2445:b0:cc:f057:d3e2 with SMTP id t5-20020a056a20244500b000ccf057d3e2mr1161218pzc.9.1677538887548; Mon, 27 Feb 2023 15:01:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH for-8.0 v4 01/21] target/arm: Add isar_feature_aa64_rme Date: Mon, 27 Feb 2023 13:01:02 -1000 Message-Id: <20230227230122.816702-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538933241100003 Add the missing field for ID_AA64PFR0, and the predicate. Disable it if EL3 is forced off by the board or command-line. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++++++ target/arm/cpu.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cb4e405f04..b046f96e4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2190,6 +2190,7 @@ FIELD(ID_AA64PFR0, SEL2, 36, 4) FIELD(ID_AA64PFR0, MPAM, 40, 4) FIELD(ID_AA64PFR0, AMU, 44, 4) FIELD(ID_AA64PFR0, DIT, 48, 4) +FIELD(ID_AA64PFR0, RME, 52, 4) FIELD(ID_AA64PFR0, CSV2, 56, 4) FIELD(ID_AA64PFR0, CSV3, 60, 4) =20 @@ -3808,6 +3809,11 @@ static inline bool isar_feature_aa64_sel2(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) !=3D 0; } =20 +static inline bool isar_feature_aa64_rme(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) !=3D 0; +} + static inline bool isar_feature_aa64_vh(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0b333a749f..5092450e5b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1950,6 +1950,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); + + /* Disable the realm management extension, which requires EL3. */ + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, RME, 0); } =20 if (!cpu->has_el2) { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677538910; cv=none; d=zohomail.com; s=zohoarc; b=AqzYgYioOb0kypuZ5cfCsFiDLmO3Im5rG7oU/MHYOJYwqKK4Xmh1lZrF9xYu/uS9wGTMTpO4Gq5UplOGZqEpHKOS0vfUKnnWEJQaZlQhwUV48fEewAyqQytCPsxUvp5zoNeMF0AODnmUzhjdzwR8uKSIIew47n02CV5NlEY8/dE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677538910; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hJ0GNl2EuoPc8lssfALIIXAAXNHi+1GQhJLbNmOQ6Es=; b=L4oO43lpu/ce/DtmQqd6pnY4GkCpeA1KQRVJY1YHqWMsG1bRV+XyLlyOjO84yTdYAeEHjkhVxWMA2X+SVboeVATCxZZZkaQ3aSjmJg+koa05vNOZ4/6TycB9mjGgSoo3IdCz+KKWDwvlWdvUhn5zWKVJkgB99sU6aPrRT6o0CHw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677538910176146.20849651687308; Mon, 27 Feb 2023 15:01:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmUw-0007Ps-05; Mon, 27 Feb 2023 18:01:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmUu-0007IG-A1 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:32 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmUs-0000xi-An for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:32 -0500 Received: by mail-pl1-x632.google.com with SMTP id h8so5194762plf.10 for ; Mon, 27 Feb 2023 15:01:29 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hJ0GNl2EuoPc8lssfALIIXAAXNHi+1GQhJLbNmOQ6Es=; b=wGlEKdk6VT65KfZqfUqKYsm07b8/f0PGyANtYrDLCSwRJGH5d1ViXdN/ivCa2wtXpJ f9pMnJE4RHZFiNnQgCEb9b4CUuK78rmbN/Xy/NhYDgTXMrcx3utOP9gEXoOHyzEbZZT8 wCafZsvKkQjicMnqtD0yC28GmLDUFbnh0BlJh/hOmd8zN3am3jveWJQXNiJ/ArsmEu1S 4V/UFYk5keqM6IfgRw4czvrhXN6pusBR+OdKOSVmFbhNDAIn/VrTfpUBRLcdEI/FlD+/ VD1nwQGLimkgdE8cc8YxKFmZ23j6Cyh+94ebR346/DDFsden7HDoNSWaksF/XZRu4Weu BIrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hJ0GNl2EuoPc8lssfALIIXAAXNHi+1GQhJLbNmOQ6Es=; b=5RDL++zHio7By/ukyY/XbmBQDpgOCYA90onF+GhUJ3Zl/3pOSYDLC87U2+Ry+HEbJZ 9vwbU8SgpG+/IW2Cj1U8IX2EDebrOt7eAhf9ywdNV0Vl2Wrxmr7/3Y77cQqtramE73Nd CQowbyf8rcqOs51HSVICqwROvRjyswGIaraYthpPvYIz+YJrQspvaS5wjqHv5svoJvNq 4NyhkPzWOQrffmVpT+Hle0C1nctO6yOLN5/ebM2U94wG+6tj4F4RjW9mtkVwKrhnMkim VEytHyy1uubTUCJT/RrLzqTJVT6E+p+kV+Hx0UY9cl6aXf6vyHVuo8wSNQfST/TyFLDS b9QQ== X-Gm-Message-State: AO0yUKUi6TBilolpmN1+xkY8ftiGckJZha2p+BhDDpt9f8MQMoKatgdB awo3Uc8TbG9l0uC1tXhqiUpJbfcdQApUbeD2XA8= X-Google-Smtp-Source: AK7set8bQOFo2nxEysG2wwVe/9Ji8fxJM9wB6SMkPOoheMhbEms7yf9UI7G/zXH0GjoCqxwaB8tIOw== X-Received: by 2002:a05:6a20:4322:b0:cc:692d:92de with SMTP id h34-20020a056a20432200b000cc692d92demr1286760pzk.44.1677538888967; Mon, 27 Feb 2023 15:01:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 02/21] target/arm: Update SCR and HCR for RME Date: Mon, 27 Feb 2023 13:01:03 -1000 Message-Id: <20230227230122.816702-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538910937100003 Content-Type: text/plain; charset="utf-8" Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF to be set, and invalidate TLBs when NSE changes. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 10 ++++++++-- 2 files changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b046f96e4e..230241cf93 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1650,7 +1650,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_TERR (1ULL << 36) #define HCR_TEA (1ULL << 37) #define HCR_MIOCNCE (1ULL << 38) -/* RES0 bit 39 */ +#define HCR_TME (1ULL << 39) #define HCR_APK (1ULL << 40) #define HCR_API (1ULL << 41) #define HCR_NV (1ULL << 42) @@ -1659,7 +1659,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define HCR_NV2 (1ULL << 45) #define HCR_FWB (1ULL << 46) #define HCR_FIEN (1ULL << 47) -/* RES0 bit 48 */ +#define HCR_GPF (1ULL << 48) #define HCR_TID4 (1ULL << 49) #define HCR_TICAB (1ULL << 50) #define HCR_AMVOFFEN (1ULL << 51) @@ -1724,6 +1724,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_GPF (1ULL << 48) +#define SCR_NSE (1ULL << 62) =20 #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) diff --git a/target/arm/helper.c b/target/arm/helper.c index bd12efd392..66c578c360 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1875,6 +1875,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_fgt, cpu)) { valid_mask |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D SCR_NSE | SCR_GPF; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -1904,10 +1907,10 @@ static void scr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) env->cp15.scr_el3 =3D value; =20 /* - * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then + * If SCR_EL3.{NS,NSE} changes, i.e. change of security state, * we must invalidate all TLBs below EL3. */ - if (changed & SCR_NS) { + if (changed & (SCR_NS | SCR_NSE)) { tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | ARMMMUIdxBit_E20_0 | ARMMMUIdxBit_E10_1 | @@ -5655,6 +5658,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_fwb, cpu)) { valid_mask |=3D HCR_FWB; } + if (cpu_isar_feature(aa64_rme, cpu)) { + valid_mask |=3D HCR_GPF; + } } =20 if (cpu_isar_feature(any_evt, cpu)) { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677538963; cv=none; d=zohomail.com; s=zohoarc; b=SNtCYSzeFVSITmRkE9xL+iu2x7F3f+Y7pX9BspHupLjqS0JfJE/Vg3HNQkDKT4m9ATsYRRn0k7EkHjlyuKNNOZKsIVMTcc0pXtIJwdNtHm8jxuaomwmJhzg/xPHGSUSLTLJguAwTIaRLNleZboAzsVsD2TYRjlfRmCJ/z4xIUMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677538963; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tZqDXhMcCOeub1Ju764Ko+HifWn9WFHZoVwIsyr5duY=; b=KvKdZwHiAChvMtdwmg/FQSOk03Q01JimZeJ3JCo6mOjZSnh8FKQEKg1O8PhsSMILiml8b+QX85r/iE2VOBsUtM76WW1DjwYumLALMKoxSTyu7XRtyHLshtATcIGEt+YdoeuDVwkavkYkX62lZo+vCygRr8ypxxIPYhaEkSZKKsA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677538963701949.2921643867746; Mon, 27 Feb 2023 15:02:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmUw-0007TF-KC; Mon, 27 Feb 2023 18:01:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmUv-0007OH-Ly for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:33 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmUt-0000yI-Sg for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:33 -0500 Received: by mail-pg1-x529.google.com with SMTP id q23so4565466pgt.7 for ; Mon, 27 Feb 2023 15:01:31 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tZqDXhMcCOeub1Ju764Ko+HifWn9WFHZoVwIsyr5duY=; b=xo6w2ztMChST+elFtliGIIapTKSUnZGcrkEYJYGlf0MJER4vrma3y4pEhWVznNOivR fC8+0SIt99uQhLg+5fwR+2xXSCHnLzBq0jO8TX7wq7XMlVPT5Jkfsjh2IA2QzS1NzFQu 0adc8sxEgBlBryao6cpZQ4YFz36KNX5p3JPnASWNg7t/S5XXUC9EXDjUvJgiDSWDMsDy yTyd6dpwNG6Wxmy6dl1AtcNvCXNprHPtEO2wg0yHdrf3yzuwznLmSOVvWwA10lwI8XSV U1n3B4WigkiDvfIuO+D+yoIEzp/zZbMaJcGEPOWNbMi1giB43hmSzT62P988DZfG5wmy Gr8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tZqDXhMcCOeub1Ju764Ko+HifWn9WFHZoVwIsyr5duY=; b=ni6pZ2GjSXeAF3iscXqMqm9Wei+OEIBnrIszMQHUAubHNWQ4utg9/XHwgog122ax4T cBdYrKbR33ZxXl+pHsSo7sZNGpFLHTf3ki8qzIB5ahoxDG3EQ7NjNqZtLaZ/MIlNdcJJ WMceBGGLijqCCNU65HAADE7LdZudjfTUAIHOpm4wZrg7KOkW3gysOPNLXgOjA939112z jO+EDwL3h/FI9UVklM4EbzvQEJpB1SNlAnx0+sjJsQ+m6XZVAM91v8FBUAOMVsTalThQ 6ETTayQj69Su572uTUBWA3Xp9XWo5KVTInOCYO9//TmSOk1SG+SghGIm8AKfjTI/M66D PoaQ== X-Gm-Message-State: AO0yUKXcCz6T3i8pJZqObo7ZuVSzDEzXpDc5YrGZKC2qFehPp0XbVOMA eajauP0VAFLFbZC8QPWT98m57F3/BcVID+vxoes= X-Google-Smtp-Source: AK7set/fIBzPGvlhhC3NRhYmhPCyAlnzVBbpxSmmw2MQaDlovoBXHYtbrzLkpfnnu9u7BmWrDFvlBg== X-Received: by 2002:aa7:8f0b:0:b0:5a9:c535:dba3 with SMTP id x11-20020aa78f0b000000b005a9c535dba3mr567113pfr.25.1677538890324; Mon, 27 Feb 2023 15:01:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 03/21] target/arm: SCR_EL3.NS may be RES1 Date: Mon, 27 Feb 2023 13:01:04 -1000 Message-Id: <20230227230122.816702-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538965376100003 Content-Type: text/plain; charset="utf-8" With RME, SEL2 must also be present to support secure state. The NS bit is RES1 if SEL2 is not present. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 66c578c360..20e28d5e09 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1856,6 +1856,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } if (cpu_isar_feature(aa64_sel2, cpu)) { valid_mask |=3D SCR_EEL2; + } else if (cpu_isar_feature(aa64_rme, cpu)) { + /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */ + value |=3D SCR_NS; } if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677538935; cv=none; d=zohomail.com; s=zohoarc; b=L37D+xcN926A99mdXpbwjy7db5Jwd5j/vXE/RcAWD1u3WHfOuA2Ahus78jAABuCM5NARGb5xPSejTunDKE8EjT6RB4t4VQ93ZE4ZtcFuglMekZE55htuNYjlcuo7NUS4Ppc1V7LrRVttIZGRw1ubC90ZoBYfA9Tt/XKH+7pP+PM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677538935; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KT8em+76sjO6uHZ8hE6K4GDRZnqGduR07fvDmbr06yk=; b=hM9WFFQ1uLjhLdfMKyXSIk7stk4ukJ2OcHwMbd3iMt8DZJ1nGyyq4/oDebbDiPxk26F3GX0ZT2PSeRsWPlrI/gnCqELZyw5eoUqlD1FCcinl+Mw+fJSqYI4k37gnm9xwhSDJ6x9pWRdKWqOS5IRzNFH1jpFmrDoU/uZO35GAfyM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677538935115961.1255726846368; Mon, 27 Feb 2023 15:02:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmUz-0007fa-AY; Mon, 27 Feb 2023 18:01:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmUx-0007YD-A8 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:35 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmUv-0000yv-Dj for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:35 -0500 Received: by mail-pj1-x1036.google.com with SMTP id k21-20020a17090aaa1500b002376652e160so7817317pjq.0 for ; Mon, 27 Feb 2023 15:01:33 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KT8em+76sjO6uHZ8hE6K4GDRZnqGduR07fvDmbr06yk=; b=l1kq7/qrYmVSu7GA0PANGmr8RawNSLkaOdxhXYDz2/rGz3tIqv7JaX2y3iDBwNs5UI wu7anfIQFBVw1QYFPkos1v8lA3fDrSBpm1NdbX96n5Bhq1G7ual+ctwSxURZDgvJrKpP eytX+MHJnd3dn2FdY/hfCrQcSx5l9a3+WOYUT3cC9qGmLi3K3U9WNU9rMAjnJCZRunbj ZdxZVtETNrJVftYYCo4DFMhr7dXCfkPJV395wGUAGd5oaclonwdsIiL82nIHjFRNLj0x tZlYmK8QQrkNPwQ8TEhZz9ijKhi+bfo13oDW7XQfRYoq3871rFTaW9LOIlj6bexHciV9 vE1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KT8em+76sjO6uHZ8hE6K4GDRZnqGduR07fvDmbr06yk=; b=mAdMjFuiKYSDeJwVrQeLXUrM9hIx1ZBdAsGvy3//bJpAvAcwNZdxxERvQ7+PP0QOKg dqtAKMQ1a4LI57zGTHIGzx1RrEV5jlEA6a0phFeTVs6yuuY97lP/kNDnEitSkgyIqKxr ByzmyFKHTy/ZKOVw7UPrJiqb2EIulMTqbmIN+fEirCMQS9sZnKJjO/7VmMytNSFZlPic RJ5QTNJGmTZS+vgYnrgtAmRSuBIv3TFgCvhyCaeieQMUmu7tTpZgXxBbeNWt34fheR9t d4W1hvcNYI98GtTf7aYbePeLwhQcKcbxsHHkhGwPpnoqth3u4uVFOo/VUcHov30uhKH/ QrGw== X-Gm-Message-State: AO0yUKWOIpSu9FhyzQdVgR8wVM2NFzR9Ue7wxrU1KV2frYkg/APflu4p ApiUMzz6Zin+JrzGx6V7SibkiQLmuPkQmD9SLsA= X-Google-Smtp-Source: AK7set9tmE3P8Ku6dX8Om8tWVqF6v4qQCUPwNdOUqXYRl2kH0uxkOgsHqRZuzATEoaGlrfNZaO9XKw== X-Received: by 2002:a05:6a20:4c28:b0:cc:fced:f700 with SMTP id fm40-20020a056a204c2800b000ccfcedf700mr977516pzb.30.1677538891976; Mon, 27 Feb 2023 15:01:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 04/21] target/arm: Add RME cpregs Date: Mon, 27 Feb 2023 13:01:05 -1000 Message-Id: <20230227230122.816702-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538937328100003 Content-Type: text/plain; charset="utf-8" This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS, RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 19 +++++++++++ target/arm/helper.c | 83 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 230241cf93..8d18d98350 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -541,6 +541,11 @@ typedef struct CPUArchState { uint64_t fgt_read[2]; /* HFGRTR, HDFGRTR */ uint64_t fgt_write[2]; /* HFGWTR, HDFGWTR */ uint64_t fgt_exec[1]; /* HFGITR */ + + /* RME registers */ + uint64_t gpccr_el3; + uint64_t gptbr_el3; + uint64_t mfar_el3; } cp15; =20 struct { @@ -1043,6 +1048,7 @@ struct ArchCPU { uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; + uint8_t reset_l0gptsz; =20 /* * Intermediate values used during property parsing. @@ -2336,6 +2342,19 @@ FIELD(MVFR1, SIMDFMAC, 28, 4) FIELD(MVFR2, SIMDMISC, 0, 4) FIELD(MVFR2, FPMISC, 4, 4) =20 +FIELD(GPCCR, PPS, 0, 3) +FIELD(GPCCR, IRGN, 8, 2) +FIELD(GPCCR, ORGN, 10, 2) +FIELD(GPCCR, SH, 12, 2) +FIELD(GPCCR, PGS, 14, 2) +FIELD(GPCCR, GPC, 16, 1) +FIELD(GPCCR, GPCP, 17, 1) +FIELD(GPCCR, L0GPTSZ, 20, 4) + +FIELD(MFAR, FPA, 12, 40) +FIELD(MFAR, NSE, 62, 1) +FIELD(MFAR, NS, 63, 1) + QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=3D R_V7M_CSSELR_INDE= X_MASK); =20 /* If adding a feature bit which corresponds to a Linux ELF diff --git a/target/arm/helper.c b/target/arm/helper.c index 20e28d5e09..6e9dcb17c4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6911,6 +6911,83 @@ static const ARMCPRegInfo sme_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D access_esm, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; + +static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush(cs); +} + +static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* L0GPTSZ is RO; other bits not mentioned are RES0. */ + uint64_t rw_mask =3D R_GPCCR_PPS_MASK | R_GPCCR_IRGN_MASK | + R_GPCCR_ORGN_MASK | R_GPCCR_SH_MASK | R_GPCCR_PGS_MASK | + R_GPCCR_GPC_MASK | R_GPCCR_GPCP_MASK; + + env->cp15.gpccr_el3 =3D (value & rw_mask) | (env->cp15.gpccr_el3 & ~rw= _mask); +} + +static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + env->cp15.gpccr_el3 =3D FIELD_DP64(0, GPCCR, L0GPTSZ, + env_archcpu(env)->reset_l0gptsz); +} + +static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static const ARMCPRegInfo rme_reginfo[] =3D { + { .name =3D "GPCCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 6, + .access =3D PL3_RW, .writefn =3D gpccr_write, .resetfn =3D gpccr_res= et, + .fieldoffset =3D offsetof(CPUARMState, cp15.gpccr_el3) }, + { .name =3D "GPTBR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.gptb= r_el3) }, + { .name =3D "MFAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 5, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mfar= _el3) }, + { .name =3D "TLBI_PAALL", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paall_write }, + { .name =3D "TLBI_PAALLOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + /* + * QEMU does not have a way to invalidate by physical address, thus + * invalidating a range of physical addresses is accomplished by + * flushing all tlb entries in the outer sharable domain, + * just like PAALLOS. + */ + { .name =3D "TLBI_RPALOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "TLBI_RPAOS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_paallos_write }, + { .name =3D "DC_CIPAPA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NOP }, +}; + +static const ARMCPRegInfo rme_mte_reginfo[] =3D { + { .name =3D "DC_CIGDPAPA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NOP }, +}; #endif /* TARGET_AARCH64 */ =20 static void define_pmu_regs(ARMCPU *cpu) @@ -9102,6 +9179,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_tlbios, cpu)) { define_arm_cp_regs(cpu, tlbios_reginfo); } + if (cpu_isar_feature(aa64_rme, cpu)) { + define_arm_cp_regs(cpu, rme_reginfo); + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, rme_mte_reginfo); + } + } #ifndef CONFIG_USER_ONLY /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z2H/Gk1sBZb1zXekpLJvx4pEHghvfBzjstzPZ4R0ZjE=; b=Mnn2xqoVUyaEtMsfWEBI/Avs2nY20c7q7zcAoC2/VFE0M6/XgkoOBLtjHfbGAbmwhZ 9J4E5kG4dXYK5g8KmHZUiz8lfvvC2Rgm7Cpq/kNFYjjhSu69y0XRddB76MEGXbd48IFw q4P3DqC8TizVDjx3LjvwaWewmakwTdR8uyYJ1+s+JmJ6MPxOL7jOqcBNa9fnbdKcpdwI NWfouqldQYlGYY0wftYUYTiB7HQ+3/Ri3eX5/tHG20f0X8fJ0JOOA+D1NYaqOuxmwy3c 9y/OLOxcs3i1hpJ/pVaiQl2uwX7tFrbN8x8NZW19eS0ru2B5tLA0KYoHV/jYlT0JeKVF 7x0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z2H/Gk1sBZb1zXekpLJvx4pEHghvfBzjstzPZ4R0ZjE=; b=xiByrsxXfQQlv9T9dSMDoMngIKXy2vWYJJy+vqkctfqJB4GQ8/swcJWZeP4WFg2LDW k3S5mVKhKYcNXucWgYQ9X+63b6T9+te/miUYRtVMWFMPDBXv8UdzyHo2Ars2u5006Egy a/sxRpIIB2HHbIX5SotV6tQ/Xe70scl5abrkkbjykmGNUSEc1l7HwxC0kig2xCB+rgb1 qnCyq8Ch9n6UTmMQGVvX/gfLC3/rK1+AeUk1NZR79TtUbxwKVd4oYB0kyHOvji5S1np5 ITKhxnv42zQsib1+J7aa3jXdQXdJF/7JlLi7awOT5ypX934/40mTpJhhjW5bUl/zzNVE nKuQ== X-Gm-Message-State: AO0yUKVnT+gpVCS1cTB3x6MGEpFDd2ynBgHF3G/wGIjBIVGD8LsVhFus K7V9rV9fWoZlK77PAFJrQ1e0t/+jDgu7ixSxHc8= X-Google-Smtp-Source: AK7set/7HurfOjHlfPUJNb+DBJqCi+S4G3U8f9Z8KYqRBeQ/HhLqdMB9QjjladFqGrFURA87VWMtUQ== X-Received: by 2002:a17:90b:3b4b:b0:234:56aa:f176 with SMTP id ot11-20020a17090b3b4b00b0023456aaf176mr9561468pjb.24.1677538893487; Mon, 27 Feb 2023 15:01:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 05/21] target/arm: Introduce ARMSecuritySpace Date: Mon, 27 Feb 2023 13:01:06 -1000 Message-Id: <20230227230122.816702-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538941318100001 Content-Type: text/plain; charset="utf-8" Introduce both the enumeration and functions to retrieve the current state, and state outside of EL3. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 89 ++++++++++++++++++++++++++++++++++----------- target/arm/helper.c | 60 ++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8d18d98350..203a3e0046 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2409,25 +2409,53 @@ static inline int arm_feature(CPUARMState *env, int= feature) =20 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); =20 -#if !defined(CONFIG_USER_ONLY) /* + * ARM v9 security states. + * The ordering of the enumeration corresponds to the low 2 bits + * of the GPI value, and (except for Root) the concat of NSE:NS. + */ + +typedef enum ARMSecuritySpace { + ARMSS_Secure =3D 0, + ARMSS_NonSecure =3D 1, + ARMSS_Root =3D 2, + ARMSS_Realm =3D 3, +} ARMSecuritySpace; + +/* Return true if @space is secure, in the pre-v9 sense. */ +static inline bool arm_space_is_secure(ARMSecuritySpace space) +{ + return space =3D=3D ARMSS_Secure || space =3D=3D ARMSS_Root; +} + +/* Return the ARMSecuritySpace for @secure, assuming !RME or EL[0-2]. */ +static inline ARMSecuritySpace arm_secure_to_space(bool secure) +{ + return secure ? ARMSS_Secure : ARMSS_NonSecure; +} + +#if !defined(CONFIG_USER_ONLY) +/** + * arm_security_space_below_el3: + * @env: cpu context + * + * Return the security space of exception levels below EL3, following + * an exception return to those levels. Unlike arm_security_space, + * this doesn't care about the current EL. + */ +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env); + +/** + * arm_is_secure_below_el3: + * @env: cpu context + * * Return true if exception levels below EL3 are in secure state, - * or would be following an exception return to that level. - * Unlike arm_is_secure() (which is always a question about the - * _current_ state of the CPU) this doesn't care about the current - * EL or mode. + * or would be following an exception return to those levels. */ static inline bool arm_is_secure_below_el3(CPUARMState *env) { - assert(!arm_feature(env, ARM_FEATURE_M)); - if (arm_feature(env, ARM_FEATURE_EL3)) { - return !(env->cp15.scr_el3 & SCR_NS); - } else { - /* If EL3 is not supported then the secure state is implementation - * defined, in which case QEMU defaults to non-secure. - */ - return false; - } + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + return ss =3D=3D ARMSS_Secure; } =20 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */ @@ -2447,16 +2475,23 @@ static inline bool arm_is_el3_or_mon(CPUARMState *e= nv) return false; } =20 -/* Return true if the processor is in secure state */ +/** + * arm_security_space: + * @env: cpu context + * + * Return the current security space of the cpu. + */ +ARMSecuritySpace arm_security_space(CPUARMState *env); + +/** + * arm_is_secure: + * @env: cpu context + * + * Return true if the processor is in secure state. + */ static inline bool arm_is_secure(CPUARMState *env) { - if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.secure; - } - if (arm_is_el3_or_mon(env)) { - return true; - } - return arm_is_secure_below_el3(env); + return arm_space_is_secure(arm_security_space(env)); } =20 /* @@ -2475,11 +2510,21 @@ static inline bool arm_is_el2_enabled(CPUARMState *= env) } =20 #else +static inline ARMSecuritySpace arm_security_space_below_el3(CPUARMState *e= nv) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure_below_el3(CPUARMState *env) { return false; } =20 +static inline ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + return ARMSS_NonSecure; +} + static inline bool arm_is_secure(CPUARMState *env) { return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 6e9dcb17c4..af71caa7c7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12155,3 +12155,63 @@ void aarch64_sve_change_el(CPUARMState *env, int o= ld_el, } } #endif + +#ifndef CONFIG_USER_ONLY +ARMSecuritySpace arm_security_space(CPUARMState *env) +{ + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_secure_to_space(env->v7m.secure); + } + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* Check for AArch64 EL3 or AArch32 Mon. */ + if (is_a64(env)) { + if (extract32(env->pstate, 2, 2) =3D=3D 3) { + if (cpu_isar_feature(aa64_rme, env_archcpu(env))) { + return ARMSS_Root; + } else { + return ARMSS_Secure; + } + } + } else { + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { + return ARMSS_Secure; + } + } + + return arm_security_space_below_el3(env); +} + +ARMSecuritySpace arm_security_space_below_el3(CPUARMState *env) +{ + assert(!arm_feature(env, ARM_FEATURE_M)); + + /* + * If EL3 is not supported then the secure state is implementation + * defined, in which case QEMU defaults to non-secure. + */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + return ARMSS_NonSecure; + } + + /* + * Note NSE cannot be set without RME, and NSE & !NS is Reserved. + * Ignoring NSE when !NS retains consistency without having to + * modify other predicates. + */ + if (!(env->cp15.scr_el3 & SCR_NS)) { + return ARMSS_Secure; + } else if (env->cp15.scr_el3 & SCR_NSE) { + return ARMSS_Realm; + } else { + return ARMSS_NonSecure; + } +} +#endif /* !CONFIG_USER_ONLY */ --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0zAr88doy4l35/U8kOUIKFNAL46N655Bwwt/mOy9kK4=; b=eQwXhSOu+8gMc5xT2K+KqPEWL1foo5Vd2FpZhZEeSEQxqVjBfdYnXzXtHbgprTAUao jQPSQu/lIvTFMBsMxsxjqDV2qh1nqlarXZ+2YmkERd5cUU6MF0la14/qNQiiukKVg2D0 BcWKgxb44Pa7ecSuUxksfwv5peCSDnI08ZozPWFGLkVKfhybVvcUyRMDeuWBNuMGEK5D 1cftzHb7n2sDsO92pcIgV3827dz4ySGlrtEfuZJvO/d0cI/VRh/O4wBfkoiBpiFpK0F+ a/0WjnmLVmRETGNieRclVYOgzkSm3EZqT80G2Rcr/kXJNg9dv/U/FoLRFq0uAjRoqvcj abRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0zAr88doy4l35/U8kOUIKFNAL46N655Bwwt/mOy9kK4=; b=8Bu/4yP286HvD4zJjjkPSwM+eYbelpsXgFaNNjFk2Jt2jYtEXPU2GzVp/50awSlRNB 7nXBv/c+JrRrxULHKWjfBKMHGfiprFNUGeYUR76R33ZsLOlIRcZjxr3l9mHVXnpXaE1t eEoINMBMsTNp41fPtThircdeL+2krKIvgRrsZm1FCDo2+eukQHKebZyqQNGmJ8MGrrGQ 5dni9YQNKHAepyccsroUmAHiHABB4vrCZzBjIj6f/E3K9rVsp6x96LhKkeyUASv56zS/ LFd0UAadvbiRplyPM2FRUuZW+OS1y5veRfomQxKHqOrPfrodUrWL33RIEbqap7ubQQUp yanQ== X-Gm-Message-State: AO0yUKVDh6QgBgOq2Q91QgfNbfWIPp8R+WRlmtk15GCpSNg3umYQV5HH hyr8o4f2f14Ek9RnUpy7yVnF7plC8EEYGBzFyWQ= X-Google-Smtp-Source: AK7set8ZYuElp6R7pPhYCEHCJ86L03AeuY5uiVjJ94UoU21mL0bGA8H26gVjDHVSdnZ3TFJCBXSHFw== X-Received: by 2002:a05:6a20:7343:b0:b5:a231:107f with SMTP id v3-20020a056a20734300b000b5a231107fmr1199691pzc.12.1677538895002; Mon, 27 Feb 2023 15:01:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 06/21] include/exec/memattrs: Add two bits of space to MemTxAttrs Date: Mon, 27 Feb 2023 13:01:07 -1000 Message-Id: <20230227230122.816702-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538967385100007 Content-Type: text/plain; charset="utf-8" We will need 2 bits to represent ARMSecurityState. Do not attempt to replace or widen secure, even though it logically overlaps the new field -- there are uses within e.g. hw/block/pflash_cfi01.c, which don't know anything specific about ARM. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..d04170aa27 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -29,10 +29,17 @@ typedef struct MemTxAttrs { * "didn't specify" if necessary. */ unsigned int unspecified:1; - /* ARM/AMBA: TrustZone Secure access + /* + * ARM/AMBA: TrustZone Secure access * x86: System Management Mode access */ unsigned int secure:1; + /* + * ARM: ArmSecuritySpace. This partially overlaps secure, but it is + * easier to have both fields to assist code that does not understand + * ARMv9 RME, or no specific knowledge of ARM at all (e.g. pflash). + */ + unsigned int space:2; /* Memory access is usermode (unprivileged) */ unsigned int user:1; /* --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539004; cv=none; d=zohomail.com; s=zohoarc; b=EUfaLe+jmYnhwLBJ2KWqkgD9icAaHs9X6medRLjd7kHR4epqv4x+Q/jmUcnNl0vkU4yVqPW2VwUq2dB3hYhzZotHBmUjhTCIQR9C5N+cYl1q+UyDo9bAagCkmBqvHYUyrhXeBI6fQyVlwUVk0maxPYsq1smOh+kq9ueh0RWcmgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677539004; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1DhgmYrdRtcz8D+NJIKyPDdTEW1LOW9SZeYmEwPQF4o=; b=Qh776Rzv3M1Z4HsYF/K7b0MFpyfBKo2CXHeI/MPLZ39rGiND/NyVRlkgIp5Lt+vMhPeNCYDuQfkR8+wdNMv+Kymp7mB/xNQHujBZWQFtxaA7AB8Oe/m/U68dgLzeYKDbLqqWLYAGq5Jo6O3ijUSM/vIDC2XkidPm8PslkP8LUMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677539004456443.0165005315762; Mon, 27 Feb 2023 15:03:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmV3-0007kP-DZ; Mon, 27 Feb 2023 18:01:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmV1-0007ip-8c for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:39 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmUz-0000xh-EX for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:39 -0500 Received: by mail-pj1-x1036.google.com with SMTP id y15-20020a17090aa40f00b00237ad8ee3a0so7777121pjp.2 for ; Mon, 27 Feb 2023 15:01:37 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1DhgmYrdRtcz8D+NJIKyPDdTEW1LOW9SZeYmEwPQF4o=; b=Mia7BNxkaRVi0Dq4tDhPuR5hbzqHAIR/77m6mtkTz9AAFn15RiXJ3pTQYRQX7R2OK9 7/sqqjxktLTxm37dYlQPhs33lgAyB/G3dA5ZJd6Q/s8N9i9WPUOWdKiITT/y2Ppx0g3L fZ6CweMBeoely6ncZAl7SycmMNjoZ3PfYZgZIro71/T/J28ZdH8HGZ8ZRetAebQhC9KK MDfw9Mtssv/Sn+ymU590NXM7mKZ/B3cP7wMAXWkOPFJcDCGfO8m/Uw1FL21L3uIyTX2j XH5XSwAWMxgho5hxF00P2z4U0vkg88NJcyKs1DHPnVl7TVc+56vPS6bhBhV3Vlxpa4eQ ntZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1DhgmYrdRtcz8D+NJIKyPDdTEW1LOW9SZeYmEwPQF4o=; b=0B2ERmBuQxO871xMK1ZtsLCVx+b7Nn/4d+RBE0aPUOdhybx6jbgXFTi7GpsVwBk+fs KL+olJ8xrdfAGZzPMqIGYfNY63y3b2e92f6Fet5Za8+8AHnIqUU3uPf8xbRx609GQPKU 0zkLbJJT+vNuFO7CwRNfh+5mYaHlsZ6kAmMDbeptJ0adQ7ikPy1KM/VXf60jHVtCySSs 5WBdP7670PxvntRV9PAIincBrNDa0dYFiSOVya7IMLwflg4RWMeJJ9Ib6irhyEde3V8j +3R6CJjHNmalVy10Yr7MSCPudnw/1NTTE8fd6EvHiYCzCevl/s/lRTdXY0dQKfanmbo4 Ijog== X-Gm-Message-State: AO0yUKWZXoKXuIZf2gSSGvJRg8KOFt0V61PTrV2jdIm9QWUEIFbYgdyf yXeo6cF/P64qIskaDAZMZt99No/y2vN7eg5LKfU= X-Google-Smtp-Source: AK7set+S8RV4FuExmWo+9Y7VEmSyArdCJFjM6TR8rPQg48I8s7srZtsOBTSvMlGm/qjhpm3roiXgmA== X-Received: by 2002:a17:90a:4146:b0:234:b35b:f8e7 with SMTP id m6-20020a17090a414600b00234b35bf8e7mr892330pjg.7.1677538896562; Mon, 27 Feb 2023 15:01:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 07/21] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx Date: Mon, 27 Feb 2023 13:01:08 -1000 Message-Id: <20230227230122.816702-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539005597100003 Content-Type: text/plain; charset="utf-8" It will be helpful to have ARMMMUIdx_Phys_* to be in the same relative order as ARMSecuritySpace enumerators. This requires the adjustment to the nstable check. While there, check for being in secure state rather than rely on clearing the low bit making no change to non-secure state. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 12 ++++++------ target/arm/ptw.c | 12 +++++------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 203a3e0046..c5fc475cf8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2855,18 +2855,18 @@ typedef enum ARMMMUIdx { ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, =20 - /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_NS =3D 8 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_S =3D 9 | ARM_MMU_IDX_A, - /* * Used for second stage of an S12 page table walk, or for descriptor * loads during first stage of an S1 page table walk. Note that both * are in use simultaneously for SecureEL2: the security state for * the S2 ptw is selected by the NS bit from the S1 ptw. */ - ARMMMUIdx_Stage2 =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2_S =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 9 | ARM_MMU_IDX_A, + + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 89cc7e2aff..5aa58c200c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1414,16 +1414,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; nstable =3D extract32(tableattrs, 4, 1); - if (nstable) { + if (nstable && ptw->in_secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS - * Assert that the non-secure idx are even, and relative order. + * Assert the relative order of the secure/non-secure indexes. */ - QEMU_BUILD_BUG_ON((ARMMMUIdx_Phys_NS & 1) !=3D 0); - QEMU_BUILD_BUG_ON((ARMMMUIdx_Stage2 & 1) !=3D 0); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS + 1 !=3D ARMMMUIdx_Phys_S); - QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2 + 1 !=3D ARMMMUIdx_Stage2_S); - ptw->in_ptw_idx &=3D ~1; + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 !=3D ARMMMUIdx_Phys_NS); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2); + ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; } if (!S1_ptw_translate(env, ptw, descaddr, fi)) { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677538956892827.2158403152127; Mon, 27 Feb 2023 15:02:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVF-0007lP-It; Mon, 27 Feb 2023 18:01:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmV3-0007jk-2S for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:41 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmV1-00011a-Bg for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:40 -0500 Received: by mail-pj1-x102d.google.com with SMTP id m20-20020a17090ab79400b00239d8e182efso943683pjr.5 for ; Mon, 27 Feb 2023 15:01:38 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sfKYqEChfrtTh13e431O8E/j8Wi+d7VSKgI7shCtu0o=; b=One1GNUXbCurN1VIU+A9CbGg4mkih2JLVqr32t0seIYiMHiyhU0Ngj2bw5//jtCtlG hW3eDUC1Zz7VCBQHgxxaigqOqIVcv/LfgWsCHLKDmVLD3XEOpcAhwVqs7f/LwmRc7hQ+ NwjMHB8bI0oMTgJEqFllPqUOEU70nphcuPxripcjMcGxXbWkYHgJdjoH+t/wGgaq56dU iLNlV9/EGpNJmPV58QWP1a5uA5A57wA+jkBYHWgNL6fbHcSAEEyfyGrM2L8zYMep6g3O vu/cJmRpvNM3nxtFXhL/jjwEUcTyyB9LrAtDIKerp6/2lXEv8iNjMhsm876UcnYQmdzA sV7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sfKYqEChfrtTh13e431O8E/j8Wi+d7VSKgI7shCtu0o=; b=WvEvbW5pIrLV0rGlWfOgTpME/0O7Z7jvPUs8cHHLmAFbf9jR3LsbixNZeg3rSFXse9 kK5ocicqEITegfVES1WK/knE4caq7NpL1nCKTCjRUeIW633YZbS+fCZQNBYXm3cgmvMm mt240yJNqJGZqB1yeFcyvBjylbZygFVFec5LQt1jRQNsKvlEUfIK5qDQ/zD7cP9hYoqK uaRNIbwupS9KNstmr/gPKVb170AIb15/oHvEoKTGJXFbP6dLcXr8JzW0VIbEAD0ZsXXV Yy7AUFeDNJVBJGCf2L2P9JRpa8vOihk49mWcVZT/Txkik+GcxSlPWIIsc7VyFCuQDhac fK3Q== X-Gm-Message-State: AO0yUKW3cbtX0D6sxLFeOvOtpOFrSiAPap81gtJgp+2/Mblmwv484Mjc RnaptxVsWpSdLuXnGx/yI+Mex9tzRNeQ5gosdX4= X-Google-Smtp-Source: AK7set8vHYyXLXspLfVaXq0JdFmabcY+UsA3nxBZKk0urR501xepEKCBwjQ4T4szMSxJ1vY8qYJRKg== X-Received: by 2002:a05:6a20:1610:b0:c0:c429:cbbd with SMTP id l16-20020a056a20161000b000c0c429cbbdmr1067065pzj.6.1677538898075; Mon, 27 Feb 2023 15:01:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH for-8.0 v4 08/21] target/arm: Introduce ARMMMUIdx_Phys_{Realm, Root} Date: Mon, 27 Feb 2023 13:01:09 -1000 Message-Id: <20230227230122.816702-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1677538957385100001 With FEAT_RME, there are four physical address spaces. For now, just define the symbols, and mention them in the same spots as the other Phys indexes in ptw.c. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu-param.h | 2 +- target/arm/cpu.h | 23 +++++++++++++++++++++-- target/arm/ptw.c | 10 ++++++++-- 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h index 53cac9c89b..8dfd7a0bb6 100644 --- a/target/arm/cpu-param.h +++ b/target/arm/cpu-param.h @@ -47,6 +47,6 @@ bool guarded; #endif =20 -#define NB_MMU_MODES 12 +#define NB_MMU_MODES 14 =20 #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c5fc475cf8..05fd6e61aa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2865,8 +2865,10 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage2 =3D 9 | ARM_MMU_IDX_A, =20 /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root =3D 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm =3D 13 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -2930,6 +2932,23 @@ typedef enum ARMASIdx { ARMASIdx_TagS =3D 3, } ARMASIdx; =20 +static inline ARMMMUIdx arm_space_to_phys(ARMSecuritySpace space) +{ + /* Assert the relative order of the physical mmu indexes. */ + QEMU_BUILD_BUG_ON(ARMSS_Secure !=3D 0); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_NS !=3D ARMMMUIdx_Phys_S + ARMSS_NonS= ecure); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Root !=3D ARMMMUIdx_Phys_S + ARMSS_Ro= ot); + QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_Realm !=3D ARMMMUIdx_Phys_S + ARMSS_R= ealm); + + return ARMMMUIdx_Phys_S + space; +} + +static inline ARMSecuritySpace arm_phys_to_space(ARMMMUIdx idx) +{ + assert(idx >=3D ARMMMUIdx_Phys_S && idx <=3D ARMMMUIdx_Phys_Realm); + return idx - ARMMMUIdx_Phys_S; +} + static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5aa58c200c..0788c342b8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -182,8 +182,10 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, case ARMMMUIdx_E3: break; =20 - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* No translation for physical address spaces. */ return true; =20 @@ -2636,8 +2638,10 @@ static bool get_phys_addr_disabled(CPUARMState *env,= target_ulong address, switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_Phys_NS: case ARMMMUIdx_Phys_S: + case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: break; =20 default: @@ -2834,6 +2838,8 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, switch (mmu_idx) { case ARMMMUIdx_Phys_S: case ARMMMUIdx_Phys_NS: + case ARMMMUIdx_Phys_Root: + case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ return get_phys_addr_disabled(env, address, access_type, mmu_idx, is_secure, result, fi); --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UwykunfgJ4wHWdk7tq7XjhvoPxXNDp8LS8Cf559qMMI=; b=dD/Hxj+i4JO5E9/7bDVlNFbiuK2VqASHUD/v0D3HSg7yvIuvl2H+TnVnpwmmt1e/jU +0HrWsTnl+1PMWOseAJe7PuqtZCBeB8kjTn47dnGH3fi/v2XFcbGBlPqQ5UJxzo1XT5+ 531oqjqoxzZADgWOMYmgk+o9nTrCNYkkVNcBJYSKCepaihithtw7X/J7DWQeh6HB0HCI 26OulfIkqGFxqM+4Jfq5lSueMN3B/C4pP8ZO+6JvJRNJpa7IYQUYUPb1lRwzDQJHR1Zk EcBBOumzNkI8bDoOdXV420SwGRAZbJgzUeq98t2YwWmeSGsnwtk7joCvbKYMGr/G7kBc LHRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UwykunfgJ4wHWdk7tq7XjhvoPxXNDp8LS8Cf559qMMI=; b=AT90moaY9MWOgL5Mp9ErIDx6+lYKxft+1JKnuDbg7C0tqUzzwg1JMZ2XbZarGbelEG rilx/ANM8D48lghXQPyvAL8kMqDS2AzJv/sOXMSXowZmI0pxvukGwQ7WcgYv5WbBYmWM +Hkk9bEw0AEBtqOzfymJyBEQijSqDa5WCLdX/U6VXS6ML0Avo1I/woMNG/SgWD8LrfBg b/6W1O9ivKFnCSAD5thv30RsLLmKCvLhSA0apAyBOSe2IhbeUe1KN3VojNOHcmnRNt0/ dfRNhZAbGt82izwc2Axt9ep7RJ3PG9RrIqTpXnzaPBTf+GAjzyMYy2NkKUYbU1RuopW6 hKbg== X-Gm-Message-State: AO0yUKVt3itDx1RoN1bCr15EnohTSud6ZUfHC/BfiFfiAbtWIzGEsF24 3MTtSlA3Ob/WEQ7xVSS/8vrpwdUTJQXTgsB7lGI= X-Google-Smtp-Source: AK7set+zHe6pFXCW3ErUEGvrsVtF+hniKQP2fBNoQb0btXJF/HnR5QtP/QK037pJWhXCnp6JI5wl/Q== X-Received: by 2002:a05:6a20:8e06:b0:cd:1e80:587d with SMTP id y6-20020a056a208e0600b000cd1e80587dmr1482783pzj.23.1677538899838; Mon, 27 Feb 2023 15:01:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH for-8.0 v4 09/21] target/arm: Remove __attribute__((nonnull)) from ptw.c Date: Mon, 27 Feb 2023 13:01:10 -1000 Message-Id: <20230227230122.816702-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539021620100003 This was added in 7e98e21c098 as part of a reorg in which one of the argument had been legally NULL, and this caught actual instances. Now that the reorg is complete, this serves little purpose. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/ptw.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0788c342b8..1a51add39c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -32,15 +32,13 @@ typedef struct S1Translate { static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, MMUAccessType access_type, bool s1_is_el0, - GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) - __attribute__((nonnull)); + GetPhysAddrResult *result, ARMMMUFaultInfo = *fi); =20 static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) - __attribute__((nonnull)); + ARMMMUFaultInfo *fi); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ static const uint8_t pamax_map[] =3D { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539054; cv=none; d=zohomail.com; s=zohoarc; b=Ca6ID8HegzC2ZObDv+GiIwe4kOLVHAtG0d9QPywJPfnnaQVftxrtgXXR9KjCTcdlRNAfGlQuTO89wFG2D+Qof5BJO25CblEzuUaqNcJ+6xSbecvol79uWOZgNgjD7X7PTpk1TsXNLZm3lG1j98Hg6u2BvnnAAlSQRJId1QIRoHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677539054; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+kdRMygz3PBTRXyQmo1Q/ab0KJfHnaDCouII/ZdNfRA=; b=PPX0CkOEZeDWVNGG4ng8563LYusNW8Hb2KRw3rTpNcYZ9acy05lOax+3Y1WXAsPtKoRrNDLz7N9KL3o74r3/NSd8lKCNwReH80YmzmvRygR0IjINg0EucpXELD1xxCXOYqjS+xERZ4tgPaIn2CYaC+0znmPud7in5PKZW7Sf6mE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677539053993860.3141060856187; Mon, 27 Feb 2023 15:04:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVQ-0008Jo-4W; Mon, 27 Feb 2023 18:02:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmV9-0007tp-La for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:55 -0500 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmV5-0000x7-Le for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:46 -0500 Received: by mail-pl1-x644.google.com with SMTP id i5so6807538pla.2 for ; Mon, 27 Feb 2023 15:01:41 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+kdRMygz3PBTRXyQmo1Q/ab0KJfHnaDCouII/ZdNfRA=; b=MnOj0FHp05MXvkBbv6QnV2qjoenuK9BlmTj/RqxiNPUpEgBpVLYYp4UxOmH1FzzscW NRnGajrzAepF0wEByzwF6fluvzbuHAPJImPYttFXr3uZXoP2Gwru934Yq69yOz7slkO+ CwI/meeugI9dvuJVJUK3se0Qx3sqkVWjFy5Kny8h4NPzlDYSLXBCxeUkwn6Zgc3lf2HY toA17gX6Q6M4WJrGfywjGft1pzka3wm05h3NKLQgBY8gGfKQ0bYU6FybNDNqFeqxvO9Q ywpUEdMsatNR5dIU6lG8I9FTaSMubkTWcOViMsBbq0v2c8fLwuSMHtCjb9Z0sSoFvv9Y /k2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+kdRMygz3PBTRXyQmo1Q/ab0KJfHnaDCouII/ZdNfRA=; b=ceQ0g0n4mX4kF2J6PMRaUf9+eu9WIN+FwFXdWg36gl55fFflR2b6eHLJQ1IK7JlmDf 8MwJtUzqZrdwYgbHxAaPR3DPzKxnz22/0ZdLexNUJ+4vX8sRiWYBNPpIF7+ZCjYwsOPq lzutQPZzP5NrXRFWD1AWlb4uCA63mprjOtJeTTQE8hhgwGrjZF9NaewpewA+pb9CZFjU ndakJPNXapuYNz6POh1oLcIN7/cCIRPxw2ao0t4QxlUdGkw9u1b6rYoHt2Hp8e6u5IFs jLMtfPoYcdTOlC8ml5SOf64xZsFyJ74GV1KKTeOMzdTHnUnz+PNrMg5TVuRsXVvQg3/K 9E+g== X-Gm-Message-State: AO0yUKVL6AdvmdlnJumoWjdkNBU37VaVaZqKyodj3HMjp983KE1c3FhC VOGhMZrefZjnDMvM2axVJOdauDoCbTioEQe7qV9XBw== X-Google-Smtp-Source: AK7set8OPhMAqZHIxxof1HEAqhjnvAAK4mIAeCPnmzU7c9kPb5pgr76knBvHZ7vtd5ZV7oqaqJ1TqQ== X-Received: by 2002:a05:6a20:1603:b0:c7:60ad:9af7 with SMTP id l3-20020a056a20160300b000c760ad9af7mr10503149pzj.1.1677538901444; Mon, 27 Feb 2023 15:01:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 10/21] target/arm: Pipe ARMSecuritySpace through ptw.c Date: Mon, 27 Feb 2023 13:01:11 -1000 Message-Id: <20230227230122.816702-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::644; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x644.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539055838100003 Content-Type: text/plain; charset="utf-8" Add input and output space members to S1Translate. Set and adjust them in S1_ptw_translate, and the various points at which we drop secure state. Initialize the space in get_phys_addr; for now leave get_phys_addr_with_secure considering only secure vs non-secure spaces. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 98 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 78 insertions(+), 20 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1a51add39c..75f276b520 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -19,11 +19,13 @@ typedef struct S1Translate { ARMMMUIdx in_mmu_idx; ARMMMUIdx in_ptw_idx; + ARMSecuritySpace in_space; bool in_secure; bool in_debug; bool out_secure; bool out_rw; bool out_be; + ARMSecuritySpace out_space; hwaddr out_virt; hwaddr out_phys; void *out_host; @@ -216,6 +218,7 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t a= ttrs) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { + ARMSecuritySpace space =3D ptw->in_space; bool is_secure =3D ptw->in_secure; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx =3D ptw->in_ptw_idx; @@ -232,7 +235,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, if (regime_is_stage2(s2_mmu_idx)) { S1Translate s2ptw =3D { .in_mmu_idx =3D s2_mmu_idx, - .in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_P= hys_NS, + .in_ptw_idx =3D arm_space_to_phys(space), + .in_space =3D space, .in_secure =3D is_secure, .in_debug =3D true, }; @@ -294,10 +298,17 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, } =20 /* Check if page table walk is to secure or non-secure PA space. */ - ptw->out_secure =3D (is_secure - && !(pte_secure + if (is_secure) { + bool out_secure =3D !(pte_secure ? env->cp15.vstcr_el2 & VSTCR_SW - : env->cp15.vtcr_el2 & VTCR_NSW)); + : env->cp15.vtcr_el2 & VTCR_NSW); + if (!out_secure) { + is_secure =3D false; + space =3D ARMSS_NonSecure; + } + } + ptw->out_secure =3D is_secure; + ptw->out_space =3D space; ptw->out_be =3D regime_translation_big_endian(env, mmu_idx); return true; =20 @@ -328,7 +339,10 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Transl= ate *ptw, } } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -371,7 +385,10 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Transl= ate *ptw, #endif } else { /* Page tables are in MMIO. */ - MemTxAttrs attrs =3D { .secure =3D ptw->out_secure }; + MemTxAttrs attrs =3D { + .secure =3D ptw->out_secure, + .space =3D ptw->out_space, + }; AddressSpace *as =3D arm_addressspace(cs, attrs); MemTxResult result =3D MEMTX_OK; =20 @@ -877,6 +894,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Transl= ate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } result->f.phys_addr =3D phys_addr; return false; @@ -1581,6 +1599,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * regime, because the attribute will already be non-secure. */ result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ @@ -2365,6 +2384,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, */ if (sattrs.ns) { result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } else if (!secure) { /* * NS access to S memory must fault. @@ -2714,6 +2734,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool is_secure =3D ptw->in_secure; bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; + ARMSecuritySpace ipa_space, s2walk_space; bool is_el0; uint64_t hcr; =20 @@ -2726,20 +2747,24 @@ static bool get_phys_addr_twostage(CPUARMState *env= , S1Translate *ptw, =20 ipa =3D result->f.phys_addr; ipa_secure =3D result->f.attrs.secure; + ipa_space =3D result->f.attrs.space; if (is_secure) { /* Select TCR based on the NS bit from the S1 walk. */ s2walk_secure =3D !(ipa_secure ? env->cp15.vstcr_el2 & VSTCR_SW : env->cp15.vtcr_el2 & VTCR_NSW); + s2walk_space =3D arm_secure_to_space(s2walk_secure); } else { assert(!ipa_secure); s2walk_secure =3D false; + s2walk_space =3D ipa_space; } =20 is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; - ptw->in_ptw_idx =3D s2walk_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; + ptw->in_space =3D s2walk_space; =20 /* * S1 is done, now do S2 translation. @@ -2827,11 +2852,12 @@ static bool get_phys_addr_with_struct(CPUARMState *= env, S1Translate *ptw, ARMMMUIdx s1_mmu_idx; =20 /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. + * The page table entries may downgrade Secure to NonSecure, but + * cannot upgrade a NonSecure translation regime's attributes + * to Secure or Realm. */ result->f.attrs.secure =3D is_secure; + result->f.attrs.space =3D ptw->in_space; =20 switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -2873,7 +2899,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, =20 default: /* Single stage and second stage uses physical for ptw. */ - ptw->in_ptw_idx =3D is_secure ? ARMMMUIdx_Phys_S : ARMMMUIdx_Phys_= NS; + ptw->in_ptw_idx =3D arm_space_to_phys(ptw->in_space); break; } =20 @@ -2948,6 +2974,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_secure =3D is_secure, + .in_space =3D arm_secure_to_space(is_secure), }; return get_phys_addr_with_struct(env, &ptw, address, access_type, result, fi); @@ -2957,7 +2984,10 @@ bool get_phys_addr(CPUARMState *env, target_ulong ad= dress, MMUAccessType access_type, ARMMMUIdx mmu_idx, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { - bool is_secure; + S1Translate ptw =3D { + .in_mmu_idx =3D mmu_idx, + }; + ARMSecuritySpace ss; =20 switch (mmu_idx) { case ARMMMUIdx_E10_0: @@ -2970,30 +3000,55 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: case ARMMMUIdx_E2: - is_secure =3D arm_is_secure_below_el3(env); + ss =3D arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: + /* + * For Secure EL2, we need this index to be NonSecure; + * otherwise this will already be NonSecure or Realm. + */ + ss =3D arm_security_space_below_el3(env); + if (ss =3D=3D ARMSS_Secure) { + ss =3D ARMSS_NonSecure; + } + break; case ARMMMUIdx_Phys_NS: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: case ARMMMUIdx_MUser: - is_secure =3D false; + ss =3D ARMSS_NonSecure; break; - case ARMMMUIdx_E3: case ARMMMUIdx_Stage2_S: case ARMMMUIdx_Phys_S: case ARMMMUIdx_MSPrivNegPri: case ARMMMUIdx_MSUserNegPri: case ARMMMUIdx_MSPriv: case ARMMMUIdx_MSUser: - is_secure =3D true; + ss =3D ARMSS_Secure; + break; + case ARMMMUIdx_E3: + if (arm_feature(env, ARM_FEATURE_AARCH64) && + cpu_isar_feature(aa64_rme, env_archcpu(env))) { + ss =3D ARMSS_Root; + } else { + ss =3D ARMSS_Secure; + } + break; + case ARMMMUIdx_Phys_Root: + ss =3D ARMSS_Root; + break; + case ARMMMUIdx_Phys_Realm: + ss =3D ARMSS_Realm; break; default: g_assert_not_reached(); } - return get_phys_addr_with_secure(env, address, access_type, mmu_idx, - is_secure, result, fi); + + ptw.in_space =3D ss; + ptw.in_secure =3D arm_space_is_secure(ss); + return get_phys_addr_with_struct(env, &ptw, address, access_type, + result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3001,9 +3056,12 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *c= s, vaddr addr, { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + ARMSecuritySpace ss =3D arm_security_space(env); S1Translate ptw =3D { - .in_mmu_idx =3D arm_mmu_idx(env), - .in_secure =3D arm_is_secure(env), + .in_mmu_idx =3D mmu_idx, + .in_space =3D ss, + .in_secure =3D arm_space_is_secure(ss), .in_debug =3D true, }; GetPhysAddrResult res =3D {}; --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PP4E13jT/Sv96Ax+VfQqfeV0Z6Vd+p408nT+Z3wCuJQ=; b=uInLixzRQQtO0QsfPkZ79882CFSX6TYtQIKw/HkxQ3NVEtuHbRxS++K5clg+7Eg0pG akqGN4ujRdtHP8v0HnIMy/HZuFKIxatqNry0JrHbJipjh8BQjQsSQf8tqczJgyxUDtKi tNdkLzmzYPi5AXdFWNJO9Y3YLOjG8VaFFWBSvthN+hSU+0fo9gPGFm/MU9OVOyOl+YWC 5NDPyO4IbdietvTGxrDSrX2rux8xJSoTHmQ11vkknk0zC9dB1CkANXB7hFsxmmxTc+hV KtUIVgX6JO7WzWgq+EJGJ18zavF2TasbdxAvsuL7DefTttAATHrPH9MEOHH2Qc7Eaxmt zSkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PP4E13jT/Sv96Ax+VfQqfeV0Z6Vd+p408nT+Z3wCuJQ=; b=JCoMsXdx/+R3iHUGI86Dqa0hE1KISPhtbQ6VWCCWhoTFRUjpVXEWjSqcNSzXcsEUJo bsQx7EkNNVHi2tLYR56Qb6Ezzyzs9uu+BrqanaY/Do0MQBNySLkYcyVfSK7N9MtFQUwY Y9UeNj3926DjitqSfiYW860tYMG3fQQRgkIznT/yiT/8QX16Exl1+aQT+W+XivVV9rJG OgVdxsgyOY0oGMn7EixwURGpWWHueTV6yYSjYggk30kbLjz/lmoxiJYQSixWCc+9IzJ+ LZgs7Ljm8hzPqBv1dYxAr/JGkP+2RDkRjl7xyNFUuCDPPvV3r8P1bOHRJqcLRwSn3k6b Swpw== X-Gm-Message-State: AO0yUKWmjk7wgSbIKbY1Wweal4x0xF81l/pGcq0ySjiDfe6UQGD9gT+n YcBPZW48dJRESGrIrKHH4J08XWVEdkBaU2l3wrk= X-Google-Smtp-Source: AK7set8LcO/Qy2VmaEcARFKk0TedwjDqU2t42f2CEZpuLppWhwrOxTfg27g3lEfvVsdLAJ0rkwbPZA== X-Received: by 2002:a05:6a20:6915:b0:cb:cb17:eac6 with SMTP id q21-20020a056a20691500b000cbcb17eac6mr999586pzj.32.1677538903324; Mon, 27 Feb 2023 15:01:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 11/21] target/arm: NSTable is RES0 for the RME EL3 regime Date: Mon, 27 Feb 2023 13:01:12 -1000 Message-Id: <20230227230122.816702-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539088325100003 Content-Type: text/plain; charset="utf-8" Test in_space instead of in_secure so that we don't switch out of Root space. Handle the output space change immediately, rather than try and combine the NSTable and NS bits later. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 75f276b520..0c07e5e24f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1242,7 +1242,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, { ARMCPU *cpu =3D env_archcpu(env); ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - bool is_secure =3D ptw->in_secure; int32_t level; ARMVAParameters param; uint64_t ttbr; @@ -1258,7 +1257,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; - bool nstable; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1419,20 +1417,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, descaddrmask =3D MAKE_64BIT_MASK(0, 40); } descaddrmask &=3D ~indexmask_grainsize; - - /* - * Secure accesses start with the page table in secure memory and - * can be downgraded to non-secure at any step. Non-secure accesses - * remain non-secure. We implement this by just ORing in the NSTable/NS - * bits at each step. - */ - tableattrs =3D is_secure ? 0 : (1 << 4); + tableattrs =3D 0; =20 next_level: descaddr |=3D (address >> (stride * (4 - level))) & indexmask; descaddr &=3D ~7ULL; - nstable =3D extract32(tableattrs, 4, 1); - if (nstable && ptw->in_secure) { + + /* + * Process the NSTable bit from the previous level. This changes + * the table address space and the output space from Secure to + * NonSecure. With RME, the EL3 translation regime does not change + * from Root to NonSecure. + */ + if (extract32(tableattrs, 4, 1) && ptw->in_space =3D=3D ARMSS_Secure) { /* * Stage2_S -> Stage2 or Phys_S -> Phys_NS * Assert the relative order of the secure/non-secure indexes. @@ -1441,7 +1438,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 !=3D ARMMMUIdx_Stage2); ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; + ptw->in_space =3D ARMSS_NonSecure; + result->f.attrs.secure =3D false; + result->f.attrs.space =3D ARMSS_NonSecure; } + if (!S1_ptw_translate(env, ptw, descaddr, fi)) { goto do_fault; } @@ -1544,7 +1545,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, */ attrs =3D new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(5= 0, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |=3D nstable << 5; /* NS */ + attrs |=3D !ptw->in_secure << 5; /* NS */ if (!param.hpd) { attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539014; cv=none; d=zohomail.com; s=zohoarc; b=KArF/oth9QOv4VuMY/Nrs9uz+zoCpnOSAyi/4jfPwuyKFEe+mZzb2HvbC06U5brYOl4HivU+EvleEutFmpDfjVbwlMvtpLVROvL/X+hFCBxI3Uaml+xepkyo5vdVlXzp4uMNi9bsVsllLUZNnfOLbSqtqIQRf1KYFptQv+wcKl4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677539014; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RwsedNDTKts66Uf/cUt0lXtmwdA1RwOLSlvaMbWJEv0=; b=KnyZx8ugmH7rPDCRS+yEz3vm6Od0UBTMwqWqBVGhETlGGT0MxG+DDf6qM8QMj4I8TO6khniQJY1aDnDEaEgYEMRA7FydXBiAz8q2hClThFUeeD9ApRWXRjDPrhAB7bUJXpybEpNG4JjVGG+XVBiw12nUql19li88RktRd9ao/V0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677539014898967.0523477649252; Mon, 27 Feb 2023 15:03:34 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVS-000060-H8; Mon, 27 Feb 2023 18:02:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmVB-0007tw-8n for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:55 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmV9-00013X-CP for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:48 -0500 Received: by mail-pj1-x1030.google.com with SMTP id qa18-20020a17090b4fd200b0023750b675f5so11728120pjb.3 for ; Mon, 27 Feb 2023 15:01:45 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RwsedNDTKts66Uf/cUt0lXtmwdA1RwOLSlvaMbWJEv0=; b=wV+Gjld+E0GXpuYommBWFyAR3I3D7Cxo60qV5lEfwvDMBCU5u0R7gHnY36mS1GPAxt 21jSljcdY86to9LebENcFRiux2c0+2N1zN8fA9KO8tbRKgPzy54T75v3tBWQhdue0nuX 0xOdHI9tuO1DBmqr2KATaS8rPVDvZC60xvBbgDzRxGueIN51BKCc+HSdKcR8UtVZPYOQ 606Xkm2UE2BLucORHdo63sCpZK2Qp3s9oW4zVpDIEj/iMSt5xbjlZKqvYuLCaJiaHhal uQi0zvrnDRXPHjGMRY9rEMVcOw93mroJNcLAJ99lMFUnCwY1BQE+g8ZNLpw3IKeEsg9n 9hRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RwsedNDTKts66Uf/cUt0lXtmwdA1RwOLSlvaMbWJEv0=; b=yiEOJHT6rFfv3NxJ5UkutUYHdieLpAVFXF/yii51Bq/RnuZQm+XSbUCT7gu9y2cYKi GEBpjnsl1ArBbh3cjmEJTcIHJZpJp9MkpyOkYekDWSp7B6/ltLdtj/38193Jc/RAjBzi eCL9agkVwcOQ5nUio5gF7iCLHJNVStlkIxaedvC/JI7+eJZ+UzmUBTwpp7cQNv9GI2cg oUGlX/nYERU26x1Sf2k0eEpX2apQxIFrLDBe4LyxZ7jxWeAe1XlCNhtRXl9snw1x4fVw fbV8/pgcH9svbIzBkfQ9c3DqhnbeE4LbN34Ce96eSAO4seHAVT0zkIc1IbXiRXoYBgih 1t9A== X-Gm-Message-State: AO0yUKW3mr9moYiywxwv7q9kTx/c19vDiv+eMsXsqBf+m5H3KFbpSRuV 0yLFH01V7beuH3nEQXTBUxL2h7zM1ASRvA31pP8= X-Google-Smtp-Source: AK7set8qBkAYjZfMX39/jGlZ2HTj/eAo0g17q1jF6Yb/hvdmW+0e3t/AuBYqg6JpiphLMTzz8/1pzg== X-Received: by 2002:a17:90b:4d04:b0:234:d42:1628 with SMTP id mw4-20020a17090b4d0400b002340d421628mr904313pjb.10.1677538904943; Mon, 27 Feb 2023 15:01:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 12/21] target/arm: Handle Block and Page bits for security space Date: Mon, 27 Feb 2023 13:01:13 -1000 Message-Id: <20230227230122.816702-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539015666100003 Content-Type: text/plain; charset="utf-8" With Realm security state, bit 55 of a block or page descriptor during the stage2 walk becomes the NS bit; during the stage1 walk the bit 5 NS bit is RES0. With Root security state, bit 11 of the block or page descriptor during the stage1 walk becomes the NSE bit. Rather than collecting an NS bit and applying it later, compute the output pa space from the input pa space and unconditionally assign. This means that we no longer need to adjust the output space earlier for the NSTable bit. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 91 ++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 73 insertions(+), 18 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0c07e5e24f..887c91ed13 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -958,12 +958,14 @@ static int get_S2prot(CPUARMState *env, int s2ap, int= xn, bool s1_is_el0) * @mmu_idx: MMU index indicating required translation regime * @is_aa64: TRUE if AArch64 * @ap: The 2-bit simple AP (AP[2:1]) - * @ns: NS (non-secure) bit * @xn: XN (execute-never) bit * @pxn: PXN (privileged execute-never) bit + * @in_pa: The original input pa space + * @out_pa: The output pa space, modified by NSTable, NS, and NSE */ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) + int ap, int xn, int pxn, + ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { bool is_user =3D regime_is_user(env, mmu_idx); int prot_rw, user_rw; @@ -984,7 +986,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_i= dx, bool is_aa64, } } =20 - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { + if (out_pa =3D=3D ARMSS_NonSecure && in_pa =3D=3D ARMSS_Secure && + (env->cp15.scr_el3 & SCR_SIF)) { return prot_rw; } =20 @@ -1252,11 +1255,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap, ns, xn, pxn; + int ap, xn, pxn; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; + ARMSecuritySpace out_space; =20 /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1439,8 +1443,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, ptw->in_ptw_idx +=3D 1; ptw->in_secure =3D false; ptw->in_space =3D ARMSS_NonSecure; - result->f.attrs.secure =3D false; - result->f.attrs.space =3D ARMSS_NonSecure; } =20 if (!S1_ptw_translate(env, ptw, descaddr, fi)) { @@ -1558,15 +1560,75 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, } =20 ap =3D extract32(attrs, 6, 2); + out_space =3D ptw->in_space; if (regime_is_stage2(mmu_idx)) { - ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; + /* + * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. + * The bit remains ignored for other security states. + */ + if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { + out_space =3D ARMSS_NonSecure; + } xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { - ns =3D extract32(attrs, 5, 1); + int nse, ns =3D extract32(attrs, 5, 1); + switch (out_space) { + case ARMSS_Root: + /* + * R_GVZML: Bit 11 becomes the NSE field in the EL3 regime. + * R_XTYPW: NSE and NS together select the output pa space. + */ + nse =3D extract32(attrs, 11, 1); + out_space =3D (nse << 1) | ns; + if (out_space =3D=3D ARMSS_Secure && + !cpu_isar_feature(aa64_sel2, cpu)) { + out_space =3D ARMSS_NonSecure; + } + break; + case ARMSS_Secure: + if (ns) { + out_space =3D ARMSS_NonSecure; + } + break; + case ARMSS_Realm: + switch (mmu_idx) { + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: + case ARMMMUIdx_Stage1_E1_PAN: + /* I_CZPRF: For Realm EL1&0 stage1, NS bit is RES0. */ + break; + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + /* + * R_LYKFZ, R_WGRZN: For Realm EL2 and EL2&1, + * NS changes the output to non-secure space. + */ + if (ns) { + out_space =3D ARMSS_NonSecure; + } + break; + default: + g_assert_not_reached(); + } + break; + case ARMSS_NonSecure: + /* R_QRMFF: For NonSecure state, the NS bit is RES0. */ + break; + default: + g_assert_not_reached(); + } xn =3D extract64(attrs, 54, 1); pxn =3D extract64(attrs, 53, 1); - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, p= xn); + + /* + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security space. + */ + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, ap, xn, pxn, + result->f.attrs.space, out_space); } =20 if (!(result->f.prot & (1 << access_type))) { @@ -1593,15 +1655,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, } } =20 - if (ns) { - /* - * The NS bit will (as required by the architecture) have no effec= t if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - result->f.attrs.secure =3D false; - result->f.attrs.space =3D ARMSS_NonSecure; - } + result->f.attrs.space =3D out_space; + result->f.attrs.secure =3D arm_space_is_secure(out_space); =20 /* When in aarch64 mode, and BTI is enabled, remember GP in the TLB. = */ if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TNo1abJPmKBNh/vFLOZMsXlNw7z0lrzbcY3tJpdOOx8=; b=mqmlJ+7fY3f9OsbmAn+FuYU7GfWjo36K2WF6bsKZaFN5hUZpCaX1+XH9imPNSVgC8I EC0EQkj+xHq+v58Fa98jjLQmwkBRRyuXUqiaQjkWkMVC1lCobz6lNUzHupVnBcBSvxoW RUp8RpuDxCIZ3Uz4f7HGhIfN9GiaaGz/A/MrJ7PuNMnEIJc8sinmDpRJFLZSNXxJW/pC TDywzz/ZKqOQkYNe+qrS/fx2dbfVStTy0iyAcSxiHVxZGIi4EIktzdIrxEcnY+C9TdDP gDUyzhhsGuTmthDrgWMF/9qWRQr3RTmwl5I5lnZ4/JWiNZ9WiltGr9qETwvDthTNUn+l UmTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TNo1abJPmKBNh/vFLOZMsXlNw7z0lrzbcY3tJpdOOx8=; b=sZOMDj65RO8xdYIZVHq+ks94vCAU/uEmHvfgF/1QkUwlcd1uLO5C7BotOQA8sj1Z+a 01GcsTor7WNemIN5ixD33SFq3yHbGViS8oKLJFZMl0M9jevpGbrjwM4P2v/ZASDUrimn SaS/A7ShSkDO1GkG0iqSea3/tS9BeNbg5mAxqWWa71leX9SzDXs0NStX5hF6hkdVmWf7 zhZJdbMXIk5Wa7qS9IFE/LH1fDFfTMiza2uR+JmYCJwQ1I2ulGxcxYHyyamzn69Lr32K DMOxQWwYy/8WUz9ypR5jg/hx3Kzg++FvXpYKZ9hJ3r1cfHH3Au8LJwdwuivAkSret7Iz jcfw== X-Gm-Message-State: AO0yUKVthIMDS2mBJAZnpiOesmpjl2GbLKSQNvuoyycuTscMlK1rpI1C IdRr1Pj1krnyvyBQsh1jdZkNSYQEa/jJmi0a+aQ= X-Google-Smtp-Source: AK7set8ZfQY9/w6yI2lD3gmEsvseWlD0ZeJK/bWe7C4qWM/E3Dn7I509f9MVTkGcd9onivUex5nGIA== X-Received: by 2002:a17:90b:3881:b0:234:1645:5266 with SMTP id mu1-20020a17090b388100b0023416455266mr825456pjb.30.1677538906751; Mon, 27 Feb 2023 15:01:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 13/21] target/arm: Handle no-execute for Realm and Root regimes Date: Mon, 27 Feb 2023 13:01:14 -1000 Message-Id: <20230227230122.816702-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539104308100003 Content-Type: text/plain; charset="utf-8" While Root and Realm may read and write data from other spaces, neither may execute from other pa spaces. This happens for Stage1 EL3, EL2, EL2&0, and Stage2 EL1&0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 52 ++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 887c91ed13..2eae7a69cb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -911,7 +911,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +static int get_S2prot_noexecute(int s2ap) { int prot =3D 0; =20 @@ -921,6 +921,12 @@ static int get_S2prot(CPUARMState *env, int s2ap, int = xn, bool s1_is_el0) if (s2ap & 2) { prot |=3D PAGE_WRITE; } + return prot; +} + +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot =3D get_S2prot_noexecute(s2ap); =20 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -986,9 +992,39 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_= idx, bool is_aa64, } } =20 - if (out_pa =3D=3D ARMSS_NonSecure && in_pa =3D=3D ARMSS_Secure && - (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; + if (in_pa !=3D out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + return prot_rw; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + switch (mmu_idx) { + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + return prot_rw; + default: + break; + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + return prot_rw; + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } } =20 /* TODO have_wxn should be replaced with @@ -1565,12 +1601,16 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. + * R_YMCSL: Executing an insn fetched from non-Realm causes + * a stage2 permission fault. */ if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { out_space =3D ARMSS_NonSecure; + result->f.prot =3D get_S2prot_noexecute(ap); + } else { + xn =3D extract64(attrs, 53, 2); + result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } - xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); } else { int nse, ns =3D extract32(attrs, 5, 1); switch (out_space) { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539092; cv=none; d=zohomail.com; s=zohoarc; b=LF4Fk70w6kcIGheifzmGGoMt97K5LfO7KPHZ8bfPwdIhNGrgX0pej6Ma7DeZWZUnHKt7mCWpFLLMMdStJyOpT0XJYCiNjk8RTRBfIZyiotIttuK5JzIEn9grs5LXAjXnQwLrDk9ByNZqdOkDdhRyBlkYRyo9UWHM3sUEggUyv7E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677539092; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AKzOS7a1/7VrG1zwCTYqvRSxgc9GTxbO/gKX1CrEEmc=; b=l57naG/Ps4BvmLtGg3M4c6gmPivXwciQ/J1lBVrTsR47GrT1D88mmtRybDuACvkVrtJNfTh5StVb9k9P7wSRDEahToH9N30W7mInJS96cR0ek7HcNAAsHoQq8vouvXT5Zs/jnowvkErpDEneA4FHlP5Pto94IEHM6IMMNjekZlo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677539091996577.8193622455979; Mon, 27 Feb 2023 15:04:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVV-0000Kb-KZ; Mon, 27 Feb 2023 18:02:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmVD-0007wA-UC for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:56 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmVB-00013C-7w for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:51 -0500 Received: by mail-pj1-x1030.google.com with SMTP id h17-20020a17090aea9100b0023739b10792so7780697pjz.1 for ; Mon, 27 Feb 2023 15:01:48 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AKzOS7a1/7VrG1zwCTYqvRSxgc9GTxbO/gKX1CrEEmc=; b=khnllu7UiJfE+VCzWMdUIuBYp5kalyLXLEWdRLejppfslZJUt67nXdqbrRfCJvKLXv LB8rW10NG92BFTfP48ru/4cC7WUnXkjobcPSwa6hs3J/KvzImq/TsQ6DwH2aNNm1t5vR uAdK4iU1xRprAzajM21j24SLo03HVk9aRSrolB1gopqK7G40g5XxAdikhQuyXPOx+msX CPjohRheohjr2ljfBmynoecY24xqENe/f64KTf5x0EZ4AVvzDlQbxsHKTUVWzjXeJyaS 2WzOadyW//DbXg1R/fAcucH4re0KWEDcP3qClirAjN4nTqVoJfjDYS8xaT7mxAGmnGzY QN6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AKzOS7a1/7VrG1zwCTYqvRSxgc9GTxbO/gKX1CrEEmc=; b=LI6pVZLQHBuVglsVUlFXe+gbabUL7jY3pfrgdIzJK3M2aGuGTrd2ktpCc7/KS88Ljb KvWYQ5ggjDVKQ83aTMCgZJFqGypsK/GtCm9GmYG+F8+FwphfhSUoixHDVE8p2P2rWJJp q53GOCRV6eQFy/UH0yjYTOzB0JV2L6kYbK2VRHTm1xd95bR/QWbnfN7HjAp3CHmHBno8 XgGGS2pm0Q93ihOEOscdS5SyBvpC9MUeBnKSZph8gRxJyw7219YNztEoFX3sOIlWEwd8 +pEJMXO5KEDt7TCnsvM2IIZw+3//VRCg17vGgcZ8n83tr4e2afeycifuuTORZCwDGWC6 rFww== X-Gm-Message-State: AO0yUKUdfDLlI+myXYyjnJVVOUgAsztZabzVaaQEeD2zIHigHXxtGDb3 9vzSb7Ttp8KYvMxIkbfMK9C2Uxg/1QOnyvttbJM= X-Google-Smtp-Source: AK7set9lCYGyhCNPLYRwdXI3d+n3mryCtnOyTJnQT3XMm2D5yhJsbo1keQTzpkS7Nfn4sPV6bhc5IQ== X-Received: by 2002:a17:90b:33c4:b0:234:8cd:c0e4 with SMTP id lk4-20020a17090b33c400b0023408cdc0e4mr891532pjb.23.1677538908475; Mon, 27 Feb 2023 15:01:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 14/21] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate Date: Mon, 27 Feb 2023 13:01:15 -1000 Message-Id: <20230227230122.816702-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539094198100003 Content-Type: text/plain; charset="utf-8" Do not provide a fast-path for physical addresses, as those will need to be validated for GPC. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2eae7a69cb..0177dea0cf 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -232,29 +232,22 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ - if (regime_is_stage2(s2_mmu_idx)) { - S1Translate s2ptw =3D { - .in_mmu_idx =3D s2_mmu_idx, - .in_ptw_idx =3D arm_space_to_phys(space), - .in_space =3D space, - .in_secure =3D is_secure, - .in_debug =3D true, - }; - GetPhysAddrResult s2 =3D { }; + S1Translate s2ptw =3D { + .in_mmu_idx =3D s2_mmu_idx, + .in_ptw_idx =3D arm_space_to_phys(space), + .in_space =3D space, + .in_secure =3D is_secure, + .in_debug =3D true, + }; + GetPhysAddrResult s2 =3D { }; =20 - if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD, - false, &s2, fi)) { - goto fail; - } - ptw->out_phys =3D s2.f.phys_addr; - pte_attrs =3D s2.cacheattrs.attrs; - pte_secure =3D s2.f.attrs.secure; - } else { - /* Regime is physical. */ - ptw->out_phys =3D addr; - pte_attrs =3D 0; - pte_secure =3D is_secure; + if (get_phys_addr_with_struct(env, &s2ptw, addr, + MMU_DATA_LOAD, &s2, fi)) { + goto fail; } + ptw->out_phys =3D s2.f.phys_addr; + pte_attrs =3D s2.cacheattrs.attrs; + pte_secure =3D s2.f.attrs.secure; ptw->out_host =3D NULL; ptw->out_rw =3D false; } else { --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539007; cv=none; d=zohomail.com; s=zohoarc; b=NlEyKbE2M+DQvOlN0o/Anixs5UHWAei7QSzZkED0yUfzFs+RH0e25hzRQWR3QK2oX2dWvEeEdMpsxROhLuL2VT7clqF9eg4X2cTzBVgJ3k25pEzEXSs3ejNxmXbvnEozlLubQDoB5j4laoJ7ZmmMmXjEB0xnOjIyQsgIhNr2Nyw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677539007; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CXUGcnVq4p+V6/QgEEXXaOcAhNQGJeh+oZJI6zT9+Xw=; b=J6MFisB9A8HF5hwCUyVTMvNRKUMVCes09gty53Tqx20leEgSOHIfNcCOdqJH0oqXpbd+2vK1gldNYEWWAsVciJyabkaeP7L2ZH945PrEdrRFInXLlT8XWOlQx+vikS6TvKnEoOC7csNmgmc2B0+fjqZ3rJCvD/WdRb5ten6izcY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677539007180849.9736264810633; Mon, 27 Feb 2023 15:03:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVU-0000Av-0M; Mon, 27 Feb 2023 18:02:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmVF-0007wa-OB for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:56 -0500 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmVD-000150-Cg for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:52 -0500 Received: by mail-pl1-x635.google.com with SMTP id bh1so8468423plb.11 for ; Mon, 27 Feb 2023 15:01:50 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CXUGcnVq4p+V6/QgEEXXaOcAhNQGJeh+oZJI6zT9+Xw=; b=SgZmI9CvnIHXSfJM1HQCZTw17NYAZNbE6CBN8gaikgZS/xfwVyw6pLa3N4bq84vpoy g+IhAQpW7nGipAmihyNFkO+8Y8GNNNSs16owSOms5OONZ8Or2KfxlI1Uc4iTyZsYzm/D FVmRfPHT2jUParQ9P3xzX9+/6H+O0P8cRQDHw001ABIgJ6hkq/kDVSaPtjAjMq+oeJZ6 UDtSZw1Cm51h+LL2mpgR+m9fC0yaxZ30g80qI7d7fChUmNHFnwQZss9+Z61sMy6pLHSz AYbu0mYEgG1gn2dUNcgEpH8jbE6586t/7knJnsFyOKUWF8uMJJRqSLGpXkQEgr8sN9W5 kGHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CXUGcnVq4p+V6/QgEEXXaOcAhNQGJeh+oZJI6zT9+Xw=; b=naniIq/uLI48CNMT0QxHUm0mTmBDqwpdzx4r6hoXziirDhPMGpoixYRKFJ9wYmkMSt JitqBSJBvjw80HjUH2SNR4hMIz0/0RHPzVgnAuJ8RHa6dNff3KfRROPoo4WkNbasI8yv 0EB8lYskiym8pRmB9UDwR1yVeX2A9nLMcLTk22pUmsivL/SHfchftt/a+sFh+4Ug7OCI +cLfVV1kjeD7/TyJOWgICEfvc94A5C8mkbOWV0gaVK4fQh/5hiRBnlYVjRCtH5ppl1+T OTskOeyMkcziq02+q2/T9IhdVxtfb1K40h81vH0qchcATcBSAa2a2Kd4j/gevPh8e+xK 9nJQ== X-Gm-Message-State: AO0yUKUWipTGThZTvkviLhsT5oygiWHYQcCCFA77++umLI6vujillCwK ayFyZJKtg8akJXK1A0e9vU9mNyxJh2qiOQj8SVE= X-Google-Smtp-Source: AK7set94q790ou54rMvpg/3n5o4NuVcXUrOXpyucBcr1+GxpEO9jyc5v4BcHYOVUM3LHPIz5c00LNg== X-Received: by 2002:a05:6a20:4287:b0:c7:13be:6dec with SMTP id o7-20020a056a20428700b000c713be6decmr1347819pzj.15.1677538910029; Mon, 27 Feb 2023 15:01:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH for-8.0 v4 15/21] target/arm: Move s1_is_el0 into S1Translate Date: Mon, 27 Feb 2023 13:01:16 -1000 Message-Id: <20230227230122.816702-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539007607100005 Instead of passing this to get_phys_addr_lpae, stash it in the S1Translate structure. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0177dea0cf..eb3f37495c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -22,6 +22,12 @@ typedef struct S1Translate { ARMSecuritySpace in_space; bool in_secure; bool in_debug; + /* + * If this is stage 2 of a stage 1+2 page table walk, then this must + * be true if stage 1 is an EL0 access; otherwise this is ignored. + * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. + */ + bool in_s1_is_el0; bool out_secure; bool out_rw; bool out_be; @@ -32,8 +38,7 @@ typedef struct S1Translate { } S1Translate; =20 static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + uint64_t address, MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi); =20 static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, @@ -1259,17 +1264,12 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_= aa64, uint64_t tcr, * @ptw: Current and next stage parameters for the walk. * @address: virtual address to get physical address for * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @s1_is_el0: if @ptw->in_mmu_idx is ARMMMUIdx_Stage2 - * (so this is a stage 2 page table walk), - * must be true if this is stage 2 of a stage 1+2 - * walk for an EL0 access. If @mmu_idx is anything else, - * @s1_is_el0 is ignored. * @result: set on translation success, * @fi: set to fault info if the translation fails */ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, uint64_t address, - MMUAccessType access_type, bool s1_is_el0, + MMUAccessType access_type, GetPhysAddrResult *result, ARMMMUFaultInfo = *fi) { ARMCPU *cpu =3D env_archcpu(env); @@ -1602,7 +1602,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.prot =3D get_S2prot_noexecute(ap); } else { xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, s1_is_el0); + result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } } else { int nse, ns =3D extract32(attrs, 5, 1); @@ -2824,7 +2824,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, bool ret, ipa_secure, s2walk_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space, s2walk_space; - bool is_el0; uint64_t hcr; =20 ret =3D get_phys_addr_with_struct(env, ptw, address, access_type, resu= lt, fi); @@ -2849,7 +2848,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, s2walk_space =3D ipa_space; } =20 - is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; + ptw->in_s1_is_el0 =3D ptw->in_mmu_idx =3D=3D ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx =3D s2walk_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Sta= ge2; ptw->in_ptw_idx =3D arm_space_to_phys(s2walk_space); ptw->in_secure =3D s2walk_secure; @@ -2868,8 +2867,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, ret =3D get_phys_addr_pmsav8(env, ipa, access_type, ptw->in_mmu_idx, is_secure, result, fi); } else { - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, - is_el0, result, fi); + ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); } fi->s2addr =3D ipa; =20 @@ -3045,8 +3043,7 @@ static bool get_phys_addr_with_struct(CPUARMState *en= v, S1Translate *ptw, } =20 if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, ptw, address, access_type, false, - result, fi); + return get_phys_addr_lpae(env, ptw, address, access_type, result, = fi); } else if (arm_feature(env, ARM_FEATURE_V7) || regime_sctlr(env, mmu_idx) & SCTLR_XP) { return get_phys_addr_v6(env, ptw, address, access_type, result, fi= ); --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539122; cv=none; d=zohomail.com; s=zohoarc; b=P0cX4ddNsMfwhGL5MWcJj0Fla7IW/OTZO2JiLEzDylc+GLRQuFL6ugiL66XNuxC7xx/+jyg2Ph0t/EmNWxAwrPHFa5h1hXSRximD0EeLdMz9kLoxDZ71FcYJSAlN5v2jRzftDkXkikBpJiyZtjsvUaCAMtRMZN4teZxjWto9IhU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677539122; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WXHoQLeqrbXEjWVkbOYob2JhZTOWiyKZZ2KU5aalHNo=; b=SBxkWmIwBdqPqVytdYHivn/JrgePadsb0KYzVocvZA6nQX3B9c4yNTnEHbI+cMWibotZ4+GNmLmFcQwkkepUlzOeGP2jPAeJYNyT9rcQZj29p03UtSuajhbvQKrtE+ul+MvUsec4yngL0idJJNFuqJEDyILISw/8Pmjf1qFwVPs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677539122751137.23357415832663; Mon, 27 Feb 2023 15:05:22 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVR-0008OX-0h; Mon, 27 Feb 2023 18:02:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmVJ-0007xI-F7 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:02:01 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmVF-00015d-HN for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:56 -0500 Received: by mail-pj1-x102a.google.com with SMTP id q31-20020a17090a17a200b0023750b69614so7731370pja.5 for ; Mon, 27 Feb 2023 15:01:52 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WXHoQLeqrbXEjWVkbOYob2JhZTOWiyKZZ2KU5aalHNo=; b=gdidk/VhFLaj3VqljZ5o1gIlHpzeITDJPdc08wuGRMklA414hXkOSxLa2Lv3Z0jI52 S/hMIcmkd+cfIA/FbGS/MXluTF94GNmR4QmHPH3d/2GL1lcodTa66iVYjqZtT5NuPF6u SIO6KvUjFM2YtF6gIxIms+biPOMDefiIf/TNIzyNtUPHBfO4s4N3D6rhM1XL1vifUxC1 LNhYzAfTeesMvbv13I00XZiuealgk4ft3FsPfh6KqhP6YH4lE5YLkmjfHdp6f2yDFw6u dzy+gHVD9RfbZz/j53Q0bUCM7nnwt+XBIs2E7wiL2bh412nqPhNm6vUAmwhSuFHGY3M+ TEHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WXHoQLeqrbXEjWVkbOYob2JhZTOWiyKZZ2KU5aalHNo=; b=2aEs4qeHjfybKlWoI06clz2n0PvX4f4ckDV9/Pk1tOZlt9fyRPisWrHBTYKCAD7uML PaVJDj3H6PIWmk3K3j4eB75NU7Pbt4rAjAWOhRRJpUXC242yLOjzLO+AP0ShmZNlgFrf PofhhmWuJ1upq2V7BA11lnK9wTVT9SBezp4kR04GNeckBaFYk6RueYpyxY0+RjpF4ZdT 6N/WHmOhQJEVrHxKiovjVm7FfHrxU/Jd++ExdVDqIH2EilMbo88UtBvWHcDVaaJ/lTuo jAhKzPpscGPtMmgd0nQHECP/nASV31S6Grzjo/jD8cMlMyfZUJV2k/495i38XSK+2HSC YOsQ== X-Gm-Message-State: AO0yUKW4SAUT/6EfFgwoZprRi8H81/di7KO4hSWJnt2Vwq6Xc6pZ4nLX WnmZ57yaO7rTH+ZeuT+RVKXFs5ucjsPPG0thDtY= X-Google-Smtp-Source: AK7set9F/Yu0J95E2vD7q2pqd5oHV/mwSD3ZjICIK9NzhAVJdlz1zWeh619QnrUwFP2d44i8oCX/5g== X-Received: by 2002:a17:90b:4a4b:b0:234:b786:6869 with SMTP id lb11-20020a17090b4a4b00b00234b7866869mr831600pjb.26.1677538911720; Mon, 27 Feb 2023 15:01:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH for-8.0 v4 16/21] target/arm: Use get_phys_addr_with_struct for stage2 Date: Mon, 27 Feb 2023 13:01:17 -1000 Message-Id: <20230227230122.816702-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539124398100003 This fixes a bug in which we failed to initialize the result attributes properly after the memset. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/ptw.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index eb3f37495c..95424bca4c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -37,10 +37,6 @@ typedef struct S1Translate { void *out_host; } S1Translate; =20 -static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, - uint64_t address, MMUAccessType access_type, - GetPhysAddrResult *result, ARMMMUFaultInfo = *fi); - static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, @@ -2863,12 +2859,7 @@ static bool get_phys_addr_twostage(CPUARMState *env,= S1Translate *ptw, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - if (arm_feature(env, ARM_FEATURE_PMSA)) { - ret =3D get_phys_addr_pmsav8(env, ipa, access_type, - ptw->in_mmu_idx, is_secure, result, fi); - } else { - ret =3D get_phys_addr_lpae(env, ptw, ipa, access_type, result, fi); - } + ret =3D get_phys_addr_with_struct(env, ptw, ipa, access_type, result, = fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539058; cv=none; d=zohomail.com; s=zohoarc; b=RYB/dPXPLTxjd753kSzCJ/xsqJJTk4hAk7VV3oZbz5rkSDFX3VhEzXXtXrQVtGMd9Mqh8AEYOfF1qQC8SBKhU4Zobg4/2Vl+MxTAvbcworx+lYfC5IokV22tiaA+dyajHVN/0b2hFMqVfD76TJXTjLEi1prOs87MfK0th+zIb50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677539058; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=S9FR2Wrgrfm7jib0Rt22KYuQdB3JvMm3uUDf3dn/w3iSIdTIuBjv8kSoG9W5yTVqTUrKeFmNJiUzI/jRD0Wl2FXsKayOfMzAsBZwQqUYvbIjtvc0w/o5tvzbw3y1b0Sgy0TE/SJlz8IUeeoqxAnGy7PLugLCf/gqMDZO0/SAcy4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677539058232516.9459728353818; Mon, 27 Feb 2023 15:04:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVU-0000EY-T8; Mon, 27 Feb 2023 18:02:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmVK-0007xQ-RR for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:02:01 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmVH-000160-RK for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:57 -0500 Received: by mail-pl1-x62b.google.com with SMTP id bh1so8468581plb.11 for ; Mon, 27 Feb 2023 15:01:54 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=TJrGn2ZWEhXVIu936f+7Yx3wEJHuml2EvqSC2JEYKiyGyhS9x2yWfuBeZ3jw1QdLYe dneVW4I2ZhsYA4PHG1Zcj8gwiobVjg4TXDpht3Uw1i4RUCl2ZXnfdL+EUGfXXcsPlLtQ dPLkVGvVEgHyvoXPzYy3tjpmfyQRdYBnqf/tLBIwFnCFxP7J0f5wlMRu7oYm8qs2Ll/K KHSBML1CZlxh5TDFDjBk3kYGh8O3J+HRzyylGETkhTGGIYuuHLzPjmf1AA5w01ZovBD3 5nDGhsJ29yezKdL2E2VZrCVdTdsXsfPZkirVbgSvjWmBBOcJbnSle6hoq+yL/bsKXBqy xeYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BdnIrBC/vjhypfMOEhRm01STyDVGWe2QDHvXiznUOKk=; b=CZlVseO0SlDVz/pfx3ajC0hXbIMg5xtY6fN83QGARjqmS5FoDgzkSmvOtSDzQupK2L qZz/BvyKz3NStUp9g09oipSgMDqGPe5bjAPbcXX+WxyapUUVQdthJP9IS7uGZ+0UGb8q OaPt5Ykcj36Srl/GhOJkox/ICO/bb474LV7OmDrbLrOyJis2uM6TMZknxvoP1fxRv0IK XrD24J0fAIT5rhBPeGVTda7cS0WcPhKslSyF/xta68QbxKep5eN27Db16I2MBLsXVZRh VwSZ2v0IyMcZBbAc0h6Yvh9IltoipBrW/wuOOpEm79EnQR0/hH9X08KWdEDB0YAOD2aE dDOg== X-Gm-Message-State: AO0yUKU/xGh+nG7I01TpKIbskOQTeiypOIVJC4wiuXcfyTD67nwtfPG+ 6aA3e37wsoIfUHXx736op/5SI8Mj18USny469/A= X-Google-Smtp-Source: AK7set9BA0ntFTNwxCf4D/xN/E2xUkFQd4BiLug6kOFhXOpeDWN4lhDjMLsea0DXAnEFYHx4zmSEKw== X-Received: by 2002:a17:90b:1805:b0:234:b2a:8251 with SMTP id lw5-20020a17090b180500b002340b2a8251mr1002546pjb.0.1677538913237; Mon, 27 Feb 2023 15:01:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 17/21] target/arm: Add GPC syndrome Date: Mon, 27 Feb 2023 13:01:18 -1000 Message-Id: <20230227230122.816702-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539059802100003 Content-Type: text/plain; charset="utf-8" The function takes the fields as filled in by the Arm ARM pseudocode for TakeGPCException. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index d27d1bc31f..62254d0e51 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -50,6 +50,7 @@ enum arm_exception_class { EC_SVEACCESSTRAP =3D 0x19, EC_ERETTRAP =3D 0x1a, EC_SMETRAP =3D 0x1d, + EC_GPC =3D 0x1e, EC_INSNABORT =3D 0x20, EC_INSNABORT_SAME_EL =3D 0x21, EC_PCALIGNMENT =3D 0x22, @@ -247,6 +248,15 @@ static inline uint32_t syn_bxjtrap(int cv, int cond, i= nt rm) (cv << 24) | (cond << 20) | rm; } =20 +static inline uint32_t syn_gpc(int s2ptw, int ind, int gpcsc, + int cm, int s1ptw, int wnr, int fsc) +{ + /* TODO: FEAT_NV2 adds VNCR */ + return (EC_GPC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (s2ptw << 21) + | (ind << 20) | (gpcsc << 14) | (cm << 8) | (s1ptw << 7) + | (wnr << 6) | fsc; +} + static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int = fsc) { return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT) --=20 2.34.1 From nobody Sat May 4 07:27:28 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677538977; cv=none; d=zohomail.com; s=zohoarc; b=DiU4GtjjljA0om9p8viTR276GO7XR2C+O4qtpPPzoo2S+Az7dJWKgQYh9/c39rPAaKDN8OI8sNS8Pz12Pa+PwYD/ReSfBfZnWtp3KQO7OJxlUy3CkmP6dGrcmU0OPtltyDmy6t4plTmpYrYoj46FpEYzh/ZhmN17zA9+9L89fYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677538977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=br+OcGschTWgfPIedhbqHTnE0emVLTZCCCRg9OewAXg=; b=N16SFOoF6w1Rk0swIs8SmAEyaZtR95vzTIxFHPCiJxJ+jsjYu9gCWOO7bHZsk6en+c8zv/Ttpt0fdhMbeWK8wPF1WdT/r4kYyStMvtKb6GDHe8l5YgpQnYoarIvMMI/kZ2XZLL0LRCEJf6ErFegoC0gZk0sKcbY1QXnhn/K5a/k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677538977533375.58719538231514; Mon, 27 Feb 2023 15:02:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVU-0000EX-R1; Mon, 27 Feb 2023 18:02:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmVK-0007xP-Rj for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:02:01 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmVH-0000zq-Rt for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:01:57 -0500 Received: by mail-pj1-x102b.google.com with SMTP id c23so7834565pjo.4 for ; Mon, 27 Feb 2023 15:01:55 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=br+OcGschTWgfPIedhbqHTnE0emVLTZCCCRg9OewAXg=; b=HNI4jPYgC6jotE4bRjeH+Rsuom4hj+dfl68nch9mbbqJAraYX9kZoL4vwmoKwBAVKc HnwuuaAO7s+euvWjPZao4r+rGmYNJP4yrTJmBBeEHuanJGqz6JV64btoAFH9S2376+n6 Ty/e60f8hYhP9vl5zegntwX1+SpxvvOuyi0849dV+3E2HtJfRdnll04LtPBgNN9mK8FA LOd1kNuEkdYL48jz9tR41mYdjgnPQiIZBaaWgQsCxw5NF8c6pqLHVdb9dwr+ofIVIt45 D5dsgpruGenZQf5G01duO+Tsu6bcjbl9PDuXbGhpzhZmNghkN85661kqlbeu35tktnI+ y2JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=br+OcGschTWgfPIedhbqHTnE0emVLTZCCCRg9OewAXg=; b=dviWdhLrmNqRpPdF9TDatoX6RfIafDkcBHGOpgkKHqt77wvZAeaP13iSNr+YZTp0rj PoIIJS8fws10VbdRZjo6lFpx2NQzn1sMxAQBBOVDmlzPuRUw13/EhPjKBqslgvrfbg1Y UgidTCmA3XaJoqpjlogybS/iJ55x+DDxc3cta48FdCDmM9bJRLyJaFi+qlh+FkZBB82l 15cPaHYKAr+iZCpV5vrLgb7J3pydGHiNrNT0ikHhhpsN2iLgbbUM8rFKYwmyIvh4M+xc yw0m9hFCLdBj5E0nyoEBhgn3Ntikc/n/bIRGe88yx4n2b2tAKMPcUUBY4cJ8+6OKoKoh SRzg== X-Gm-Message-State: AO0yUKVPDmIVzRKzyrOUTy62iH/qCy76fWbNm2TaK4RxXAOs/zOWzDo6 GHMX9ZxTJVFMcxl9Ss7xL/CKqk44J6+3D2ffU3g= X-Google-Smtp-Source: AK7set/6kLkGzZDkacTRkFczc+ypGsJEFpgA3eUbJE0gkgm0PZ+BMSjXKlZqcQCezmWMsTZelD+K/Q== X-Received: by 2002:a05:6a21:3290:b0:cb:a2eb:841f with SMTP id yt16-20020a056a21329000b000cba2eb841fmr1216565pzb.53.1677538914778; Mon, 27 Feb 2023 15:01:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 18/21] target/arm: Implement GPC exceptions Date: Mon, 27 Feb 2023 13:01:19 -1000 Message-Id: <20230227230122.816702-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538979524100003 Content-Type: text/plain; charset="utf-8" Handle GPC Fault types in arm_deliver_fault, reporting as either a GPC exception at EL3, or falling through to insn or data aborts at various exception levels. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 27 +++++++++++ target/arm/helper.c | 5 ++ target/arm/tcg/tlb_helper.c | 96 +++++++++++++++++++++++++++++++++++-- 4 files changed, 126 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05fd6e61aa..b189efadf8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 +#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/internals.h b/target/arm/internals.h index 680c574717..80aa6d0ede 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -352,14 +352,27 @@ typedef enum ARMFaultType { ARMFault_ICacheMaint, ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ + ARMFault_GPCFOnWalk, + ARMFault_GPCFOnOutput, } ARMFaultType; =20 +typedef enum ARMGPCF { + GPCF_None, + GPCF_AddressSize, + GPCF_Walk, + GPCF_EABT, + GPCF_Fail, +} ARMGPCF; + /** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @type: Type of fault + * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. * @level: Table walk level (for translation, access flag and permission f= aults) * @domain: Domain of the fault address (for non-LPAE CPUs only) * @s2addr: Address that caused a fault at stage 2 + * @paddr: physical address that caused a fault for gpc + * @paddr_space: physical address space that caused a fault for gpc * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table = walk * @s1ns: True if we faulted on a non-secure IPA while in secure state @@ -368,7 +381,10 @@ typedef enum ARMFaultType { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { ARMFaultType type; + ARMGPCF gpcf; target_ulong s2addr; + target_ulong paddr; + ARMSecuritySpace paddr_space; int level; int domain; bool stage2; @@ -542,6 +558,17 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo = *fi) case ARMFault_Exclusive: fsc =3D 0x35; break; + case ARMFault_GPCFOnWalk: + assert(fi->level >=3D -1 && fi->level <=3D 3); + if (fi->level < 0) { + fsc =3D 0b100011; + } else { + fsc =3D 0b100100 | fi->level; + } + break; + case ARMFault_GPCFOnOutput: + fsc =3D 0b101000; + break; default: /* Other faults can't occur in a context that requires a * long-format status code. diff --git a/target/arm/helper.c b/target/arm/helper.c index af71caa7c7..de164c31c3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10214,6 +10214,7 @@ void arm_log_exception(CPUState *cs) [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", [EXCP_VSERR] =3D "Virtual SERR", + [EXCP_GPC] =3D "Granule Protection Check", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -10945,6 +10946,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) } =20 switch (cs->exception_index) { + case EXCP_GPC: + qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", + env->cp15.mfar_el3); + /* fall through */ case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: /* diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 31eb77f7df..b1ad20e68a 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -91,17 +91,106 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, ARMM= MUFaultInfo *fi, return fsr; } =20 +static bool report_as_gpc_exception(ARMCPU *cpu, int current_el, + ARMMMUFaultInfo *fi) +{ + bool ret; + + switch (fi->gpcf) { + case GPCF_None: + return false; + case GPCF_AddressSize: + case GPCF_Walk: + case GPCF_EABT: + /* R_PYTGX: GPT faults are reported as GPC. */ + ret =3D true; + break; + case GPCF_Fail: + /* + * R_BLYPM: A GPF at EL3 is reported as insn or data abort. + * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC + * if SCR_EL3.GPF is set, otherwise an insn or data abort. + */ + ret =3D (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el !=3D 3; + break; + default: + g_assert_not_reached(); + } + + assert(cpu_isar_feature(aa64_rme, cpu)); + assert(fi->type =3D=3D ARMFault_GPCFOnWalk || + fi->type =3D=3D ARMFault_GPCFOnOutput); + if (fi->gpcf =3D=3D GPCF_AddressSize) { + assert(fi->level =3D=3D 0); + } else { + assert(fi->level >=3D 0 && fi->level <=3D 1); + } + + return ret; +} + +static unsigned encode_gpcsc(ARMMMUFaultInfo *fi) +{ + static uint8_t const gpcsc[] =3D { + [GPCF_AddressSize] =3D 0b000000, + [GPCF_Walk] =3D 0b000100, + [GPCF_Fail] =3D 0b001100, + [GPCF_EABT] =3D 0b010100, + }; + + /* Note that we've validated fi->gpcf and fi->level above. */ + return gpcsc[fi->gpcf] | fi->level; +} + static G_NORETURN void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; - int target_el; + int target_el =3D exception_target_el(env); + int current_el =3D arm_current_el(env); bool same_el; uint32_t syn, exc, fsr, fsc; =20 - target_el =3D exception_target_el(env); + if (report_as_gpc_exception(cpu, current_el, fi)) { + target_el =3D 3; + + fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + + syn =3D syn_gpc(fi->stage2 && fi->type =3D=3D ARMFault_GPCFOnWalk, + access_type =3D=3D MMU_INST_FETCH, + encode_gpcsc(fi), 0, fi->s1ptw, + access_type =3D=3D MMU_DATA_STORE, fsc); + + env->cp15.mfar_el3 =3D fi->paddr; + switch (fi->paddr_space) { + case ARMSS_Secure: + break; + case ARMSS_NonSecure: + env->cp15.mfar_el3 |=3D R_MFAR_NS_MASK; + break; + case ARMSS_Root: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK; + break; + case ARMSS_Realm: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK | R_MFAR_NS_MASK; + break; + default: + g_assert_not_reached(); + } + + exc =3D EXCP_GPC; + goto do_raise; + } + + /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ + if (fi->gpcf =3D=3D GPCF_Fail && target_el < 2) { + if (arm_hcr_el2_eff(env) & HCR_GPF) { + target_el =3D 2; + } + } + if (fi->stage2) { target_el =3D 2; env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; @@ -109,8 +198,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |=3D HPFAR_NS; } } - same_el =3D (arm_current_el(env) =3D=3D target_el); =20 + same_el =3D current_el =3D=3D target_el; fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); =20 if (access_type =3D=3D MMU_INST_FETCH) { @@ -128,6 +217,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, exc =3D EXCP_DATA_ABORT; } =20 + do_raise: env->exception.vaddress =3D addr; env->exception.fsr =3D fsr; raise_exception(env, exc, syn, target_el); --=20 2.34.1 From nobody Sat May 4 07:27:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539097; cv=none; d=zohomail.com; s=zohoarc; b=BTkLX/8pJ4vCcdTtNm4OA6GJHskQFmkKQ4ATlgK7gQL629G4i3Ut5tYH2dSXPVjJhQ69FxnUb9KtYp9aSfsCejOYn0KwTglecv3z5B08nMMbqH5wYf1Uc0jEvYVVpAbLIp3XgW3qwHziq/tgIBegIWoTU9ECXFCzFfAX5mgEhxU= ARC-Message-Signature: i=1; a=rsa-sha256; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RTa5VZ1+2+RvKiAzovni2Fgpn0m7gqnULFZBvlHvbmc=; b=gziqo6kS3srln1fEhPZYmnGNdriZZplAru9Xyt9A7AvcLhl0WIdTOJ/GJdYovCV9wY xrw5dKAnS80+gXiVI8IG/ygdQv2Fb4vVn0hyor5f4n31F1Uod/sbhCxv+F/J6F9WXDLN 1xgtxfF8t/qspxY3bmUv9baC46aqKRQRPSEB7i3qNyesQq47BJKO+TrudG2VpIGQC13q a0YPfps7ENeV1PoiUhmYj/2noKaF03h3ROkGlsQC6/IHVumK6FTJqTjmajdyfpRPJvrK 5Q61fAR0odr2z7GbQsOjFUeLKQrKmyEfGwDrkGP4JYv7lxLJlnFIqsKTL03VCD+1Vd7Z e8ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RTa5VZ1+2+RvKiAzovni2Fgpn0m7gqnULFZBvlHvbmc=; b=pWYgo0imGlNxY0IMp5KlS+8rH8ec+a8neJk2t7CKrwFgwO41LolKy5S34ZMHOAJGVz EbBZmstGu2lSjynG8yADc9tDGomJJykFb5W0y2FSzn6+JsV6PD5G4qPSLoQDcpAo9NTg hskiaX2gjEc618pg45gZRa+/datpKF2e7Rqqs1LGhXWRlj1x+3hTtFCsqZqdC2Xb+UXc M/8/Q+sh2wxysZVQD5WthLxa0soefU40UzYbPc+j/21FO54u99F3SH/70bRwwpjqq9Di PZZKKsW/D6X9gktpXR/kDvWGu8ay9vn5vmPCufcLBGXZmbG9sMQGzRgeb4IadiozB1zD baMw== X-Gm-Message-State: AO0yUKW6KP3UI7aeOKe4V1WHu+2TZnQo/Wulersz1DCZabTC8QciP9Ug BsxGKjZZWvBndRKyuQwQmb4u9DJfTZ7c417DS36RPA== X-Google-Smtp-Source: AK7set+R2y3x5Om2MdnJyZ++/quhEYEDByA8qi03qmGgEho9t+YrHfI0nMLYHRfmtRh5wzTSvvnqRw== X-Received: by 2002:a17:902:f78b:b0:19c:f849:80a1 with SMTP id q11-20020a170902f78b00b0019cf84980a1mr638017pln.27.1677538916335; Mon, 27 Feb 2023 15:01:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH for-8.0 v4 19/21] target/arm: Implement the granule protection check Date: Mon, 27 Feb 2023 13:01:20 -1000 Message-Id: <20230227230122.816702-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539098286100006 Content-Type: text/plain; charset="utf-8" Place the check at the end of get_phys_addr_with_struct, so that we check all physical results. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/ptw.c | 249 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 232 insertions(+), 17 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 95424bca4c..f3a3a74f74 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -37,11 +37,17 @@ typedef struct S1Translate { void *out_host; } S1Translate; =20 -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, - target_ulong address, - MMUAccessType access_type, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi); +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); + +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi); =20 /* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. = */ static const uint8_t pamax_map[] =3D { @@ -197,6 +203,197 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 +static bool granule_protection_check(CPUARMState *env, uint64_t paddress, + ARMSecuritySpace pspace, + ARMMMUFaultInfo *fi) +{ + MemTxAttrs attrs =3D { + .secure =3D true, + .space =3D ARMSS_Root, + }; + ARMCPU *cpu =3D env_archcpu(env); + uint64_t gpccr =3D env->cp15.gpccr_el3; + unsigned pps, pgs, l0gptsz, level =3D 0; + uint64_t tableaddr, pps_mask, align, entry, index; + AddressSpace *as; + MemTxResult result; + int gpi; + + if (!FIELD_EX64(gpccr, GPCCR, GPC)) { + return true; + } + + /* + * GPC Priority 1 (R_GMGRR): + * R_JWCSM: If the configuration of GPCCR_EL3 is invalid, + * the access fails as GPT walk fault at level 0. + */ + + /* + * Configuration of PPS to a value exceeding the implemented + * physical address size is invalid. + */ + pps =3D FIELD_EX64(gpccr, GPCCR, PPS); + if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) { + goto fault_walk; + } + pps =3D pamax_map[pps]; + pps_mask =3D MAKE_64BIT_MASK(0, pps); + + switch (FIELD_EX64(gpccr, GPCCR, SH)) { + case 0b10: /* outer shareable */ + break; + case 0b00: /* non-shareable */ + case 0b11: /* inner shareable */ + /* Inner and Outer non-cacheable requires Outer shareable. */ + if (FIELD_EX64(gpccr, GPCCR, ORGN) =3D=3D 0 && + FIELD_EX64(gpccr, GPCCR, IRGN) =3D=3D 0) { + goto fault_walk; + } + break; + default: /* reserved */ + goto fault_walk; + } + + switch (FIELD_EX64(gpccr, GPCCR, PGS)) { + case 0b00: /* 4KB */ + pgs =3D 12; + break; + case 0b01: /* 64KB */ + pgs =3D 16; + break; + case 0b10: /* 16KB */ + pgs =3D 14; + break; + default: /* reserved */ + goto fault_walk; + } + + /* Note this field is read-only and fixed at reset. */ + l0gptsz =3D 30 + FIELD_EX64(gpccr, GPCCR, L0GPTSZ); + + /* + * GPC Priority 2: Secure, Realm or Root address exceeds PPS. + * R_CPDSB: A NonSecure physical address input exceeding PPS + * does not experience any fault. + */ + if (paddress & ~pps_mask) { + if (pspace =3D=3D ARMSS_NonSecure) { + return true; + } + goto fault_size; + } + + /* GPC Priority 3: the base address of GPTBR_EL3 exceeds PPS. */ + tableaddr =3D env->cp15.gptbr_el3 << 12; + if (tableaddr & ~pps_mask) { + goto fault_size; + } + + /* + * BADDR is aligned per a function of PPS and L0GPTSZ. + * These bits of GPTBR_EL3 are RES0, but are not a configuration error, + * unlike the RES0 bits of the GPT entries (R_XNKFZ). + */ + align =3D MAX(pps - l0gptsz + 3, 12); + align =3D MAKE_64BIT_MASK(0, align); + tableaddr &=3D ~align; + + as =3D arm_addressspace(env_cpu(env), attrs); + + /* Level 0 lookup. */ + index =3D extract64(paddress, l0gptsz, pps - l0gptsz); + tableaddr +=3D index * 8; + entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + if (result !=3D MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* block descriptor */ + if (entry >> 8) { + goto fault_walk; /* RES0 bits not 0 */ + } + gpi =3D extract32(entry, 4, 4); + goto found; + case 3: /* table descriptor */ + tableaddr =3D entry & ~0xf; + align =3D MAX(l0gptsz - pgs - 1, 12); + align =3D MAKE_64BIT_MASK(0, align); + if (tableaddr & (~pps_mask | align)) { + goto fault_walk; /* RES0 bits not 0 */ + } + break; + default: /* invalid */ + goto fault_walk; + } + + /* Level 1 lookup */ + level =3D 1; + index =3D extract64(paddress, pgs + 4, l0gptsz - pgs - 4); + tableaddr +=3D index * 8; + entry =3D address_space_ldq_le(as, tableaddr, attrs, &result); + if (result !=3D MEMTX_OK) { + goto fault_eabt; + } + + switch (extract32(entry, 0, 4)) { + case 1: /* contiguous descriptor */ + if (entry >> 10) { + goto fault_walk; /* RES0 bits not 0 */ + } + /* + * Because the softmmu tlb only works on units of TARGET_PAGE_SIZE, + * and because we cannot invalidate by pa, and thus will always + * flush entire tlbs, we don't actually care about the range here + * and can simply extract the GPI as the result. + */ + if (extract32(entry, 8, 2) =3D=3D 0) { + goto fault_walk; /* reserved contig */ + } + gpi =3D extract32(entry, 4, 4); + break; + default: + index =3D extract64(paddress, pgs, 4); + gpi =3D extract64(entry, index * 4, 4); + break; + } + + found: + switch (gpi) { + case 0b0000: /* no access */ + break; + case 0b1111: /* all access */ + return true; + case 0b1000: + case 0b1001: + case 0b1010: + case 0b1011: + if (pspace =3D=3D (gpi & 3)) { + return true; + } + break; + default: + goto fault_walk; /* reserved */ + } + + fi->gpcf =3D GPCF_Fail; + goto fault_common; + fault_eabt: + fi->gpcf =3D GPCF_EABT; + goto fault_common; + fault_size: + fi->gpcf =3D GPCF_AddressSize; + goto fault_common; + fault_walk: + fi->gpcf =3D GPCF_Walk; + fault_common: + fi->level =3D level; + fi->paddr =3D paddress; + fi->paddr_space =3D pspace; + return false; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -242,10 +439,10 @@ static bool S1_ptw_translate(CPUARMState *env, S1Tran= slate *ptw, }; GetPhysAddrResult s2 =3D { }; =20 - if (get_phys_addr_with_struct(env, &s2ptw, addr, - MMU_DATA_LOAD, &s2, fi)) { + if (get_phys_addr_gpc(env, &s2ptw, addr, MMU_DATA_LOAD, &s2, fi)) { goto fail; } + ptw->out_phys =3D s2.f.phys_addr; pte_attrs =3D s2.cacheattrs.attrs; pte_secure =3D s2.f.attrs.secure; @@ -308,6 +505,9 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, =20 fail: assert(fi->type !=3D ARMFault_None); + if (fi->type =3D=3D ARMFault_GPCFOnOutput) { + fi->type =3D ARMFault_GPCFOnWalk; + } fi->s2addr =3D addr; fi->stage2 =3D true; fi->s1ptw =3D true; @@ -2735,7 +2935,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, ARMMMUFaultInfo *fi) { uint8_t memattr =3D 0x00; /* Device nGnRnE */ - uint8_t shareability =3D 0; /* non-sharable */ + uint8_t shareability =3D 0; /* non-shareable */ int r_el; =20 switch (mmu_idx) { @@ -2794,7 +2994,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, = target_ulong address, } else { memattr =3D 0x44; /* Normal, NC, No */ } - shareability =3D 2; /* outer sharable */ + shareability =3D 2; /* outer shareable */ } result->cacheattrs.is_s2_format =3D false; break; @@ -2822,7 +3022,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, ARMSecuritySpace ipa_space, s2walk_space; uint64_t hcr; =20 - ret =3D get_phys_addr_with_struct(env, ptw, address, access_type, resu= lt, fi); + ret =3D get_phys_addr_nogpc(env, ptw, address, access_type, result, fi= ); =20 /* If S1 fails, return early. */ if (ret) { @@ -2859,7 +3059,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, cacheattrs1 =3D result->cacheattrs; memset(result, 0, sizeof(*result)); =20 - ret =3D get_phys_addr_with_struct(env, ptw, ipa, access_type, result, = fi); + ret =3D get_phys_addr_nogpc(env, ptw, ipa, access_type, result, fi); fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ @@ -2919,7 +3119,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, return false; } =20 -static bool get_phys_addr_with_struct(CPUARMState *env, S1Translate *ptw, +static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, target_ulong address, MMUAccessType access_type, GetPhysAddrResult *result, @@ -3043,6 +3243,23 @@ static bool get_phys_addr_with_struct(CPUARMState *e= nv, S1Translate *ptw, } } =20 +static bool get_phys_addr_gpc(CPUARMState *env, S1Translate *ptw, + target_ulong address, + MMUAccessType access_type, + GetPhysAddrResult *result, + ARMMMUFaultInfo *fi) +{ + if (get_phys_addr_nogpc(env, ptw, address, access_type, result, fi)) { + return true; + } + if (!granule_protection_check(env, result->f.phys_addr, + result->f.attrs.space, fi)) { + fi->type =3D ARMFault_GPCFOnOutput; + return true; + } + return false; +} + bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_id= x, bool is_secure, GetPhysAddrResult *result, @@ -3053,8 +3270,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, targ= et_ulong address, .in_secure =3D is_secure, .in_space =3D arm_secure_to_space(is_secure), }; - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } =20 bool get_phys_addr(CPUARMState *env, target_ulong address, @@ -3124,8 +3340,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong add= ress, =20 ptw.in_space =3D ss; ptw.in_secure =3D arm_space_is_secure(ss); - return get_phys_addr_with_struct(env, &ptw, address, access_type, - result, fi); + return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } =20 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, @@ -3145,7 +3360,7 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs= , vaddr addr, ARMMMUFaultInfo fi =3D {}; bool ret; =20 - ret =3D get_phys_addr_with_struct(env, &ptw, addr, MMU_DATA_LOAD, &res= , &fi); + ret =3D get_phys_addr_gpc(env, &ptw, addr, MMU_DATA_LOAD, &res, &fi); *attrs =3D res.f.attrs; =20 if (ret) { --=20 2.34.1 From nobody Sat May 4 07:27:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677539097; cv=none; d=zohomail.com; s=zohoarc; b=G9xGQIN0pmwbmzMY4DZaP7bTZAxG67slyoJVoR7wcwr0EzflDVLI79EIPh7P272Xb9ATYK9gyaDg45Wnm35GlVR2baGVjj8a6nxVh+qNj35z83yVyZTccaFGhEZKeucz1Y/O02S+Wav8nzrIxd3t6iKN9P/Qa4B5oosiP3g3bCU= ARC-Message-Signature: i=1; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/Ut/aS2oezKic9UZ9DAK+e9x8VNxmPUkA0viJdZ3AGc=; b=xMzdGw/zkrh4HwAwLsEo9pLZwDZO8nnL1UmLwrwKM9kqlxF5An4WaMFAGbDXJ6ai5G 7eiiY7WmxDbnrXxetUgkXS6ae39Nio5LLPKAcegbDwJ3++/yiUmhee7BGSmugZOWKBLM d1pYYva5O2qNMF5jLW3PAJS4RP5vKG6g8HoTWeFkTdgWk32kY6D52uaXrYySGlsaFWfk WGZCcykyc62Ux6d2I92uY2mf2gzK5c6N2pS1hUg1SRMwi1tUG69orjnL2/3lrcQwoe28 idQUGj9TmD//23CWCVpDH2WSXxKAjcrGLYOc+yS86MWmq7b5nCfnxOxsFb72z5dpeBay buZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Ut/aS2oezKic9UZ9DAK+e9x8VNxmPUkA0viJdZ3AGc=; b=NB8USHqELQVIogmlvXzXku+WevLNp8uZLBrsRycjYadARJRkGGWqb13Euw6i2md6fI uKnvm2zZ+sVmJqBpFUXvtHnDQDhnLOJKBMlyzo6Y/eNDW3qjleOUEf8xsKbk17PjjePf Na3iGhEKQOUHlLbxojc9dBn9TPBXf427jkZLY4L+0sbrktLXsDOsuzddPDJBi0QRxALu Z0FyrPcE6OXLDOtEuox7zs0pkNOrQLJPyEpHdwn9dAGMG0NlJPYUFIZFxsAPh2+XNg3x RsZOQ8egBXCAOXG6C6BWaAubboIZdOE0JQ3D5Bj253sdCxhZfSXaztJjd7ztIbQ31cPm 8YIg== X-Gm-Message-State: AO0yUKUXI2tPSKTjfcwF9Hz96UqbMYO8rUdARZYVwPjt3ZAReNjCAU1w s+DvoJyWlQCvzgJ0MUybbUkUrYi4wariuHdDfEV70g== X-Google-Smtp-Source: AK7set+UhgulHlqYCtniBvsRGIt+vvu4virgCdkilaY+Yzsp4KEPJJ5nxeu5GBA80Gj0AlL668x06Q== X-Received: by 2002:a05:6a20:a111:b0:cd:5334:e240 with SMTP id q17-20020a056a20a11100b000cd5334e240mr1456897pzk.5.1677538917647; Mon, 27 Feb 2023 15:01:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH for-8.0 v4 20/21] NOTFORMERGE target/arm: Enable RME for -cpu max Date: Mon, 27 Feb 2023 13:01:21 -1000 Message-Id: <20230227230122.816702-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677539098233100005 Content-Type: text/plain; charset="utf-8" Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing various possible configurations. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da1..70c173ee3d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -672,6 +672,40 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp) cpu->isar.id_aa64mmfr0 =3D t; } =20 +static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value; + + if (!visit_type_uint32(v, name, &value, errp)) { + return; + } + + /* Encode the value for the GPCCR_EL3 field. */ + switch (value) { + case 30: + case 34: + case 36: + case 39: + cpu->reset_l0gptsz =3D value - 30; + break; + default: + error_setg(errp, "invalid value for l0gptsz"); + error_append_hint(errp, "valid values are 30, 34, 36, 39\n"); + break; + } +} + +static void cpu_max_get_l0gptsz(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value =3D cpu->reset_l0gptsz + 30; + + visit_type_uint32(v, name, &value, errp); +} + static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1200,6 +1234,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RME, 1); /* FEAT_RME */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; @@ -1301,6 +1336,8 @@ static void aarch64_max_initfn(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); + object_property_add(obj, "l0gptsz", "uint32", cpu_max_get_l0gptsz, + cpu_max_set_l0gptsz, NULL, NULL); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { --=20 2.34.1 From nobody Sat May 4 07:27:29 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677538943; cv=none; d=zohomail.com; s=zohoarc; b=AqWq2YQ8tx+0R6NNbzL2jv+wLrEjGhPrETYsZ9XsJj/KylnxNQq4M209F83k2ZZI+iyXWy14orIs6COarp+5NVHJiTgpKPlDGzmkOROe1XMjoIF2C7y+JiNkcfmbMkp8kXXqKXJtTO7jDMeAMKbjNHzCRY/usebX4/Ppk81Q/d4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677538943; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H9Qr7wA8wSIkfPgh/j+3hKBpjrPyoBLV3ksLdpb2kIs=; b=D1JWnwMbtbHaE9EuqUy40aRDlvcwJYi/9sh3AokJVVwKQizWhfBP2VHOkuc6NoJBnWbbU7pumTeqxMTJdoMAbK2MsiXzC4sRSKG+DZpbL59MDpPI9yDhNG2L7NTQdSnADYyTz2rbIBD1ctOZbB17SVTXZKhrkPnHWjsAIK4371Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677538943193960.9634258621946; Mon, 27 Feb 2023 15:02:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pWmVT-0000A8-PQ; Mon, 27 Feb 2023 18:02:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pWmVO-00089L-B1 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:02:02 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pWmVM-00017i-H6 for qemu-devel@nongnu.org; Mon, 27 Feb 2023 18:02:01 -0500 Received: by mail-pl1-x62a.google.com with SMTP id n6so7116545plf.5 for ; Mon, 27 Feb 2023 15:02:00 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a637902000000b0050301745a5dsm4406130pgc.50.2023.02.27.15.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Feb 2023 15:01:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H9Qr7wA8wSIkfPgh/j+3hKBpjrPyoBLV3ksLdpb2kIs=; b=SLophdP1kfF7Ksr1o+Kuvk7AIgQlliVoQ9EE8Nojk1Oi63y4v0Mt0YQ4/Sc0T2ogHO EXJZsmJB2AoyF/Qu+AZsxt3hfpPu5DeFD7c0gemd5nTj+SrwabnKk6srIthAXSUrk0cN ecBbxv+bbDVuOg9FNJj5vJ71jbPlM1VzfWHkD3F7BSSoQPoM7Zzw4ypjm/rPQo00DoYr rmkEu9zFx5tHi7fE7qThwvl29fC/RfRgadxCOer+xvJHq97FvRzz87SiaAqDbla94lGO LulBnhZDeJNk/JF0HGwPEWINysV6DfysZKIfisoT9YIVNUYWgg4W7iAJDSKQ7oefsQvR X5Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H9Qr7wA8wSIkfPgh/j+3hKBpjrPyoBLV3ksLdpb2kIs=; b=e3+vcEO8hOIzOMBp7A3itJ+cp4wA+K4T4hc7uycePzUNSIBqJ4x0UzDq22w+wk9SVV 8rb8OFllc7LjOCRLGW923PDy/ixZikGktyLgV4SRDw+nAJVpq01HSMn/i3Qf3M+fV4jU 1nDtfhPqtbXbAl24rfJGS+WYQ28Bsbvp9Kfla9UWKdQTy+HtfeDC8W2G8QvZ/04vFiI6 RcSBbHKNaWQfIe9U83oqSWWTwkGTERF++beV1Er3ZylP5kojXJr5JmHQXoLQnIHO3vvx XT4ZisUeftm0vTAdx6oInsZUtrSiJBi9jzao02JfkgTAqiNA+lWZyS/DvADc5Tl8FQK/ Y+fQ== X-Gm-Message-State: AO0yUKVZTfZy8Yb9EuN8eh/m+MCXvwFcWQ5WnYlIK4NtUt7Uscz74kO5 D4Agfi9T89O2djFsqqbUwSultZfiemzrAxWSKIU= X-Google-Smtp-Source: AK7set8Cfr97uz9w+NlHTrmCj6rNElBCU8Z9gbv9Sch9Eu5AKPer8QXFJGtBf4l2I0g3cn94tby8aQ== X-Received: by 2002:a05:6a20:a11f:b0:cc:32a8:323d with SMTP id q31-20020a056a20a11f00b000cc32a8323dmr7945737pzk.28.1677538918954; Mon, 27 Feb 2023 15:01:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH for-8.0 v4 21/21] NOTFORMERGE hw/arm/virt: Add some memory for Realm Management Monitor Date: Mon, 27 Feb 2023 13:01:22 -1000 Message-Id: <20230227230122.816702-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230227230122.816702-1-richard.henderson@linaro.org> References: <20230227230122.816702-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677538945311100007 Content-Type: text/plain; charset="utf-8" This is arbitrary, but used by the Huawei TF-A test code. Signed-off-by: Richard Henderson --- include/hw/arm/virt.h | 2 ++ hw/arm/virt.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index e1ddbea96b..5c0c8a67e4 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -86,6 +86,7 @@ enum { VIRT_ACPI_GED, VIRT_NVDIMM_ACPI, VIRT_PVTIME, + VIRT_RMM_MEM, VIRT_LOWMEMMAP_LAST, }; =20 @@ -159,6 +160,7 @@ struct VirtMachineState { bool virt; bool ras; bool mte; + bool rmm; bool dtb_randomness; OnOffAuto acpi; VirtGICType gic_version; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac626b3bef..067f16cd77 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -159,6 +159,7 @@ static const MemMapEntry base_memmap[] =3D { /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that siz= e */ [VIRT_PLATFORM_BUS] =3D { 0x0c000000, 0x02000000 }, [VIRT_SECURE_MEM] =3D { 0x0e000000, 0x01000000 }, + [VIRT_RMM_MEM] =3D { 0x0f000000, 0x00100000 }, [VIRT_PCIE_MMIO] =3D { 0x10000000, 0x2eff0000 }, [VIRT_PCIE_PIO] =3D { 0x3eff0000, 0x00010000 }, [VIRT_PCIE_ECAM] =3D { 0x3f000000, 0x01000000 }, @@ -1602,6 +1603,25 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } =20 +static void create_rmm_ram(VirtMachineState *vms, + MemoryRegion *sysmem, + MemoryRegion *tag_sysmem) +{ + MemoryRegion *rmm_ram =3D g_new(MemoryRegion, 1); + hwaddr base =3D vms->memmap[VIRT_RMM_MEM].base; + hwaddr size =3D vms->memmap[VIRT_RMM_MEM].size; + + memory_region_init_ram(rmm_ram, NULL, "virt.rmm-ram", size, + &error_fatal); + memory_region_add_subregion(sysmem, base, rmm_ram); + + /* do not fill in fdt to hide rmm from normal world guest */ + + if (tag_sysmem) { + create_tag_ram(tag_sysmem, base, size, "mach-virt.rmm-tag"); + } +} + static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { const VirtMachineState *board =3D container_of(binfo, VirtMachineState, @@ -2283,6 +2303,10 @@ static void machvirt_init(MachineState *machine) machine->ram_size, "mach-virt.tag"); } =20 + if (vms->rmm) { + create_rmm_ram(vms, sysmem, tag_sysmem); + } + vms->highmem_ecam &=3D (!firmware_loaded || aarch64); =20 create_rtc(vms); @@ -2562,6 +2586,20 @@ static void virt_set_mte(Object *obj, bool value, Er= ror **errp) vms->mte =3D value; } =20 +static bool virt_get_rmm(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + return vms->rmm; +} + +static void virt_set_rmm(Object *obj, bool value, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + vms->rmm =3D value; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); @@ -3115,6 +3153,11 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) "guest CPU which implements the = ARM " "Memory Tagging Extension"); =20 + object_class_property_add_bool(oc, "rmm", virt_get_rmm, virt_set_rmm); + object_class_property_set_description(oc, "rmm", + "Set on/off to enable/disable ra= m " + "for the Realm Management Monito= r"); + object_class_property_add_bool(oc, "its", virt_get_its, virt_set_its); object_class_property_set_description(oc, "its", --=20 2.34.1