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bh=dexhZ5Xm+mRmqvkIXWEp2lRhiLrw/yWW9emSw29h0JY=; b=KEbAsqwtIE9dAv+uosYYLDm2/vMOZVfdGSkobRMmfJ677kctGORtylipt823ZR0cwV57aC 3lOE0RTVgcQfW1TRtk3kkFG51QP8Cit0trzKUsdI0QRsdg4nUSWbSAUFAJV2nldwo6iqqQ ZFNfkAaECdgwHR7TewcCreuN4kJtPGM= X-MC-Unique: bDJ4BsPoO2udCDNGQisd2A-1 From: Cornelia Huck To: Peter Maydell , Thomas Huth , Laurent Vivier Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Eric Auger , "Dr. David Alan Gilbert" , Juan Quintela , Gavin Shan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Cornelia Huck Subject: [PATCH v6 1/2] arm/kvm: add support for MTE Date: Tue, 28 Feb 2023 16:02:15 +0100 Message-Id: <20230228150216.77912-2-cohuck@redhat.com> In-Reply-To: <20230228150216.77912-1-cohuck@redhat.com> References: <20230228150216.77912-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1677596651169100001 Content-Type: text/plain; charset="utf-8" Introduce a new cpu feature flag to control MTE support. To preserve backwards compatibility for tcg, MTE will continue to be enabled as long as tag memory has been provided. If MTE has been enabled, we need to disable migration, as we do not yet have a way to migrate the tags as well. Therefore, MTE will stay off with KVM unless requested explicitly. Signed-off-by: Cornelia Huck --- docs/system/arm/cpu-features.rst | 21 ++++++ hw/arm/virt.c | 2 +- target/arm/cpu.c | 18 ++--- target/arm/cpu.h | 1 + target/arm/cpu64.c | 110 +++++++++++++++++++++++++++++++ target/arm/internals.h | 1 + target/arm/kvm.c | 29 ++++++++ target/arm/kvm64.c | 5 ++ target/arm/kvm_arm.h | 19 ++++++ target/arm/monitor.c | 1 + 10 files changed, 194 insertions(+), 13 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-feature= s.rst index 00c444042ff5..f8b0f339d32d 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -443,3 +443,24 @@ As with ``sve-default-vector-length``, if the default = length is larger than the maximum vector length enabled, the actual vector length will be reduced. If this property is set to ``-1`` then the default vector length is set to the maximum possible length. + +MTE CPU Property +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The ``mte`` property controls the Memory Tagging Extension. For TCG, it re= quires +presence of tag memory (which can be turned on for the ``virt`` machine via +``mte=3Don``). For KVM, it requires the ``KVM_CAP_ARM_MTE`` capability; un= til +proper migration support is implemented, enabling MTE will install a migra= tion +blocker. + +If not specified explicitly via ``on`` or ``off``, MTE will be available +according to the following rules: + +* When TCG is used, MTE will be available if and only if tag memory is ava= ilable; + i.e. it preserves the behaviour prior to the introduction of the feature. + +* When KVM is used, MTE will default to off, so that migration will not + unintentionally be blocked. This might change in a future QEMU version. + +* Other accelerators currently don't support MTE. + diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac626b3bef74..8201bc0dc42d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2146,7 +2146,7 @@ static void machvirt_init(MachineState *machine) =20 if (vms->mte && (kvm_enabled() || hvf_enabled())) { error_report("mach-virt: %s does not support providing " - "MTE to the guest CPU", + "emulated MTE to the guest CPU (tag memory not suppor= ted)", current_accel_name()); exit(1); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 876ab8f3bf8a..19fbf7df09ec 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1532,6 +1532,11 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) error_propagate(errp, local_err); return; } + arm_cpu_mte_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } } #endif =20 @@ -1608,7 +1613,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } if (cpu->tag_memory) { error_setg(errp, - "Cannot enable %s when guest CPUs has MTE enabled", + "Cannot enable %s when guest CPUs has tag memory en= abled", current_accel_name()); return; } @@ -1987,17 +1992,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) ID_PFR1, VIRTUALIZATION, 0); } =20 -#ifndef CONFIG_USER_ONLY - if (cpu->tag_memory =3D=3D NULL && cpu_isar_feature(aa64_mte, cpu)) { - /* - * Disable the MTE feature bits if we do not have tag-memory - * provided by the machine. - */ - cpu->isar.id_aa64pfr1 =3D - FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); - } -#endif - if (tcg_enabled()) { /* * Don't report the Statistical Profiling Extension in the ID diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12b1082537c5..0960ae6d3e4e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1051,6 +1051,7 @@ struct ArchCPU { bool prop_pauth; bool prop_pauth_impdef; bool prop_lpa2; + OnOffAuto prop_mte; =20 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint32_t dcz_blocksize; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da15c..eb562ae7122c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -24,11 +24,16 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "internals.h" +#include "qapi/qapi-visit-common.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/arm/virt.h" +#endif =20 static void aarch64_a35_initfn(Object *obj) { @@ -1096,6 +1101,109 @@ static void aarch64_neoverse_n1_initfn(Object *obj) cpu->isar.reset_pmcr_el0 =3D 0x410c3000; } =20 +static void aarch64_cpu_get_mte(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + OnOffAuto mte =3D cpu->prop_mte; + + visit_type_OnOffAuto(v, name, &mte, errp); +} + +static void aarch64_cpu_set_mte(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + visit_type_OnOffAuto(v, name, &cpu->prop_mte, errp); +} + +static void aarch64_add_mte_properties(Object *obj) +{ + /* + * For tcg, "AUTO" means turn on mte if tag memory has been provided, = and + * turn it off (without error) if not. + * For kvm, "AUTO" currently means mte off, as migration is not suppor= ted + * yet. + * For all others, "AUTO" means mte off. + */ + object_property_add(obj, "mte", "OnOffAuto", aarch64_cpu_get_mte, + aarch64_cpu_set_mte, NULL, NULL); +} + +static inline bool arm_machine_has_tag_memory(void) +{ +#ifndef CONFIG_USER_ONLY + Object *obj =3D object_dynamic_cast(qdev_get_machine(), TYPE_VIRT_MACH= INE); + + /* so far, only the virt machine has support for tag memory */ + if (obj) { + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + return vms->mte; + } + return false; +#endif + return true; +} + +void arm_cpu_mte_finalize(ARMCPU *cpu, Error **errp) +{ + bool enable_mte; + + switch (cpu->prop_mte) { + case ON_OFF_AUTO_OFF: + enable_mte =3D false; + break; + case ON_OFF_AUTO_ON: + enable_mte =3D true; + if (tcg_enabled()) { + if (arm_machine_has_tag_memory()) { + break; + } + error_setg(errp, "mte=3Don requires tag memory"); + return; + } + if (kvm_enabled() && kvm_arm_mte_supported()) { + break; + } + error_setg(errp, "mte not supported by %s", current_accel_name()); + return; + default: /* AUTO */ + enable_mte =3D false; + if (tcg_enabled()) { + if (cpu_isar_feature(aa64_mte, cpu)) { + /* + * Tie mte enablement to presence of tag memory, in order = to + * preserve pre-existing behaviour. + */ + enable_mte =3D arm_machine_has_tag_memory(); + } + break; + } + if (kvm_enabled()) { + /* + * This cannot yet be + * enable_mte =3D kvm_arm_mte_supported(); + * as we don't support migration yet. + */ + enable_mte =3D false; + } + } + + if (!enable_mte) { + /* Disable MTE feature bits. */ + cpu->isar.id_aa64pfr1 =3D + FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0); + return; + } + + /* accelerator-specific enablement */ + if (kvm_enabled()) { + kvm_arm_enable_mte(errp); + } +} + static void aarch64_host_initfn(Object *obj) { #if defined(CONFIG_KVM) @@ -1104,6 +1212,7 @@ static void aarch64_host_initfn(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); aarch64_add_pauth_properties(obj); + aarch64_add_mte_properties(obj); } #elif defined(CONFIG_HVF) ARMCPU *cpu =3D ARM_CPU(obj); @@ -1301,6 +1410,7 @@ static void aarch64_max_initfn(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property); + aarch64_add_mte_properties(obj); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { diff --git a/target/arm/internals.h b/target/arm/internals.h index 759b70c646f8..3b9ef2cbb9ae 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1334,6 +1334,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp); +void arm_cpu_mte_finalize(ARMCPU *cpu, Error **errp); #endif =20 #ifdef CONFIG_USER_ONLY diff --git a/target/arm/kvm.c b/target/arm/kvm.c index f022c644d2ff..e6f2cb807bde 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -31,6 +31,7 @@ #include "hw/boards.h" #include "hw/irq.h" #include "qemu/log.h" +#include "migration/blocker.h" =20 const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO @@ -1062,3 +1063,31 @@ bool kvm_arch_cpu_check_are_resettable(void) void kvm_arch_accel_class_init(ObjectClass *oc) { } + +void kvm_arm_enable_mte(Error **errp) +{ + static bool tried_to_enable =3D false; + Error *mte_migration_blocker =3D NULL; + int ret; + + if (tried_to_enable) { + /* + * MTE on KVM is enabled on a per-VM basis (and retrying doesn't m= ake + * sense), and we only want a single migration blocker as well. + */ + return; + } + tried_to_enable =3D true; + + if ((ret =3D kvm_vm_enable_cap(kvm_state, KVM_CAP_ARM_MTE, 0))) { + error_setg_errno(errp, -ret, "Failed to enable KVM_CAP_ARM_MTE"); + return; + } + + /* TODO: add proper migration support with MTE enabled */ + error_setg(&mte_migration_blocker, + "Live migration disabled due to MTE enabled"); + if (migrate_add_blocker(mte_migration_blocker, errp)) { + error_free(mte_migration_blocker); + } +} diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 1197253d12f7..b777bd0a11d2 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -764,6 +764,11 @@ bool kvm_arm_steal_time_supported(void) return kvm_check_extension(kvm_state, KVM_CAP_STEAL_TIME); } =20 +bool kvm_arm_mte_supported(void) +{ + return kvm_check_extension(kvm_state, KVM_CAP_ARM_MTE); +} + QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); =20 uint32_t kvm_arm_sve_get_vls(CPUState *cs) diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 99017b635ce4..9f88b0722293 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -305,6 +305,13 @@ bool kvm_arm_pmu_supported(void); */ bool kvm_arm_sve_supported(void); =20 +/** + * kvm_arm_mte_supported: + * + * Returns: true if KVM can enable MTE, and false otherwise. + */ +bool kvm_arm_mte_supported(void); + /** * kvm_arm_get_max_vm_ipa_size: * @ms: Machine state handle @@ -369,6 +376,8 @@ void kvm_arm_pvtime_init(CPUState *cs, uint64_t ipa); =20 int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level); =20 +void kvm_arm_enable_mte(Error **errp); + #else =20 /* @@ -395,6 +404,11 @@ static inline bool kvm_arm_steal_time_supported(void) return false; } =20 +static inline bool kvm_arm_mte_supported(void) +{ + return false; +} + /* * These functions should never actually be called without KVM support. */ @@ -443,6 +457,11 @@ static inline uint32_t kvm_arm_sve_get_vls(CPUState *c= s) g_assert_not_reached(); } =20 +static inline void kvm_arm_enable_mte(Error **errp) +{ + g_assert_not_reached(); +} + #endif =20 static inline const char *gic_class_name(void) diff --git a/target/arm/monitor.c b/target/arm/monitor.c index ecdd5ee81742..c419c81612ed 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -96,6 +96,7 @@ static const char *cpu_model_advertised_features[] =3D { "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", "kvm-no-adjvtime", "kvm-steal-time", "pauth", "pauth-impdef", + "mte", NULL }; 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bh=rIsd2AR6rBy3LvtthCKr/JKSUa9znVYdiWORb5ehAkA=; b=bVSnEFUH3o2GtsVnGqPdJbCjUcDK8q4XkCJwcVY36VqngOqJfw+xm5y7HCgtfxNFRU05le 3DTuC9NAroy7NtYMlncRg/5KdmZVH4qKErKCYVSP+9RQ7ATdVnL/M0BhmSWlZxhcrsPrGq AwFEy9Q7DPPrmbLZrxHgiR/Pbb7xCrg= X-MC-Unique: gAnLldRtOpO0CBL4B9-sug-1 From: Cornelia Huck To: Peter Maydell , Thomas Huth , Laurent Vivier Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kvm@vger.kernel.org, Eric Auger , "Dr. David Alan Gilbert" , Juan Quintela , Gavin Shan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Cornelia Huck Subject: [PATCH v6 2/2] qtests/arm: add some mte tests Date: Tue, 28 Feb 2023 16:02:16 +0100 Message-Id: <20230228150216.77912-3-cohuck@redhat.com> In-Reply-To: <20230228150216.77912-1-cohuck@redhat.com> References: <20230228150216.77912-1-cohuck@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=cohuck@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1677596675482100003 With TCG, verify the interaction of the 'mte' cpu feature with virt machine tag memory. With KVM, only verify the existence of the cpu feature, as we cannot probe or enable the feature. Acked-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Cornelia Huck --- tests/qtest/arm-cpu-features.c | 80 ++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 1cb08138ad1c..9533646f0dc5 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -22,6 +22,7 @@ =20 #define MACHINE "-machine virt,gic-version=3Dmax -accel tcg " #define MACHINE_KVM "-machine virt,gic-version=3Dmax -accel kvm " +#define MACHINE_MTE "-machine virt,gic-version=3Dmax,mte=3Don -accel tcg " #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ " 'arguments': { 'type': 'full', " #define QUERY_TAIL "}}" @@ -156,6 +157,18 @@ static bool resp_get_feature(QDict *resp, const char *= feature) g_assert(qdict_get_bool(_props, feature) =3D=3D (expected_value)); = \ }) =20 +#define resp_assert_feature_str(resp, feature, expected_value) \ +({ \ + QDict *_props; \ + \ + g_assert(_resp); \ + g_assert(resp_has_props(_resp)); \ + _props =3D resp_get_props(_resp); \ + g_assert(qdict_get(_props, feature)); \ + g_assert_cmpstr(qdict_get_try_str(_props, feature), =3D=3D, = \ + expected_value); \ +}) + #define assert_feature(qts, cpu_type, feature, expected_value) \ ({ \ QDict *_resp; \ @@ -166,6 +179,16 @@ static bool resp_get_feature(QDict *resp, const char *= feature) qobject_unref(_resp); \ }) =20 +#define assert_feature_str(qts, cpu_type, feature, expected_value) \ +({ \ + QDict *_resp; \ + \ + _resp =3D do_query_no_props(qts, cpu_type); \ + g_assert(_resp); \ + resp_assert_feature_str(_resp, feature, expected_value); \ + qobject_unref(_resp); \ +}) + #define assert_set_feature(qts, cpu_type, feature, value) \ ({ \ const char *_fmt =3D (value) ? "{ %s: true }" : "{ %s: false }"; \ @@ -177,6 +200,17 @@ static bool resp_get_feature(QDict *resp, const char *= feature) qobject_unref(_resp); \ }) =20 +#define assert_set_feature_str(qts, cpu_type, feature, value, _fmt) \ +({ \ + const char *__fmt =3D _fmt; \ + QDict *_resp; \ + \ + _resp =3D do_query(qts, cpu_type, __fmt, feature); \ + g_assert(_resp); \ + resp_assert_feature_str(_resp, feature, value); \ + qobject_unref(_resp); \ +}) + #define assert_has_feature_enabled(qts, cpu_type, feature) \ assert_feature(qts, cpu_type, feature, true) =20 @@ -413,6 +447,24 @@ static void sve_tests_sve_off_kvm(const void *data) qtest_quit(qts); } =20 +static void mte_tests_tag_memory_on(const void *data) +{ + QTestState *qts; + + qts =3D qtest_init(MACHINE_MTE "-cpu max"); + + /* + * With tag memory, "mte" should default to on, and explicitly specify= ing + * either on or off should be fine. + */ + assert_has_feature(qts, "max", "mte"); + + assert_set_feature_str(qts, "max", "mte", "off", "{ 'mte': 'off' }"); + assert_set_feature_str(qts, "max", "mte", "on", "{ 'mte': 'on' }"); + + qtest_quit(qts); +} + static void pauth_tests_default(QTestState *qts, const char *cpu_type) { assert_has_feature_enabled(qts, cpu_type, "pauth"); @@ -425,6 +477,19 @@ static void pauth_tests_default(QTestState *qts, const= char *cpu_type) "{ 'pauth': false, 'pauth-impdef': true }"); } =20 +static void mte_tests_default(QTestState *qts, const char *cpu_type) +{ + assert_has_feature(qts, cpu_type, "mte"); + + /* + * Without tag memory, mte will be off under tcg. + * Explicitly enabling it yields an error. + */ + assert_set_feature_str(qts, "max", "mte", "off", "{ 'mte': 'off' }"); + assert_error(qts, cpu_type, "mte=3Don requires tag memory", + "{ 'mte': 'on' }"); +} + static void test_query_cpu_model_expansion(const void *data) { QTestState *qts; @@ -474,6 +539,7 @@ static void test_query_cpu_model_expansion(const void *= data) =20 sve_tests_default(qts, "max"); pauth_tests_default(qts, "max"); + mte_tests_default(qts, "max"); =20 /* Test that features that depend on KVM generate errors without. = */ assert_error(qts, "max", @@ -517,6 +583,18 @@ static void test_query_cpu_model_expansion_kvm(const v= oid *data) assert_set_feature(qts, "host", "pmu", false); assert_set_feature(qts, "host", "pmu", true); =20 + /* + * Unfortunately, there's no easy way to test whether this instance + * of KVM supports MTE: the cpu model expansion will return "auto"= for + * the mte prop, regardless whether the host/KVM supports MTE or n= ot. + * Even if we got around that hurdle somehow, we would need to set= up + * proper memory mappings in order to enable MTE, which is not fea= sible + * with qtest. + * So we can only assert that the feature is present, but not whet= her it + * can be toggled. + */ + assert_has_feature(qts, "host", "mte"); + /* * Some features would be enabled by default, but they're disabled * because this instance of KVM doesn't support them. Test that the @@ -631,6 +709,8 @@ int main(int argc, char **argv) =20 qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", NULL, sve_tests_sve_off_kvm); + qtest_add_data_func("/arm/max/query-cpu-model-expansion/tag-memory= ", + NULL, mte_tests_tag_memory_on); } =20 if (qtest_has_accel("tcg")) { --=20 2.39.2