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Tsirkin" , Paolo Bonzini , Richard Henderson , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH v2 10/13] hw/pci-host/q35: Rename local variable to more idiomatic "phb" Date: Sat, 4 Mar 2023 16:26:45 +0100 Message-Id: <20230304152648.103749-11-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304152648.103749-1-shentey@gmail.com> References: <20230304152648.103749-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677943689753100001 Content-Type: text/plain; charset="utf-8" Variables of type PCIHostState* are typically named "phb" in QEMU. Follow this convention here as well for consistency. Signed-off-by: Bernhard Beschow --- hw/pci-host/q35.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index afd192cc2a..cf9fb35064 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -46,21 +46,21 @@ =20 static void q35_host_realize(DeviceState *dev, Error **errp) { - PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); Q35PCIHost *s =3D Q35_HOST_DEVICE(dev); + PCIHostState *phb =3D PCI_HOST_BRIDGE(dev); SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 memory_region_add_subregion(s->mch.address_space_io, - MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_me= m); + MCH_HOST_BRIDGE_CONFIG_ADDR, &phb->conf_me= m); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); =20 memory_region_add_subregion(s->mch.address_space_io, - MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_me= m); + MCH_HOST_BRIDGE_CONFIG_DATA, &phb->data_me= m); sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); =20 /* register q35 0xcf8 port as coalesced pio */ - memory_region_set_flush_coalesced(&pci->data_mem); - memory_region_add_coalescing(&pci->conf_mem, 0, 4); + memory_region_set_flush_coalesced(&phb->data_mem); + memory_region_add_coalescing(&phb->conf_mem, 0, 4); =20 /* * pci hole goes from end-of-low-ram to io-apic. @@ -69,12 +69,12 @@ static void q35_host_realize(DeviceState *dev, Error **= errp) range_set_bounds(&s->pci_hole, s->mch.below_4g_mem_size, IO_APIC_DEFAULT_ADDRESS - 1); =20 - pci->bus =3D pci_root_bus_new(DEVICE(s), "pcie.0", + phb->bus =3D pci_root_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, 0, TYPE_PCIE_BUS); =20 - qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); + qdev_realize(DEVICE(&s->mch), BUS(phb->bus), &error_fatal); } =20 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, --=20 2.39.2