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Tsirkin" , Paolo Bonzini , Richard Henderson , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH v2 08/13] hw/pci-host/q35: Initialize PCI hole boundaries just once Date: Sat, 4 Mar 2023 16:26:43 +0100 Message-Id: <20230304152648.103749-9-shentey@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230304152648.103749-1-shentey@gmail.com> References: <20230304152648.103749-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=shentey@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1677943671943100006 Content-Type: text/plain; charset="utf-8" The boundaries of the PCI hole depend on a property only which doesn't change at runtime. There is no need to reevaluate the boundaries whenever the PCI configuration space changes. While at it, move the pci_hole attribute into the host device since it is only used there. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/q35.h | 2 +- hw/pci-host/q35.c | 21 +++++++++------------ 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h index 93e41ffbee..a04d5f1a17 100644 --- a/include/hw/pci-host/q35.h +++ b/include/hw/pci-host/q35.h @@ -51,7 +51,6 @@ struct MCHPCIState { MemoryRegion tseg_blackhole, tseg_window; MemoryRegion smbase_blackhole, smbase_window; bool has_smram_at_smbase; - Range pci_hole; uint64_t below_4g_mem_size; uint64_t above_4g_mem_size; uint16_t ext_tseg_mbytes; @@ -62,6 +61,7 @@ struct Q35PCIHost { PCIExpressHost parent_obj; /*< public >*/ =20 + Range pci_hole; uint64_t pci_hole64_size; uint32_t short_root_bus; bool pci_hole64_fix; diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index f20e092516..23df52a256 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -62,6 +62,13 @@ static void q35_host_realize(DeviceState *dev, Error **e= rrp) memory_region_set_flush_coalesced(&pci->data_mem); memory_region_add_coalescing(&pci->conf_mem, 0, 4); =20 + /* + * pci hole goes from end-of-low-ram to io-apic. + * mmconfig will be excluded by the dsdt builder. + */ + range_set_bounds(&s->pci_hole, s->mch.below_4g_mem_size, + IO_APIC_DEFAULT_ADDRESS - 1); + pci->bus =3D pci_root_bus_new(DEVICE(s), "pcie.0", s->mch.pci_address_space, s->mch.address_space_io, @@ -90,8 +97,7 @@ static void q35_host_get_pci_hole_start(Object *obj, Visi= tor *v, uint64_t val64; uint32_t value; =20 - val64 =3D range_is_empty(&s->mch.pci_hole) - ? 0 : range_lob(&s->mch.pci_hole); + val64 =3D range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); value =3D val64; assert(value =3D=3D val64); visit_type_uint32(v, name, &value, errp); @@ -105,8 +111,7 @@ static void q35_host_get_pci_hole_end(Object *obj, Visi= tor *v, uint64_t val64; uint32_t value; =20 - val64 =3D range_is_empty(&s->mch.pci_hole) - ? 0 : range_upb(&s->mch.pci_hole) + 1; + val64 =3D range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) += 1; value =3D val64; assert(value =3D=3D val64); visit_type_uint32(v, name, &value, errp); @@ -506,14 +511,6 @@ static void mch_update(MCHPCIState *mch) mch_update_smram(mch); mch_update_ext_tseg_mbytes(mch); mch_update_smbase_smram(mch); - - /* - * pci hole goes from end-of-low-ram to io-apic. - * mmconfig will be excluded by the dsdt builder. - */ - range_set_bounds(&mch->pci_hole, - mch->below_4g_mem_size, - IO_APIC_DEFAULT_ADDRESS - 1); } =20 static int mch_post_load(void *opaque, int version_id) --=20 2.39.2