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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Paolo Bonzini Cc: Eduardo Habkost --- target/i386/tcg/translate.c | 41 -------------------------------- target/i386/tcg/decode-new.c.inc | 15 ------------ target/i386/tcg/emit.c.inc | 6 ----- 3 files changed, 62 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index defbc43deb..2f3842663d 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -899,10 +899,6 @@ static void gen_compute_eflags(DisasContext *s) gen_update_cc_op(s); gen_helper_cc_compute_all(cpu_cc_src, dst, src1, src2, cpu_cc_op); set_cc_op(s, CC_OP_EFLAGS); - - if (dead) { - tcg_temp_free(zero); - } } =20 typedef struct CCPrepare { @@ -1650,7 +1646,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot= , TCGv result, } else { tcg_gen_mov_tl(cpu_cc_src, shm1); } - tcg_temp_free(z_tl); =20 /* Get the two potential CC_OP values into temporaries. */ tcg_gen_movi_i32(s->tmp2_i32, (is_right ? CC_OP_SARB : CC_OP_SHLB) + o= t); @@ -1666,8 +1661,6 @@ static void gen_shift_flags(DisasContext *s, MemOp ot= , TCGv result, s32 =3D tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(s32, count); tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, old= op); - tcg_temp_free_i32(z32); - tcg_temp_free_i32(s32); =20 /* The CC_OP value is no longer predictable. */ set_cc_op(s, CC_OP_DYNAMIC); @@ -1827,8 +1820,6 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, = int op1, int is_right) tcg_gen_movi_i32(s->tmp3_i32, CC_OP_EFLAGS); tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, t1, t0, s->tmp2_i32, s->tmp3_i32); - tcg_temp_free_i32(t0); - tcg_temp_free_i32(t1); =20 /* The CC_OP value is no longer predictable. */ set_cc_op(s, CC_OP_DYNAMIC); @@ -2049,7 +2040,6 @@ static void gen_shiftd_rm_T1(DisasContext *s, MemOp o= t, int op1, gen_op_st_rm_T0_A0(s, ot, op1); =20 gen_shift_flags(s, ot, s->T0, s->tmp0, count, is_right); - tcg_temp_free(count); } =20 static void gen_shift(DisasContext *s1, int op, MemOp ot, int d, int s) @@ -2513,13 +2503,6 @@ static void gen_cmovcc1(CPUX86State *env, DisasConte= xt *s, MemOp ot, int b, tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2, s->T0, cpu_regs[reg]); gen_op_mov_reg_v(s, ot, reg, s->T0); - - if (cc.mask !=3D -1) { - tcg_temp_free(cc.reg); - } - if (!cc.use_reg2) { - tcg_temp_free(cc.reg2); - } } =20 static inline void gen_op_movl_T0_seg(DisasContext *s, X86Seg seg_reg) @@ -2748,7 +2731,6 @@ static void gen_set_hflag(DisasContext *s, uint32_t m= ask) tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); tcg_gen_ori_i32(t, t, mask); tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); - tcg_temp_free_i32(t); s->flags |=3D mask; } } @@ -2760,7 +2742,6 @@ static void gen_reset_hflag(DisasContext *s, uint32_t= mask) tcg_gen_ld_i32(t, cpu_env, offsetof(CPUX86State, hflags)); tcg_gen_andi_i32(t, t, ~mask); tcg_gen_st_i32(t, cpu_env, offsetof(CPUX86State, hflags)); - tcg_temp_free_i32(t); s->flags &=3D ~mask; } } @@ -2772,7 +2753,6 @@ static void gen_set_eflags(DisasContext *s, target_ul= ong mask) tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); tcg_gen_ori_tl(t, t, mask); tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); - tcg_temp_free(t); } =20 static void gen_reset_eflags(DisasContext *s, target_ulong mask) @@ -2782,7 +2762,6 @@ static void gen_reset_eflags(DisasContext *s, target_= ulong mask) tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, eflags)); tcg_gen_andi_tl(t, t, ~mask); tcg_gen_st_tl(t, cpu_env, offsetof(CPUX86State, eflags)); - tcg_temp_free(t); } =20 /* Clear BND registers during legacy branches. */ @@ -3015,13 +2994,11 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_TEUQ); } - tcg_temp_free_i64(val); =20 /* Set tmp0 to match the required value of Z. */ tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); Z =3D tcg_temp_new(); tcg_gen_trunc_i64_tl(Z, cmp); - tcg_temp_free_i64(cmp); =20 /* * Extract the result values for the register pair. @@ -3042,12 +3019,10 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86St= ate *env, int modrm) tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, s->T1, cpu_regs[R_EDX]); } - tcg_temp_free_i64(old); =20 /* Update Z. */ gen_compute_eflags(s); tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); - tcg_temp_free(Z); } =20 #ifdef TARGET_X86_64 @@ -3072,8 +3047,6 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86Sta= te *env, int modrm) } =20 tcg_gen_extr_i128_i64(s->T0, s->T1, val); - tcg_temp_free_i128(cmp); - tcg_temp_free_i128(val); =20 /* Determine success after the fact. */ t0 =3D tcg_temp_new_i64(); @@ -3081,13 +3054,11 @@ static void gen_cmpxchg16b(DisasContext *s, CPUX86S= tate *env, int modrm) tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); tcg_gen_or_i64(t0, t0, t1); - tcg_temp_free_i64(t1); =20 /* Update Z. */ gen_compute_eflags(s); tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); - tcg_temp_free_i64(t0); =20 /* * Extract the result values for the register pair. We may do this @@ -3437,10 +3408,8 @@ static bool disas_insn(DisasContext *s, CPUState *cp= u) tcg_gen_neg_tl(t1, t0); tcg_gen_atomic_cmpxchg_tl(t0, a0, t0, t1, s->mem_index, ot | MO_LE); - tcg_temp_free(t1); tcg_gen_brcond_tl(TCG_COND_NE, t0, t2, label1); =20 - tcg_temp_free(t2); tcg_gen_neg_tl(s->T0, t0); } else { tcg_gen_neg_tl(s->T0, s->T0); @@ -3927,9 +3896,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_mov_tl(s->cc_srcT, cmpv); tcg_gen_sub_tl(cpu_cc_dst, cmpv, oldv); set_cc_op(s, CC_OP_SUBB + ot); - tcg_temp_free(oldv); - tcg_temp_free(newv); - tcg_temp_free(cmpv); } break; case 0x1c7: /* cmpxchg8b */ @@ -4380,7 +4346,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (shift) { TCGv imm =3D tcg_const_tl(x86_ldub_code(env, s)); gen_shiftd_rm_T1(s, ot, opreg, op, imm); - tcg_temp_free(imm); } else { gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); } @@ -4614,7 +4579,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_st_tl(last_addr, cpu_env, offsetof(CPUX86State, fpdp)); } - tcg_temp_free(last_addr); } else { /* register float ops */ opreg =3D rm; @@ -6279,9 +6243,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_compute_eflags(s); tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z); tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } break; case 0x102: /* lar */ @@ -6308,7 +6269,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_mov_reg_v(s, ot, reg, t0); gen_set_label(label1); set_cc_op(s, CC_OP_EFLAGS); - tcg_temp_free(t0); } break; case 0x118: @@ -6353,7 +6313,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) TCGv_i64 notu =3D tcg_temp_new_i64(); tcg_gen_not_i64(notu, cpu_bndu[reg]); gen_bndck(env, s, modrm, TCG_COND_GTU, notu); - tcg_temp_free_i64(notu); } else if (prefixes & PREFIX_DATA) { /* bndmov -- from reg/mem */ if (reg >=3D 4 || s->aflag =3D=3D MO_16) { diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.= c.inc index d5fd8d965c..4fdd87750b 100644 --- a/target/i386/tcg/decode-new.c.inc +++ b/target/i386/tcg/decode-new.c.inc @@ -1567,20 +1567,6 @@ illegal: return false; } =20 -static void decode_temp_free(X86DecodedOp *op) -{ - if (op->v_ptr) { - tcg_temp_free_ptr(op->v_ptr); - } -} - -static void decode_temps_free(X86DecodedInsn *decode) -{ - decode_temp_free(&decode->op[0]); - decode_temp_free(&decode->op[1]); - decode_temp_free(&decode->op[2]); -} - /* * Convert one instruction. s->base.is_jmp is set if the translation must * be stopped. @@ -1835,7 +1821,6 @@ static void disas_insn_new(DisasContext *s, CPUState = *cpu, int b) decode.e.gen(s, env, &decode); gen_writeback(s, &decode, 0, s->T0); } - decode_temps_free(&decode); return; illegal_op: gen_illegal_opcode(s); diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 0d01e13002..95fb4f52fa 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -629,7 +629,6 @@ static inline void gen_ternary_sse(DisasContext *s, CPU= X86State *env, X86Decoded /* The format of the fourth input is Lx */ tcg_gen_addi_ptr(ptr3, cpu_env, ZMM_OFFSET(op3)); fn(cpu_env, OP_PTR0, OP_PTR1, OP_PTR2, ptr3); - tcg_temp_free_ptr(ptr3); } #define TERNARY_SSE(uname, uvname, lname) = \ static void gen_##uvname(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) \ @@ -1001,7 +1000,6 @@ static inline void gen_vsib_avx(DisasContext *s, CPUX= 86State *env, X86DecodedIns int ymmh_ofs =3D vector_elem_offset(&decode->op[1], MO_128, 1); tcg_gen_gvec_dup_imm(MO_64, ymmh_ofs, 16, 16, 0); } - tcg_temp_free_ptr(index); } #define VSIB_AVX(uname, lname) = \ static void gen_##uname(DisasContext *s, CPUX86State *env, X86DecodedInsn = *decode) \ @@ -1627,7 +1625,6 @@ static void gen_PMOVMSKB(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); } } - tcg_temp_free(t); } =20 static void gen_PSHUFW(DisasContext *s, CPUX86State *env, X86DecodedInsn *= decode) @@ -1762,7 +1759,6 @@ static void gen_PSRLDQ_i(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco } else { gen_helper_psrldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); } - tcg_temp_free_ptr(imm_vec); } =20 static void gen_PSLLDQ_i(DisasContext *s, CPUX86State *env, X86DecodedInsn= *decode) @@ -1775,7 +1771,6 @@ static void gen_PSLLDQ_i(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco } else { gen_helper_pslldq_xmm(cpu_env, OP_PTR0, OP_PTR1, imm_vec); } - tcg_temp_free_ptr(imm_vec); } =20 static void gen_RORX(DisasContext *s, CPUX86State *env, X86DecodedInsn *de= code) @@ -2293,7 +2288,6 @@ static void gen_VZEROALL(DisasContext *s, CPUX86State= *env, X86DecodedInsn *deco tcg_gen_addi_ptr(ptr, cpu_env, offsetof(CPUX86State, xmm_t0)); gen_helper_memset(ptr, ptr, tcg_constant_i32(0), tcg_constant_ptr(CPU_NB_REGS * sizeof(ZMMReg))); - tcg_temp_free_ptr(ptr); } =20 static void gen_VZEROUPPER(DisasContext *s, CPUX86State *env, X86DecodedIn= sn *decode) --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953944; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NMAbXRT3XuWjgVWXzFHUDpgAHu3JgPZi8PcGKw6ji90=; b=vlDpSUncoFqQiSouoT/JIjKV3PzWX4zW6935bPJei3yjMKv7+6qimUY/0J7upXLfZX Et7C9+KRLZdyWsU2anfqSaraN3Odce15ssIb5mfoUpMTTCVL0gUK1ZSmxNM/5WYkRLN3 +Xv1uPvCoJWnmhkLn3kf3iwh0w2IAYmBiLm7/aoxZUVO39/5/9HWDyghOM/ajeoWzI8K tVSM1IgRuP+AKU8y9QmEB/3Su9Du/IdkWyD5SWcDYMqF7f9izWYLwuXcdi+CcxkDOV9g K2Mka5spWYSNhUY3KzJ0LltQZZG0EGq/QwNc+s6PBoq8aP6jmzcnGWtiRp6yd/hKugrT jGNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953944; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NMAbXRT3XuWjgVWXzFHUDpgAHu3JgPZi8PcGKw6ji90=; b=pi6LUtg7IDULvylQWx/SG1iwOsH+faKfve8o7HISUCh1f9IdrVhmutbbWKSJSbtAPk qvei9Y8Ev9JiV4B2O+NIX4rp2JRA1yubLIXjaTKlxHvrn5rybvet7YgD09owBgMTt9tG vr19QAJ2FSVAn8kV5oeApqgDj9zU2Q9SvXVvGVc0FwFjj+7LDZooBDR4OV7BpXLKPZw/ ZAsVlrbyuEH2oDcq5yh4wwC3Z8O/G39vHTuRQXgKUTmVixp7dRLe57+taznMOuVMhEfI 1lh3uaMTw2h3Y9npVij0UCplUjGUqRhhLXHPbh+FB9Of4M2KTKZF7eEHSLGeNbFlyfKA GFcQ== X-Gm-Message-State: AO0yUKUR+LcZgMbXQyP+d2AMI5u03fB2J16EiXHbpX9Qui6PBX81+Fon Nhz2bU/zGtxNMMUwrLzlNdnAxZjQKwpt3B8ijLtdBVCy X-Google-Smtp-Source: AK7set8IU0tpFXPSVioZVPr+ofzsjDwUM4JiHzhwp/h5fuIus4jOfanN+MkXs9UNoQMgEgOh6mjH4Q== X-Received: by 2002:a62:1c07:0:b0:5a8:a467:f975 with SMTP id c7-20020a621c07000000b005a8a467f975mr5696714pfc.17.1677953944019; Sat, 04 Mar 2023 10:19:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 02/20] target/mips: Drop tcg_temp_free from micromips_translate.c.inc Date: Sat, 4 Mar 2023 10:18:42 -0800 Message-Id: <20230304181900.1097116-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954104680100003 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/micromips_translate.c.inc | 8 -------- 1 file changed, 8 deletions(-) diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/mi= cromips_translate.c.inc index 632895cc9e..23f80d4315 100644 --- a/target/mips/tcg/micromips_translate.c.inc +++ b/target/mips/tcg/micromips_translate.c.inc @@ -724,9 +724,6 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32= _t opc, int reglist, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free_i32(t2); } =20 =20 @@ -1018,8 +1015,6 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t= opc, int rd, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, in= t rs) @@ -1067,7 +1062,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) =20 gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rs, (ctx->opcode >> 11) & 0x7); - tcg_temp_free(t0); } break; #endif @@ -1276,7 +1270,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) * mode. */ ctx->base.is_jmp =3D DISAS_STOP; - tcg_temp_free(t0); } break; case EI: @@ -1293,7 +1286,6 @@ static void gen_pool32axf(CPUMIPSState *env, DisasCon= text *ctx, int rt, int rs) */ gen_save_pc(ctx->base.pc_next + 4); ctx->base.is_jmp =3D DISAS_EXIT; - tcg_temp_free(t0); } break; default: --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954069; cv=none; d=zohomail.com; s=zohoarc; b=NZyXelaY3JbFk3DN9CdmJ8KBhVf7k3fXz9Wn96ithtHqUKHSGc8eR9oIa1EqMPBOxur14xDcOXB0APOpfVFZOic9KPWubJgbXbIKBAm20eyoKnTAERbEWavKEA7ca0uRjn/51N72/mK9JjCAerJJfZyCfwy6egl41XAcJ1nbfG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954069; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CC08sc/7f1akAHHWB9NB+xcDcBZ96GXhinyNlTxvBEg=; b=HLUIwhvVHVf1OQByHBb3z0pNBY2ue9jUW9TRZVGh1ESTReq2Qlb4nUqL0ZLfjBnfuJAJXftaNVBhA3N2Ptrla4z49vhLv6rrAX+W+NOEtzJRcEblWOcr154AvPrfPVPL7hRiMyk6fHxoG0K6hEpAK9ZT+gkRIvyJQIQlH1RMo10= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677954069271878.6652215877773; Sat, 4 Mar 2023 10:21:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTS-0006Pw-Cy; Sat, 04 Mar 2023 13:19:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTP-0006Np-Rn for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:11 -0500 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTL-0003M7-Ox for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:10 -0500 Received: by mail-pl1-x62b.google.com with SMTP id n6so6083508plf.5 for ; Sat, 04 Mar 2023 10:19:05 -0800 (PST) Received: from stoup.. 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Signed-off-by: Richard Henderson Reviewed-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/mips16e_translate.c.inc | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips= 16e_translate.c.inc index 918b15d55c..602f5f0c02 100644 --- a/target/mips/tcg/mips16e_translate.c.inc +++ b/target/mips/tcg/mips16e_translate.c.inc @@ -280,9 +280,6 @@ static void gen_mips16_save(DisasContext *ctx, =20 tcg_gen_movi_tl(t2, -framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 static void gen_mips16_restore(DisasContext *ctx, @@ -386,9 +383,6 @@ static void gen_mips16_restore(DisasContext *ctx, =20 tcg_gen_movi_tl(t2, framesize); gen_op_addr_add(ctx, cpu_gpr[29], cpu_gpr[29], t2); - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 #if defined(TARGET_MIPS64) --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954129; cv=none; d=zohomail.com; s=zohoarc; b=MspA1TchSYkEN5lNwMRUkS3TeZGXhW2hWZ/N6lX1M2RJjQ7ysegVM/JWFyjXfVAxxv9sDzL0IIYAZbm+K0jeZkHNkr670aDM6KIyBlCcIvhojKcb1FRwE3Pi1xPtaJD5gxGo6pXOHJ/8H6QnKqkGA8FshEkFWA4vi4ImSswcilI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954129; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YagYARUj+tWscHqmLJkuonA2cFZqj495U+6irFp0EFc=; b=Q7oY0bsw8h4+Tx7MkiZAt5oEac+FnNdXInbJK99nr3MUsMcFDziALYWr0vU64APxbO2neBlvbepmP7gmG+mNMgrBkiwn0QfPYLrE3G/NLpNhqGyjidWtxUAR3y92t51kLevLVwJvp22SsGfHnKXmjO5tFoJ32Dgnc2noobMY92s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167795412976167.04453943989643; Sat, 4 Mar 2023 10:22:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTR-0006PJ-Of; Sat, 04 Mar 2023 13:19:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTN-0006NV-TF for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:11 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTL-0003MF-Of for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:09 -0500 Received: by mail-pg1-x529.google.com with SMTP id y19so3298338pgk.5 for ; Sat, 04 Mar 2023 10:19:06 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YagYARUj+tWscHqmLJkuonA2cFZqj495U+6irFp0EFc=; b=l6IkY4biV0ZozsbhuQkUZok6zvhr7QEsn6CnXKSHibBn4E78R6f8WqqfG8Y0zPai/D /LuVUXTRpEVN1mP4F9dzbtbrdo/S7mYZmYXm4cZbWNoGCTLJ2LKxnYeOuuozgJJqPH/1 uTov/4noSJ3jH6Odqi4/DqcXXQASvr4BLcBsxObp9DfoP/15CSgJBG6zUL++TNPd5eNn yNVulffTj++CCsiK2VngI1JqoZMJFVHgXmyLYXjyQ753vSo7gaW0KgLmXrO0vgn2myZ6 3qw+HNRwQxg8EHxuplKp5x0lDM4EVTOlDHsREdLriax/XHHrr6SaDpCgkjy9NL4Tc3P8 9PMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953945; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YagYARUj+tWscHqmLJkuonA2cFZqj495U+6irFp0EFc=; b=WPSA7Cv6TeA/vV0Vx1sakuk1/aPdQ34dER38szBTE5N3c93vMrejLDpW2P6fKppEks T1yaxyQXa4c6TknbLTDhBxfIiwS1snNUyjbyZGoROkrIqomHYksjpxRlUpb90o7t0Xfg AxbUFiRa7tYP3HOLW2RyIpFSMQiJTnm+g3Zymql403WtQIc3TzW3CZsirf5deD6dIgyE dtNjCqMCtBqzawHBAZF6rumQxVc9qeFUASGGHQZ2cImI3jJ0tS04l6WnctRdO8B6QhU8 PGx0lmti7USolhZNfeM2PCzKshMiJ8+8owuWN2NIjoVC6uJi9DJpG1vbG0+tuQlPAV2f z3GQ== X-Gm-Message-State: AO0yUKWCXM5LmJU6IGWfuAgNTbYeRTxKSJO+3XwQL5i20SD+b4mUxDKf nwfneeTmp/VYCERisHWeU5zwfT8yRz3L2FsWg03rhg== X-Google-Smtp-Source: AK7set9iCy9z932p9L+fEa3O6k7YzYXhXQhXLmSult2kNoJdn3FxTx3HydgUE/EeM6PZZpKzE3a9dA== X-Received: by 2002:a62:5e43:0:b0:593:da8:6f34 with SMTP id s64-20020a625e43000000b005930da86f34mr4506638pfb.5.1677953945540; Sat, 04 Mar 2023 10:19:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 04/20] target/mips: Drop tcg_temp_free from msa_translate.c Date: Sat, 4 Mar 2023 10:18:44 -0800 Message-Id: <20230304181900.1097116-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954130804100007 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/msa_translate.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index 1bcdbb1121..220cd3b048 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -217,8 +217,6 @@ static void gen_check_zero_element(TCGv tresult, uint8_= t df, uint8_t wt, /* if some bit is non-zero then some element is zero */ tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(tresult, t0); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond) @@ -237,7 +235,6 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, in= t sa, TCGCond cond) tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]); tcg_gen_setcondi_i64(cond, t0, t0, 0); tcg_gen_trunc_i64_tl(bcond, t0); - tcg_temp_free_i64(t0); =20 ctx->btarget =3D ctx->base.pc_next + (sa << 2) + 4; =20 @@ -545,8 +542,6 @@ static bool trans_CTCMSA(DisasContext *ctx, arg_msa_elm= *a) gen_load_gpr(telm, a->ws); gen_helper_msa_ctcmsa(cpu_env, telm, tcg_constant_i32(a->wd)); =20 - tcg_temp_free(telm); - return true; } =20 @@ -563,8 +558,6 @@ static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm= *a) gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); gen_store_gpr(telm, a->wd); =20 - tcg_temp_free(telm); - return true; } =20 @@ -782,8 +775,6 @@ static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i= *a, gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); gen_msa_ldst(cpu_env, tcg_constant_i32(a->wd), taddr); =20 - tcg_temp_free(taddr); - return true; } =20 --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954131; cv=none; d=zohomail.com; s=zohoarc; b=gV59M+uY+ez8RGi+DtoZKrM7WeiXyOxNrbib2VxuaaQnDBST3DECU2W0fAM1uirDq/72GEHZuGsCprFRd4le0AdOeu+LrSo8eCBA10qEPHVqvMriqBW+7MTUmEwW01seGcLy8vw0OHIeYPLKMyeQqrMUhdE2d3TBZgqyzEkICG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954131; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kN7X/63OjI0YxgXw6QQNze3Fb3vk89R3yYS7zsFK+48=; b=JKotxe86GCfj9D4lzGutVM+hdVKVEAr9iSHHz1+uXPt+6Qxr/uLU/x0i6DP24MhYwJJghC0wYvQ7g8BUyPgcnBFQLpYH40TtRahTTxMu3VTQB620zjf4PSY/+aBVxOMV4DIJ33o8wc2VvvFTvnLyM785d8mmVPTUGWer6x2W9Tg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167795413153891.11190411465464; Sat, 4 Mar 2023 10:22:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTX-0006Sp-3S; Sat, 04 Mar 2023 13:19:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTQ-0006Ny-0g for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:12 -0500 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTL-0003ML-P9 for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:10 -0500 Received: by mail-pg1-x534.google.com with SMTP id d10so3280517pgt.12 for ; Sat, 04 Mar 2023 10:19:07 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kN7X/63OjI0YxgXw6QQNze3Fb3vk89R3yYS7zsFK+48=; b=w12u4z/4LCbFtvkOwPKPCzcvO9oiTYvafcTUuuhpoy41g8caHlLFn2sLCU/Gfte1YI 3/w6KTYbe2R4dA41h8ph5dszpbGytSeOehb9xjUPtGHaoixHY4fwC7vB91MPs1HFoyNs 7wX+EpK8fwYpwDz/J/Os6spEinahpfL9zT7NIoF7UterIklhilHxyCF790SV+iO1lcfA cyz8qFHIPRvpSwQUxU6JqDl3wU/W3bZLPFfhxrqD43RdDXLcpcrKvEvFEPBKBUl5Wbi3 IQn5LS6lll9/OhtQsZVufqGumC44Rfdg2dk1cHSabRoE6lVIBBz+DYOx+sl38YNE0Dfe W5Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kN7X/63OjI0YxgXw6QQNze3Fb3vk89R3yYS7zsFK+48=; b=Wlp5eRiVKkjImx1OlphVioyoueTa2VLN6BX9kMnMHlTByXrjpmdSBerg89Uygv/rpY ohxbIifjx1PuEVbUxqzsH2TNsxDVw2i/ep5A/tBuxsaWC8g6WM8TQ2WKurvJkxZ9TFNP vPfVwsq0DthRWOOIbvLelm+FeUMceWtOZN8jxODmB4aDVphq3JUpYm3gwFb6Bd4SNZSZ oK1GWKgD8YUPqOGAY/Ggf0fVjtK7C5zsSRZLgPTegPtiZ0oYs2NaLNTrqMGLIHilUZ7J J6hutJ1MOt7eeU4m5xeKWFF86dOl7hb/ggk/WNpWHsr4nto+aR9drJDUDlPxcrwGZtcO ogUA== X-Gm-Message-State: AO0yUKW1KseHdu59w3uCyfPk2WpU31ReAyu/27mNXlNFR3sZYqMavPV3 3vXYKDrpYDSqoDO+6AymT/joA9/xgqBfMYh4bwoCQQ== X-Google-Smtp-Source: AK7set/eNW9qhsNrKlSHC6X53pkJas4428ZSMlqCuYFwj3sL+UvE8eYzExw7/iveomOuaiqF1q4Hbg== X-Received: by 2002:a62:4ecb:0:b0:593:f191:966 with SMTP id c194-20020a624ecb000000b00593f1910966mr5132742pfb.1.1677953946476; Sat, 04 Mar 2023 10:19:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 05/20] target/mips: Drop tcg_temp_free from mxu_translate.c Date: Sat, 4 Mar 2023 10:18:45 -0800 Message-Id: <20230304181900.1097116-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954132780100011 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/mxu_translate.c | 51 --------------------------------- 1 file changed, 51 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translat= e.c index f52244e1b2..8703b0cef4 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -513,8 +513,6 @@ static void gen_mxu_s32i2m(DisasContext *ctx) } else if (XRa =3D=3D 16) { gen_store_mxu_cr(t0); } - - tcg_temp_free(t0); } =20 /* @@ -537,8 +535,6 @@ static void gen_mxu_s32m2i(DisasContext *ctx) } =20 gen_store_gpr(t0, Rb); - - tcg_temp_free(t0); } =20 /* @@ -613,9 +609,6 @@ static void gen_mxu_s8ldd(DisasContext *ctx) } =20 gen_store_mxu_gpr(t0, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* @@ -664,11 +657,6 @@ static void gen_mxu_d16mul(DisasContext *ctx) } gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); } =20 /* @@ -741,11 +729,6 @@ static void gen_mxu_d16mac(DisasContext *ctx) } gen_store_mxu_gpr(t3, XRa); gen_store_mxu_gpr(t2, XRd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); } =20 /* @@ -821,15 +804,6 @@ static void gen_mxu_q8mul_q8mulsu(DisasContext *ctx) =20 gen_store_mxu_gpr(t0, XRd); gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); - tcg_temp_free(t5); - tcg_temp_free(t6); - tcg_temp_free(t7); } =20 /* @@ -860,9 +834,6 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP)); =20 gen_store_mxu_gpr(t1, XRa); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -1125,9 +1096,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) tcg_gen_shri_i32(t0, t0, 16); /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); } else if (unlikely(XRb =3D=3D XRc)) { /* both operands same -> just set destination to one of them */ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); @@ -1161,9 +1129,6 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) tcg_gen_shri_i32(t0, t0, 16); /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); - - tcg_temp_free(t1); - tcg_temp_free(t0); } } =20 @@ -1226,9 +1191,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } - - tcg_temp_free(t1); - tcg_temp_free(t0); } else if (unlikely(XRb =3D=3D XRc)) { /* both operands same -> just set destination to one of them */ tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); @@ -1266,9 +1228,6 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } - - tcg_temp_free(t1); - tcg_temp_free(t0); } } =20 @@ -1384,9 +1343,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 24); =20 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN2: @@ -1410,9 +1366,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 16); =20 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN3: @@ -1436,9 +1389,6 @@ static void gen_mxu_S32ALNI(DisasContext *ctx) tcg_gen_shri_i32(t1, t1, 8); =20 tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); - - tcg_temp_free(t1); - tcg_temp_free(t0); } break; case MXU_OPTN3_PTN4: @@ -1598,7 +1548,6 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn) } =20 gen_set_label(l_exit); - tcg_temp_free(t_mxu_cr); } =20 return true; --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/nanomips_translate.c.inc | 127 ++--------------------- 1 file changed, 10 insertions(+), 117 deletions(-) diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nan= omips_translate.c.inc index faf6d679bd..b3df7fec40 100644 --- a/target/mips/tcg/nanomips_translate.c.inc +++ b/target/mips/tcg/nanomips_translate.c.inc @@ -1005,13 +1005,9 @@ static void gen_llwp(DisasContext *ctx, uint32_t bas= e, int16_t offset, tcg_gen_extr_i64_tl(tmp1, tmp2, tval); } gen_store_gpr(tmp1, reg1); - tcg_temp_free(tmp1); gen_store_gpr(tmp2, reg2); - tcg_temp_free(tmp2); tcg_gen_st_i64(tval, cpu_env, offsetof(CPUMIPSState, llval_wp)); - tcg_temp_free_i64(tval); tcg_gen_st_tl(taddr, cpu_env, offsetof(CPUMIPSState, lladdr)); - tcg_temp_free(taddr); } =20 static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset, @@ -1084,9 +1080,6 @@ static void gen_save(DisasContext *ctx, uint8_t rt, u= int8_t count, =20 /* adjust stack pointer */ gen_adjust_sp(ctx, -u); - - tcg_temp_free(t0); - tcg_temp_free(va); } =20 static void gen_restore(DisasContext *ctx, uint8_t rt, uint8_t count, @@ -1110,9 +1103,6 @@ static void gen_restore(DisasContext *ctx, uint8_t rt= , uint8_t count, =20 /* adjust stack pointer */ gen_adjust_sp(ctx, u); - - tcg_temp_free(t0); - tcg_temp_free(va); } =20 static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc, @@ -1232,8 +1222,6 @@ static void gen_compute_branch_nm(DisasContext *ctx, = uint32_t opc, if (insn_bytes =3D=3D 2) { ctx->hflags |=3D MIPS_HFLAG_B16; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_pool16c_nanomips_insn(DisasContext *ctx) @@ -1358,7 +1346,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) } break; } - tcg_temp_free(t0); #endif } else { gen_slt(ctx, OPC_SLTU, rd, rs, rt); @@ -1381,10 +1368,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) /* operands of same sign, result different sign */ tcg_gen_setcondi_tl(TCG_COND_LT, t0, t1, 0); gen_store_gpr(t0, rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } break; case NM_MUL: @@ -1427,7 +1410,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) =20 gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rs, extract32(ctx->opcode, 11, 3)); - tcg_temp_free(t0); } break; case NM_D_E_MT_VPE: @@ -1467,8 +1449,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) } break; } - - tcg_temp_free(t0); } break; case NM_FORK: @@ -1480,8 +1460,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); gen_helper_fork(t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case NM_MFTR: @@ -1508,7 +1486,6 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *= env, DisasContext *ctx) gen_load_gpr(t0, rs); gen_helper_yield(t0, cpu_env, t0); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; #endif @@ -1557,11 +1534,6 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasCon= text *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free_i32(t0); - - tcg_temp_free(v0_t); - tcg_temp_free(v1_t); } =20 =20 @@ -1682,10 +1654,6 @@ static void gen_pool32axf_1_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(v0_t); } =20 static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc, @@ -1802,8 +1770,6 @@ static void gen_pool32axf_2_multiply(DisasContext *ct= x, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free_i32(t0); } =20 static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -1855,10 +1821,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_MULT: @@ -1878,8 +1842,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case NM_EXTRV_W: @@ -1915,10 +1877,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_MULTU: @@ -1938,8 +1898,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasContex= t *ctx, uint32_t opc, tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case NM_EXTRV_R_W: @@ -1982,10 +1940,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_EXTRV_RS_W: @@ -2027,10 +1983,8 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case NM_EXTRV_S_H: @@ -2045,12 +1999,6 @@ static void gen_pool32axf_2_nanomips_insn(DisasConte= xt *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(t0); - tcg_temp_free(t1); - - tcg_temp_free(v0_t); - tcg_temp_free(v1_t); } =20 static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -2162,7 +2110,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContex= t *ctx, uint32_t opc, gen_load_gpr(tv0, rt); gen_helper_insv(v0_t, cpu_env, v0_t, tv0); gen_store_gpr(v0_t, ret); - tcg_temp_free(tv0); } break; case NM_RADDU_W_QB: @@ -2188,9 +2135,6 @@ static void gen_pool32axf_4_nanomips_insn(DisasContex= t *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(v0_t); - tcg_temp_free(t0); } =20 static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc, @@ -2243,8 +2187,6 @@ static void gen_pool32axf_7_nanomips_insn(DisasContex= t *ctx, uint32_t opc, gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); - tcg_temp_free(rs_t); } =20 =20 @@ -2304,7 +2246,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; - tcg_temp_free(t0); } break; case NM_EI: @@ -2317,7 +2258,6 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState = *env, DisasContext *ctx) gen_store_gpr(t0, rt); /* Stop translation as we may have switched the execution mode= */ ctx->base.is_jmp =3D DISAS_STOP; - tcg_temp_free(t0); } break; case NM_RDPGPR: @@ -2374,7 +2314,7 @@ static void gen_compute_imm_branch(DisasContext *ctx,= uint32_t opc, /* Unconditional branch */ } else if (rt =3D=3D 0 && imm !=3D 0) { /* Treat as NOP */ - goto out; + return; } else { cond =3D TCG_COND_EQ; } @@ -2384,12 +2324,12 @@ static void gen_compute_imm_branch(DisasContext *ct= x, uint32_t opc, check_nms(ctx); if (imm >=3D 32 && !(ctx->hflags & MIPS_HFLAG_64)) { gen_reserved_instruction(ctx); - goto out; + return; } else if (rt =3D=3D 0 && opc =3D=3D NM_BBEQZC) { /* Unconditional branch */ } else if (rt =3D=3D 0 && opc =3D=3D NM_BBNEZC) { /* Treat as NOP */ - goto out; + return; } else { tcg_gen_shri_tl(t0, t0, imm); tcg_gen_andi_tl(t0, t0, 1); @@ -2404,7 +2344,7 @@ static void gen_compute_imm_branch(DisasContext *ctx,= uint32_t opc, case NM_BNEIC: if (rt =3D=3D 0 && imm =3D=3D 0) { /* Treat as NOP */ - goto out; + return; } else if (rt =3D=3D 0 && imm !=3D 0) { /* Unconditional branch */ } else { @@ -2434,7 +2374,7 @@ static void gen_compute_imm_branch(DisasContext *ctx,= uint32_t opc, default: MIPS_INVAL("Immediate Value Compact branch"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* branch completion */ @@ -2455,10 +2395,6 @@ static void gen_compute_imm_branch(DisasContext *ctx= , uint32_t opc, =20 gen_goto_tb(ctx, 0, ctx->base.pc_next + 4); } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* P.BALRSC type nanoMIPS R6 branches: BALRSC and BRSC */ @@ -2488,9 +2424,6 @@ static void gen_compute_nanomips_pbalrsc_branch(Disas= Context *ctx, int rs, /* unconditional branch to register */ tcg_gen_mov_tl(cpu_PC, btarget); tcg_gen_lookup_and_goto_ptr(); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* nanoMIPS Branches */ @@ -2540,14 +2473,12 @@ static void gen_compute_compact_branch_nm(DisasCont= ext *ctx, uint32_t opc, gen_load_gpr(tbase, rt); tcg_gen_movi_tl(toffset, offset); gen_op_addr_add(ctx, btarget, tbase, toffset); - tcg_temp_free(tbase); - tcg_temp_free(toffset); } break; default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 if (bcond_compute =3D=3D 0) { @@ -2559,7 +2490,7 @@ static void gen_compute_compact_branch_nm(DisasContex= t *ctx, uint32_t opc, default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } } else { /* Conditional compact branch */ @@ -2620,7 +2551,7 @@ static void gen_compute_compact_branch_nm(DisasContex= t *ctx, uint32_t opc, default: MIPS_INVAL("Compact conditional branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* branch completion */ @@ -2633,10 +2564,6 @@ static void gen_compute_compact_branch_nm(DisasConte= xt *ctx, uint32_t opc, =20 gen_goto_tb(ctx, 0, ctx->base.pc_next + 4); } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -2664,15 +2591,12 @@ static void gen_compute_branch_cp1_nm(DisasContext = *ctx, uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } =20 tcg_gen_trunc_i64_tl(bcond, t0); =20 ctx->btarget =3D btarget; - -out: - tcg_temp_free_i64(t0); } =20 =20 @@ -2709,7 +2633,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int = rs, int rt) break; default: gen_reserved_instruction(ctx); - goto out; + return; } } gen_op_addr_add(ctx, t0, t0, t1); @@ -2799,10 +2723,6 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int= rs, int rt) gen_reserved_instruction(ctx); break; } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_pool32f_nanomips_insn(DisasContext *ctx) @@ -3443,7 +3363,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *= ctx, int opc, gen_helper_precr_sra_ph_w(v1_t, sa_t, v1_t, cpu_gpr[rt]); gen_store_gpr(v1_t, rt); - tcg_temp_free_i32(sa_t); } break; case 1: @@ -3453,7 +3372,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *= ctx, int opc, gen_helper_precr_sra_r_ph_w(v1_t, sa_t, v1_t, cpu_gpr[rt]); gen_store_gpr(v1_t, rt); - tcg_temp_free_i32(sa_t); } break; } @@ -3536,8 +3454,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext *= ctx, int opc, tcg_gen_movi_tl(tv0, rd >> 3); tcg_gen_movi_tl(tv1, imm); gen_helper_shilo(tv0, tv1, cpu_env); - tcg_temp_free(tv1); - tcg_temp_free(tv0); } break; case NM_MULEQ_S_W_PHL: @@ -3652,10 +3568,6 @@ static void gen_pool32a5_nanomips_insn(DisasContext = *ctx, int opc, gen_reserved_instruction(ctx); break; } - - tcg_temp_free(v2_t); - tcg_temp_free(v1_t); - tcg_temp_free(t0); } =20 static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) @@ -3827,7 +3739,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) =20 tcg_gen_movi_tl(t0, addr); tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_T= ESL); - tcg_temp_free(t0); } break; case NM_SWPC48: @@ -3844,9 +3755,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t1, rt); =20 tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); - - tcg_temp_free(t0); - tcg_temp_free(t1); } break; default: @@ -3908,8 +3816,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t0, rs); tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, imm); gen_store_gpr(t0, rt); - - tcg_temp_free(t0); } break; case NM_ADDIUNEG: @@ -3965,11 +3871,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *e= nv, DisasContext *ctx) =20 gen_load_gpr(t0, rs); gen_helper_rotx(cpu_gpr[rt], t0, shift, shiftx, stripe); - tcg_temp_free(t0); - - tcg_temp_free_i32(shift); - tcg_temp_free_i32(shiftx); - tcg_temp_free_i32(stripe); } break; case NM_P_INS: @@ -4239,8 +4140,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) MO_UNALN); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case NM_P_LL: @@ -4432,8 +4331,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) } counter++; } - tcg_temp_free(va); - tcg_temp_free(t1); } break; default: @@ -4454,7 +4351,6 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_load_gpr(t0, rt); tcg_gen_mov_tl(cpu_gpr[rd], t0); gen_compute_branch_nm(ctx, OPC_BGEZAL, 4, 0, 0, s); - tcg_temp_free(t0); } break; case NM_P_BAL: @@ -4606,7 +4502,6 @@ static int decode_isa_nanomips(CPUMIPSState *env, Dis= asContext *ctx) if (ctx->base.pc_next & 0x1) { TCGv tmp =3D tcg_const_tl(ctx->base.pc_next); tcg_gen_st_tl(tmp, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr)); 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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y9Yxuq9oSk+IAEhFz8O1INvxDLagZl+WTzfcEJCwEho=; b=GfgywBfz35AbuxjVfJlSAM1gvH+VLw23/4t+VJBgUUW/bnBNrNgUNdAjNIXjZ4JmAM RaVRzBhaN9sRilggkXHWaG08zvTCikRQvFhEKd1vVGrTCkeAMSjUIEcVrjjSk9a5ruO3 fAlldyLtQ6Mm5wokPT4kMAZgxxKMrlE3mdKGzLK75jVgG+DPh7j7l36znE9qBNwIDM0D TAHjXAp731qmNnjcoWf1CyDBQLGvEPHsujRSkSIbYCvM4kpgLd8SneDa4u5NEwtWPXUv RwYMza1YUmXJ3Vy99cdR+BQWLSQOh59Q0gkEjxqS59N/WiPDX+hVW147l24ZHaji2R/q d1Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y9Yxuq9oSk+IAEhFz8O1INvxDLagZl+WTzfcEJCwEho=; b=QlRYtqs+tcfNzU5n0cISYKD8VbU3QRJeQMxQ1XtZfu6iMIs3tgS+iSLM8xeMfu9MXo Z27YWOVV3VvR+aNaKzrdv1+zAO6mW4x5U55QWXAtyBMTEUdtzBBNy3LHbsTpVh8QqNRP oHic9IViVBikXb0CVcJkAE5jRRr3h7qs9s8PhTgm2fy9c0AD5fIAbqrxSMV6GNYg3rqh WQcpdoJIWa15gLYFRx6vbAt8ylFjHLzZHh/is31sjtHFad9Wl/HYaY75iDc5qcu/3r3b BXRKji+4XVAR7PH+AHdfesUrSXkkIZXiSS3qihgg64dml+0yunSvp3dNL3TvbX60Wu/u m+Ag== X-Gm-Message-State: AO0yUKWo7Wze06ez4R1/m8n142ModxpTBQNGE3cVTBpIgpeqnakPKRs7 1b33mMQ3am/dsKD8WxZE4JfgOMLpe/YvOyQ2I9yfaw== X-Google-Smtp-Source: AK7set9kz5/f4kfVcIRR3KRzXxMlCQUM/U5KkibzjxKjXKONFVP9bdhAlke+72KV++G8+rz8Cw/Mhw== X-Received: by 2002:aa7:9d11:0:b0:602:7c0:3afe with SMTP id k17-20020aa79d11000000b0060207c03afemr5912165pfp.26.1677953948385; Sat, 04 Mar 2023 10:19:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 07/20] target/mips: Drop tcg_temp_free from octeon_translate.c Date: Sat, 4 Mar 2023 10:18:47 -0800 Message-Id: <20230304181900.1097116-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677953991673100003 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/octeon_translate.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_tr= anslate.c index 6a207d2e7e..103c304d10 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -40,8 +40,6 @@ static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) ctx->hflags |=3D MIPS_HFLAG_BC; ctx->btarget =3D ctx->base.pc_next + 4 + a->offset * 4; ctx->hflags |=3D MIPS_HFLAG_BDS32; - - tcg_temp_free(t0); return true; } =20 @@ -61,10 +59,6 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a) =20 tcg_gen_add_tl(t0, t0, t1); tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 @@ -83,10 +77,6 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a) gen_load_gpr(t1, a->rt); =20 tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 @@ -103,8 +93,6 @@ static bool trans_EXTS(DisasContext *ctx, arg_EXTS *a) gen_load_gpr(t0, a->rs); tcg_gen_sextract_tl(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); - tcg_temp_free(t0); - return true; } =20 @@ -121,8 +109,6 @@ static bool trans_CINS(DisasContext *ctx, arg_CINS *a) gen_load_gpr(t0, a->rs); tcg_gen_deposit_z_tl(t0, t0, a->p, a->lenm1 + 1); gen_store_gpr(t0, a->rt); - tcg_temp_free(t0); - return true; } =20 @@ -142,8 +128,6 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a) } tcg_gen_ctpop_tl(t0, t0); gen_store_gpr(t0, a->rd); - tcg_temp_free(t0); - return true; } =20 @@ -167,10 +151,6 @@ static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *= a) } else { tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0); } - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 @@ -194,8 +174,5 @@ static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI = *a) } else { tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm); } - - tcg_temp_free(t0); - return true; } --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954166; cv=none; d=zohomail.com; s=zohoarc; b=a0GlS55tsc7xnDjkRmQk9GbkLjMZA4k9LYARA/UYn0B4bxt5+n+/ldNwSXaQUBVtOjU0iIjz3STyveJddkuAGINySr3BeblQEv2jibRtnQN8U8zDTQILfqBrF+zojDm/NckdKQYKBkU9ZHPVocJC4z98OwQ851+O8DSoRj58rTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954166; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BuI6QTMekuD+wzq4FTKchxi3GxTyvtiesMoc0e7akdM=; b=BFGKFMT0XtfL+DHxg7YMVIE4/Xi0C61HmSDJdvcLbMiUvl1SDk1bAJzik38Vz1sJD/wCqL1gH/OAtIQqCj0ByLa9IAMKTPA/zblULwMf2dOP8E4FWoLMxwGyDvP5Dx2+GgkhYRIQdRwIg7x2qW4TR2ixA22bJh7aOjPcvuCOC28= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677954166184466.7417986407926; Sat, 4 Mar 2023 10:22:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTW-0006Sm-Fz; Sat, 04 Mar 2023 13:19:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTR-0006Oy-73 for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:13 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTP-0003Mm-Eu for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:12 -0500 Received: by mail-pl1-x629.google.com with SMTP id i10so6056789plr.9 for ; Sat, 04 Mar 2023 10:19:10 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BuI6QTMekuD+wzq4FTKchxi3GxTyvtiesMoc0e7akdM=; b=Ux7QDoXCnOI7xJiABiqv7tpW+QYkZYCWESYN9pikEX1gfBm/4jAOXsyqdnM9BlIbag XKbkNRfxSY77Xz4BNTbJIEG31hRvqj7jzb5+vRwoYm9thNC0vlVhE/1nUo06R2w+BDf/ bOAFSBn7+yiKYBSSC/zrvQl8FHJzmk+ktr7TYYeoP7G7tRKekJ8gCoA+tpXlUyoNAyv+ ec0PyePPZ46iVd+dyPv0qrM2YD0GwRhNHO/lgirOQpWkIWCw9LDeby3X57hXBxHWL1AT I2Vhf+aML8d1cqruE2GKKWyVMGiO0516OZDN5duFp2v6Iv3glQ7D5rcljKOVOIy4FdrM 4H7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BuI6QTMekuD+wzq4FTKchxi3GxTyvtiesMoc0e7akdM=; b=w8zieZN/vjHs0E5v2aOo1ARqIxnV1wXTT4ch36xulKwPZ/whw9tENoKRWlkUiT+M23 v2MzjNGT9R6UACyAbGGj3n8ZdzXw6wErWRH7OmI05CET+gnqywZFprRv50/0YkFDqto1 HG6LemQjgko00YM2PE2mzZbUAB1AzbI6tqjuJXgb2V6FsfnBlujPQ9gfFLtHZVQKslmT wGcQORm3RTPAvHEnZQ0AjGcpZL1HWWTcMBiwZ4otpbp9gt1+JiSPgcOiEM+5pcVr/7jS UYYPRp+69wDlqDD5U1A1uHbAzo6ydapS8daFkm+6njWd4SsZ7L+0zEojrsv8MOQFq7qp /ixQ== X-Gm-Message-State: AO0yUKXlGr5Svkg904DLrUgrFyzpFcxBkRiBH0JKxaYMnKS7D+2cV/vb kjUDiUoBENR/D8E4VFG+ARNIiIPf/bBGWPIpbBfKOw== X-Google-Smtp-Source: AK7set9fHxluwyRQDEGkm4MW3Ww3/TQHME9y5FL5Ag/hqLaShVuI2UR9gRkmK3p9PvMwM0kRpd+dFw== X-Received: by 2002:a05:6a20:429e:b0:cc:af12:44ea with SMTP id o30-20020a056a20429e00b000ccaf1244eamr6800922pzj.51.1677953949218; Sat, 04 Mar 2023 10:19:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 08/20] target/mips: Drop tcg_temp_free from translate_addr_const.c Date: Sat, 4 Mar 2023 10:18:48 -0800 Message-Id: <20230304181900.1097116-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954166941100001 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/translate_addr_const.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/trans= late_addr_const.c index 96f483418e..a510da406c 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -30,10 +30,6 @@ bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, = int sa) tcg_gen_shli_tl(t0, t0, sa + 1); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - - tcg_temp_free(t1); - tcg_temp_free(t0); - return true; } =20 @@ -54,8 +50,5 @@ bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, = int sa) gen_load_gpr(t1, rt); tcg_gen_shli_tl(t0, t0, sa + 1); tcg_gen_add_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t1); - tcg_temp_free(t0); - return true; } --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954068; cv=none; d=zohomail.com; s=zohoarc; b=FVTX+VCty9jZv/ZuVPf+YAZRxlwDswf8kIalRnHGoQAIVZR5UZjOWiospRvUkYPD+DFKFy7o4/lU7E2anGnt4+Q0Ct7z+8bp/DoR0j19IRPZ5tLD8hRT/2P1HnwfUiLBzQIY3Lv4dOew6hUJMYDPMXCnicvoI9GPmA2u6FdqkIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954068; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nzwi1YY4fVnASIKsZHJLoZ/APWSKzcHeQLTvYVw2zL8=; b=TKM1s/cjTmNEfyEeQNQ+dm6JN/lJCggUb0iZc1hgxU/zBuXL63BwYRvGQBrp42jMQmFjQElkubTm8NPeUlj5h6c7RQGf0rCZrzjpcr6ju+xyoOqDZ41YDu/+IIUMMNZue/RPKh5Z2SoC4KPjyMAH5j37QiJViwcaBS0u0I8DWQk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167795406857087.88344941522917; Sat, 4 Mar 2023 10:21:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTX-0006Sq-4h; Sat, 04 Mar 2023 13:19:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTR-0006P0-Az for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:13 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTP-0003N3-KS for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:13 -0500 Received: by mail-pj1-x1032.google.com with SMTP id x34so5943544pjj.0 for ; Sat, 04 Mar 2023 10:19:11 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953950; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nzwi1YY4fVnASIKsZHJLoZ/APWSKzcHeQLTvYVw2zL8=; b=MZ7ztywNE98M97DRv1yZZ+zEo6VebFenw23bkdrumJ2YIaXacQOMderRJJod/Sbb/Y 2il3Mfbo7cEEBb9xHyHcE/Sq3tDdMIKMoOLl6f26o7XMzj+4CkZkqi7yLhMXBXIr9RQl jIKxLNDgHOAp+Gtg+WdfQc4zQea819pEZ64DfcPNdyZo67BOFDCoMcZe7MGqRQIWx+CT Eqa6sXt0SzQAUhEmJKTOPndDfejHBkUm/FeOKETtzWdSa6eC55DpMyRAcBnhcne3MeLf j6Vk7uQUQ7YjFQgOW+93u8GHlTsT5tN/PaljELGU5JD02adft1C2ocnxPPHfiu1zkZyk nLfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953950; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nzwi1YY4fVnASIKsZHJLoZ/APWSKzcHeQLTvYVw2zL8=; b=hfDk3YiWBO0SclGhZQAlxciuOqpkJ7O1d8Ns9Mw2sJaOfr+MRa4o5gFZwXStgx1DaJ tDqQvEfCS0xm5EpzT7pEnMGfePQUzTYRknus7Tr6Z1GkjEwSTRecCBhuyHOzSNj55rDR qca0KYNhXPP0S9N8hywebKd50wfqjLwNkT4ONigqng9yAeffUogrWiaObMtx4QxX1Shw A4xQDTp6sr9jkr++bOOgdi/qT15xIVvAO0z1d+co0/5ml7tEdkcsD8KRDrHObPNbUW2N i4W2cWMxJNv2FdM3+URUPyAYQDsvc2qaJGgyzKy0UUj16f0gKteT7DkgMmGvQfF3mnbF akIA== X-Gm-Message-State: AO0yUKUNRJyVqB3o/zF+Lc/zwUFF+0ik3dV3UKy05tSBo2SdlBjREF4p MYRcHokgCFiOJY3EctrFvcqHr5WGtxXkArF2lPwg7w== X-Google-Smtp-Source: AK7set9B+Bc7yNmnfG3zJtvgWroQ9l2kDx3C9TE8bjAhrUmILFhMDsn3aWL0ltYt7sKmj30LGvuO2w== X-Received: by 2002:a05:6a20:6982:b0:cb:c276:58d6 with SMTP id t2-20020a056a20698200b000cbc27658d6mr11157382pzk.34.1677953950180; Sat, 04 Mar 2023 10:19:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 09/20] target/mips: Drop tcg_temp_free from tx79_translate.c Date: Sat, 4 Mar 2023 10:18:49 -0800 Message-Id: <20230304181900.1097116-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954070552100005 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/tx79_translate.c | 41 -------------------------------- 1 file changed, 41 deletions(-) diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index 4e479c2d10..d46bc73972 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -138,10 +138,6 @@ static bool trans_parallel_arith(DisasContext *ctx, ar= g_r *a, gen_load_gpr_hi(ax, a->rs); gen_load_gpr_hi(bx, a->rt); gen_logic_i64(cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -273,15 +269,6 @@ static bool trans_parallel_compare(DisasContext *ctx, = arg_r *a, tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], t2, wlen= * i, wlen); } - - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); - tcg_temp_free(bx); - tcg_temp_free(ax); - tcg_temp_free(c1); - tcg_temp_free(c0); - return true; } =20 @@ -362,10 +349,6 @@ static bool trans_LQ(DisasContext *ctx, arg_i *a) tcg_gen_addi_i64(addr, addr, 8); tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEUQ); gen_store_gpr_hi(t0, a->rt); - - tcg_temp_free(t0); - tcg_temp_free(addr); - return true; } =20 @@ -389,10 +372,6 @@ static bool trans_SQ(DisasContext *ctx, arg_i *a) tcg_gen_addi_i64(addr, addr, 8); gen_load_gpr_hi(t0, a->rt); tcg_gen_qemu_st_i64(t0, addr, ctx->mem_idx, MO_TEUQ); - - tcg_temp_free(addr); - tcg_temp_free(t0); - return true; } =20 @@ -458,11 +437,6 @@ static bool trans_PPACW(DisasContext *ctx, arg_r *a) =20 gen_load_gpr_hi(t0, a->rs); /* a1 */ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], a0, t0, 32, 32); - - tcg_temp_free(t0); - tcg_temp_free(b0); - tcg_temp_free(a0); - return true; } =20 @@ -506,10 +480,6 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, = unsigned wlen) tcg_gen_shri_i64(bx, bx, wlen); tcg_gen_shri_i64(ax, ax, wlen); } - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -541,10 +511,6 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_r *a) gen_load_gpr(ax, a->rs); gen_load_gpr(bx, a->rt); gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -564,10 +530,6 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_r *a) gen_load_gpr_hi(ax, a->rs); gen_load_gpr_hi(bx, a->rt); gen_pextw(cpu_gpr[a->rd], cpu_gpr_hi[a->rd], ax, bx); - - tcg_temp_free(bx); - tcg_temp_free(ax); - return true; } =20 @@ -678,8 +640,5 @@ static bool trans_PROT3W(DisasContext *ctx, arg_r *a) =20 tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rt], ax, 0, 32); tcg_gen_rotri_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], 32); - - tcg_temp_free(ax); - return true; } --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; 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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=niO44Co69efms0IVc6R/k9jlve0XAcHkzZjYqfu6blc=; b=M+db+6/rIzU9/TzG9ZDmwawINLpJLXeUhz6Y2nXuO8qiX2Ngo0VEdIDGveWQadP8cN EBUv7zLXiFCAEefXjSrGPvgrJxtI44+3lPUf12+xRcRGnFuHS+PpyqqI4HNB+MnXqydw 2fol816FUob475DX/SNjUFcyj4XK3XIkroHIIOLbMEUNmPobvFSH/p7WXuVrchMBSDw1 57gl29ZjzE++/NSaglDfUUMv9CpYzXI2pBRv09UnsPy95G9WkwQzbZvjwOva/woc2HwM SXj8/GO0xgPQ+0e1qplbidl4ZDwbJeexv85yPQin+p1tj+xG+GGzYoJq9aHvxulftVAf Yx5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=niO44Co69efms0IVc6R/k9jlve0XAcHkzZjYqfu6blc=; b=umehgvbt68KsO71/eWnAsqflaM6voPDfspSmcPbDzxawX7eEj7RLWDA3PMbw8psHVo cgxv/qzl9wTO1f4sV4B9eBWsk+/Lh2zcucghD0BlAE/rK202CJCA5cxnAjNyhsU/QWv0 vtW8LSASq5elaPGZWyElo4+O5J9pHRRPcOB7Co/XbrTT/0H4/i7nfcgOEvFSpeKcDldm d9HKSXVZSHGRKQ9qNl60xxmjrRm3mDyuOCpgetZm68zKTjq4MCOD9C0r5aN1Yyy886sk SD5BZe0nWrVHTsoCSp1JML5CJT2MCblmwlB4MXHspdAtlFtZ/S9ZN8kLlWnHc+Q1QPvC vQ2g== X-Gm-Message-State: AO0yUKUQFPl8yTdhZ4v2SY3ISxQDXV/hbXRi7LjSXj8Ebd1QDkIfM5CJ Vtkhe7iDZkqovjjzJKfhsdPyuQxoM/Ab/tWbHlk78A== X-Google-Smtp-Source: AK7set8nMfSp7bq1aKQsJXfl31L5cG7eG0nlV+/eBRoD27Vg0MuhH4CGr42SNOUgA1TZZ62St0eB0g== X-Received: by 2002:a62:38c3:0:b0:5d9:e505:3466 with SMTP id f186-20020a6238c3000000b005d9e5053466mr5307338pfa.23.1677953951117; Sat, 04 Mar 2023 10:19:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 10/20] target/mips: Fix trans_mult_acc return Date: Sat, 4 Mar 2023 10:18:50 -0800 Message-Id: <20230304181900.1097116-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954140815100003 Success from trans_* subroutines should be true. Fixes: 5fa38eedbd ("target/mips: Convert Vr54xx MACC* opcodes to decodetree= ") Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/mips/tcg/vr54xx_translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index 3e2c98f2c6..a7d241e4e7 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -53,7 +53,7 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a, tcg_temp_free(t0); tcg_temp_free(t1); =20 - return false; + return true; } =20 TRANS(MACC, trans_mult_acc, gen_helper_macc); --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954080; cv=none; d=zohomail.com; s=zohoarc; b=EkBCwBxLDf9UY9UHyqhS0wrd6+qWfcr+NSiWBf44VU3NtD/8+O48/cxJFLf/CJ0g3zwCVqugyP/WAxI0yK2UonxBO0agn786k12CKvXUWOlICpab41QyjWckodvKHWwy2tpmqRpY6QYoUwjPFreJSODasjd8r9mxpZBhm+YyZ7M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954080; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5UwUYgI1qBBmzGL8lHSf6ndjeIZ/lkTM7FpzJkl1le4=; b=kv/xJqQKW1y37bPUZ9yTa4obwZyP7ZixBq0sshGeAotvjgHTioIsL4tjhb9aGMzcxfU3MWBvJeu24aNHaHXCbEBLLqW/g15xE17oTkaGyljyYYIx1scx6RMjP1taY0Rr/SaezS4PEpuYwuugS8d4gKv4UNj6MMRQ3CpEP3cPGyg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677954080455984.0843667304498; Sat, 4 Mar 2023 10:21:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTZ-0006Tx-At; Sat, 04 Mar 2023 13:19:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTS-0006QN-Mx for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:14 -0500 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTR-0003Ne-8a for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:14 -0500 Received: by mail-pf1-x430.google.com with SMTP id y10so3421557pfi.8 for ; Sat, 04 Mar 2023 10:19:12 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5UwUYgI1qBBmzGL8lHSf6ndjeIZ/lkTM7FpzJkl1le4=; b=ZEpR9qnGXXy3wtf0zu3UR6/7hZKk8uxGVEIxV1WLqaflS56nnifXwPcPpGhNVSLadG DlSzZE1RQDsLYhBtsbNXKoZWbHWNIqtfPHYRbmEozDP7hNk1nzK5gLm49dXnAalTITnw NRPATJPtl8mD0gvi9hHNHdsNFxtRdfKtH7nE+8ASPIazN6qa+Vm/MDh4LpWXZhdAoU+g qItyoGJ4yNwuATh9g7dxiXIUFaOtmwrTL2g3jaEZ1w6wdLs4fJ/Y+Mve7eZQBr4vRxZ1 ZLCGQTtjF0RjwEIeJj0VGozMVNpCJpS4RStgngeCf3vpS/y2d+WrTOmwVBE78QFNgcKb KjCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5UwUYgI1qBBmzGL8lHSf6ndjeIZ/lkTM7FpzJkl1le4=; b=A5m4WI+NC5RsoKAYsCRpq9w6NXWc3zsB6JGcOE3/iPwVZnLE3SmkgHNcDodlwjdXpx OFYrnbahHeMJV390OIx/0Bp3r0xHdbwQC8URRa7nsm65yvWE8zGsXYOGGKrcfvE69gDC 41s8zr5YCzYjVN0tFRkYivot2C7ldXuyxHkQrKm3Xh2fdBn1EDXwX+SNoaSrI5Wpf4W9 kWEPw5zRavVU5PK8X8V/TCFAKT1IGTOpdMI2vdEKykHfhFDwwC+695w8Gv4Vuj5dfvh2 wJVSlvxOnamczoi/J0FUiDXb1emOcOuiQ7kGi2oHCc7f1pEPhbGiB6VkEkDHn0owdrqp 233g== X-Gm-Message-State: AO0yUKV7koefrdKCrTb4K8Pi93YjrZVxpe1YSZ8mxg7qX0CtXj+v4rJW G0wo/TREbM+Nw3q4sXiL68TyIYjC7Axl/aGwl1jQcQ== X-Google-Smtp-Source: AK7set/gTjS786ddrIRm6L/4kdyMSGAC5q57ThL6FUSZjHKJ5y7rA+GgimlQ7nDPP478NPPwvYCkaA== X-Received: by 2002:a05:6a00:796:b0:5a8:e3d5:d7d4 with SMTP id g22-20020a056a00079600b005a8e3d5d7d4mr9302178pfu.7.1677953951884; Sat, 04 Mar 2023 10:19:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 11/20] target/mips: Drop tcg_temp_free from vr54xx_translate.c Date: Sat, 4 Mar 2023 10:18:51 -0800 Message-Id: <20230304181900.1097116-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954082621100006 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/vr54xx_translate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_tr= anslate.c index a7d241e4e7..804672f84c 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -49,10 +49,6 @@ static bool trans_mult_acc(DisasContext *ctx, arg_r *a, gen_helper_mult_acc(t0, cpu_env, t0, t1); =20 gen_store_gpr(t0, a->rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); - return true; } =20 --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954074; cv=none; d=zohomail.com; s=zohoarc; b=flKNrBmPDOR90jma1HnCOPvnQO8nF0vMzcHWvyByGqpsupxHuiE/b128GUqGqKcKA56Rsz83dh/ZQzXJpcjetUwCTf62iIln+Jm6oBtuVPHPyo2ztyvwTpAlibxVv4gKbAecBNy/blzV9SQuRmMd3zGP7syT7yi9qwdFy+BQ3kI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954074; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zkn/AVb5efhnQvXcC4LgU7jpo8davlg5CB77WZ6Pzb0=; b=CLcDaXNxXK1/tvOIYIonMjX+cy5hGdwNU0KuZJVLsmfLJZlaj14J/RGaxpuK85neGVvcX9UHhMJTKeShIaeeapWdEFm/m02oz+VI/jCxnNA7n1mjWvthNZoPxKpu6uLF3KU6sX3BNoxugiYBPOhojp7Yi4Vs9VORTjLVlvutgFc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677954074860525.6275006415046; Sat, 4 Mar 2023 10:21:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTZ-0006V7-Vc; Sat, 04 Mar 2023 13:19:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTW-0006SV-6k for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:18 -0500 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTS-0003Ny-C5 for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:17 -0500 Received: by mail-pg1-x535.google.com with SMTP id bn17so3285738pgb.10 for ; Sat, 04 Mar 2023 10:19:13 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zkn/AVb5efhnQvXcC4LgU7jpo8davlg5CB77WZ6Pzb0=; b=xr6hxJ49MEbTlY2o595hAgprCd8IBbO5GWyeC23klFv46obK1m4UA7sAu+tbDqxa74 tl/RWpzystcmCMpX8bOdGTHYX5VXd2wRuZBV0LG3VOpsIFzzM7NEYXg5bl4lbQIbyAxr chIDFN8i+Br38y+mZfCLVgAUgELrmR9xTGO+enoxAK25rkf30BLNISCd58CbGcRnXX8P 5secmdDzIebqzUe4cEeg4A+79iuWeUQvgf3odlctTsBCSCo1ae3xyWQ8+r/xt7JgAOVg LFlVDAkIEln37LEohneEFz8BT1crHb6ql78X/DczOqTEW/CPb2JIgUdr48y3YmUFb7hF OPnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zkn/AVb5efhnQvXcC4LgU7jpo8davlg5CB77WZ6Pzb0=; b=0lHPVcJDRK803j6bDLIXrJRDaG50ZbXOrgp/EV3HFUiqJWPgH/YAps20ozBHl/M2AV 3pzVnsSrc+QbztMixmGFgDFOtaLGIvMfcMh6ig46euTF8dq16/Y7yNDk9xOuJUH1cJ/w VY3QqV9P4bZBPY5HECC+BecLUYz0rMDtslKkc9nN9sVlCz1FpsaPJcdwlEw92QlgJwNX PNCQNpMIDvCeYuQA3HgR/re5ruPKqU41bKMyx0qWALidyY6gf2SLKzoHpI26gEJWyLiK vnPTlLjydt75PNlyFNpt0ChF3Kd1cNpSEH+8bRqQibP4hfJdn8O7c6DOLEm5kIduZu5v LBfA== X-Gm-Message-State: AO0yUKUBh0i/kZSKDnWYcCfZZDhhSyxAwKH25bsadRqOWswyMbJZFqq6 wQOYdyHQLn+XVm9HAWZd+ng2DLnu9IBzJEy2dIevIA== X-Google-Smtp-Source: AK7set+/WkQc2PW3Ix1z00vb705NwIgHzhSxMuJJFmw4fxTn1zHY7OFBYKhXxQryRr1TBkF/6CZTcw== X-Received: by 2002:aa7:968e:0:b0:5aa:72c6:4a7d with SMTP id f14-20020aa7968e000000b005aa72c64a7dmr6039572pfk.16.1677953952759; Sat, 04 Mar 2023 10:19:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v3 12/20] target/mips: Drop tcg_temp_free from translate.c Date: Sat, 4 Mar 2023 10:18:52 -0800 Message-Id: <20230304181900.1097116-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954076633100003 Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Philippe Mathieu-Daud=C3=A9 Cc: Aurelien Jarno Cc: Jiaxun Yang Cc: Aleksandar Rikalo --- target/mips/tcg/translate.c | 537 +----------------------------------- 1 file changed, 14 insertions(+), 523 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 8cad3d15a0..0f27ca6149 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1274,11 +1274,8 @@ static inline void gen_load_srsgpr(int from, int to) tcg_gen_add_ptr(addr, cpu_env, addr); =20 tcg_gen_ld_tl(t0, addr, sizeof(target_ulong) * from); - tcg_temp_free_ptr(addr); - tcg_temp_free_i32(t2); } gen_store_gpr(t0, to); - tcg_temp_free(t0); } =20 static inline void gen_store_srsgpr(int from, int to) @@ -1297,9 +1294,6 @@ static inline void gen_store_srsgpr(int from, int to) tcg_gen_add_ptr(addr, cpu_env, addr); =20 tcg_gen_st_tl(t0, addr, sizeof(target_ulong) * to); - tcg_temp_free_ptr(addr); - tcg_temp_free_i32(t2); - tcg_temp_free(t0); } } =20 @@ -1396,7 +1390,6 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, i= nt reg) t64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t64, t); tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 0, 32); - tcg_temp_free_i64(t64); } =20 static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) @@ -1414,7 +1407,6 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_= i32 t, int reg) TCGv_i64 t64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t64, t); tcg_gen_deposit_i64(fpu_f64[reg], fpu_f64[reg], t64, 32, 32); - tcg_temp_free_i64(t64); } else { gen_store_fpr32(ctx, t, reg | 1); } @@ -1439,7 +1431,6 @@ void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, i= nt reg) t0 =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t0, t, 32); tcg_gen_deposit_i64(fpu_f64[reg | 1], fpu_f64[reg | 1], t0, 0, 32); - tcg_temp_free_i64(t0); } } =20 @@ -1852,8 +1843,6 @@ static inline void gen_cmp ## type ## _ ## fmt(DisasC= ontext *ctx, int n, \ default: = \ abort(); = \ } = \ - tcg_temp_free_i##bits(fp0); = \ - tcg_temp_free_i##bits(fp1); = \ } =20 FOP_CONDS(, 0, d, FMT_D, 64) @@ -1946,8 +1935,6 @@ static inline void gen_r6_cmp_ ## fmt(DisasContext *c= tx, int n, \ abort(); \ } \ STORE; \ - tcg_temp_free_i ## bits(fp0); \ - tcg_temp_free_i ## bits(fp1); \ } =20 FOP_CONDNS(d, FMT_D, 64, gen_store_fpr64(ctx, fp0, fd)) @@ -1967,7 +1954,6 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, = int mem_idx, \ tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); = \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, lladdr)); = \ tcg_gen_st_tl(ret, cpu_env, offsetof(CPUMIPSState, llval)); = \ - tcg_temp_free(t0); = \ } #else #define OP_LD_ATOMIC(insn, fname) = \ @@ -2065,9 +2051,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_gpr(t0, rt); break; case OPC_LDR: @@ -2090,15 +2074,12 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_gpr(t0, rt); break; case OPC_LDPC: t1 =3D tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TEUQ); gen_store_gpr(t0, rt); break; @@ -2106,7 +2087,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, case OPC_LWPC: t1 =3D tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, mem_idx, MO_TESL); gen_store_gpr(t0, rt); break; @@ -2170,9 +2150,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); break; @@ -2199,9 +2177,7 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); break; @@ -2214,7 +2190,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rt); break; } - tcg_temp_free(t0); } =20 /* Store */ @@ -2273,8 +2248,6 @@ static void gen_st(DisasContext *ctx, uint32_t opc, i= nt rt, gen_helper_0e2i(swr, t1, t0, mem_idx); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -2291,7 +2264,6 @@ static void gen_st_cond(DisasContext *ctx, int rt, in= t base, int offset, /* compare the address against that of the preceding LL */ gen_base_offset_addr(ctx, addr, base, offset); tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); - tcg_temp_free(addr); tcg_gen_movi_tl(t0, 0); gen_store_gpr(t0, rt); tcg_gen_br(done); @@ -2304,10 +2276,8 @@ static void gen_st_cond(DisasContext *ctx, int rt, i= nt base, int offset, eva ? MIPS_HFLAG_UM : ctx->mem_idx, tcg_mo); tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_llval); gen_store_gpr(t0, rt); - tcg_temp_free(val); =20 gen_set_label(done); - tcg_temp_free(t0); } =20 /* Load and store */ @@ -2325,7 +2295,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, ft); - tcg_temp_free_i32(fp0); } break; case OPC_SWC1: @@ -2334,7 +2303,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, gen_load_fpr32(ctx, fp0, ft); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free_i32(fp0); } break; case OPC_LDC1: @@ -2343,7 +2311,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, fp0, ft); - tcg_temp_free_i64(fp0); } break; case OPC_SDC1: @@ -2352,7 +2319,6 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t = opc, int ft, gen_load_fpr64(ctx, fp0, ft); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free_i64(fp0); } break; default: @@ -2381,7 +2347,6 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t= op, int rt, } else { generate_exception_err(ctx, EXCP_CpU, 1); } - tcg_temp_free(t0); } =20 /* Arithmetic with immediate operand */ @@ -2412,15 +2377,12 @@ static void gen_arith_imm(DisasContext *ctx, uint32= _t opc, tcg_gen_xori_tl(t1, t1, ~uimm); tcg_gen_xori_tl(t2, t0, uimm); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; case OPC_ADDIU: @@ -2445,14 +2407,11 @@ static void gen_arith_imm(DisasContext *ctx, uint32= _t opc, tcg_gen_xori_tl(t1, t1, ~uimm); tcg_gen_xori_tl(t2, t0, uimm); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rt); - tcg_temp_free(t0); } break; case OPC_DADDIU: @@ -2535,7 +2494,6 @@ static void gen_slt_imm(DisasContext *ctx, uint32_t o= pc, tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); break; } - tcg_temp_free(t0); } =20 /* Shifts with immediate operand */ @@ -2575,7 +2533,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t= opc, tcg_gen_trunc_tl_i32(t1, t0); tcg_gen_rotri_i32(t1, t1, uimm); tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); - tcg_temp_free_i32(t1); } else { tcg_gen_ext32s_tl(cpu_gpr[rt], t0); } @@ -2611,7 +2568,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t= opc, break; #endif } - tcg_temp_free(t0); } =20 /* Arithmetic */ @@ -2642,14 +2598,11 @@ static void gen_arith(DisasContext *ctx, uint32_t o= pc, tcg_gen_xor_tl(t1, t1, t2); tcg_gen_xor_tl(t2, t0, t2); tcg_gen_andc_tl(t1, t2, t1); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_ADDU: @@ -2678,9 +2631,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t2, t1, t2); tcg_gen_xor_tl(t1, t0, t1); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* * operands of different sign, first operand and the result * of different sign @@ -2688,7 +2639,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_SUBU: @@ -2718,14 +2668,11 @@ static void gen_arith(DisasContext *ctx, uint32_t o= pc, tcg_gen_xor_tl(t1, t1, t2); tcg_gen_xor_tl(t2, t0, t2); tcg_gen_andc_tl(t1, t2, t1); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* operands of same sign, result different sign */ generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_DADDU: @@ -2752,9 +2699,7 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, tcg_gen_xor_tl(t2, t1, t2); tcg_gen_xor_tl(t1, t0, t1); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); - tcg_temp_free(t1); /* * Operands of different sign, first operand and result differ= ent * sign. @@ -2762,7 +2707,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(l1); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; case OPC_DSUBU: @@ -2818,9 +2762,6 @@ static void gen_cond_move(DisasContext *ctx, uint32_t= opc, tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); break; } - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); } =20 /* Logic */ @@ -2899,8 +2840,6 @@ static void gen_slt(DisasContext *ctx, uint32_t opc, tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); break; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* Shifts */ @@ -2947,8 +2886,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_gen_andi_i32(t2, t2, 0x1f); tcg_gen_rotr_i32(t2, t3, t2); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -2970,8 +2907,6 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* Arithmetic on HI/LO registers */ @@ -3044,7 +2979,6 @@ static inline void gen_r6_ld(target_long addr, int re= g, int memidx, TCGv t0 =3D tcg_const_tl(addr); tcg_gen_qemu_ld_tl(t0, t0, memidx, memop); gen_store_gpr(t0, reg); - tcg_temp_free(t0); } =20 static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, @@ -3141,8 +3075,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MOD: @@ -3160,8 +3092,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DIVU: @@ -3173,8 +3103,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MODU: @@ -3186,8 +3114,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_MUL: @@ -3198,8 +3124,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mul_i32(t2, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MUH: @@ -3210,8 +3134,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MULU: @@ -3222,8 +3144,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mul_i32(t2, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case R6_OPC_MUHU: @@ -3234,8 +3154,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_trunc_tl_i32(t3, t1); tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_gpr[rd], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -3251,8 +3169,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movi_tl(t3, 0); tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMOD: @@ -3267,8 +3183,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) tcg_gen_movi_tl(t3, 0); tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DDIVU: @@ -3277,8 +3191,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) TCGv t3 =3D tcg_const_tl(1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_i64(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMODU: @@ -3287,8 +3199,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) TCGv t3 =3D tcg_const_tl(1); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_remu_i64(cpu_gpr[rd], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case R6_OPC_DMUL: @@ -3298,7 +3208,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc,= int rd, int rs, int rt) { TCGv t2 =3D tcg_temp_new(); tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); } break; case R6_OPC_DMULU: @@ -3308,18 +3217,14 @@ static void gen_r6_muldiv(DisasContext *ctx, int op= c, int rd, int rs, int rt) { TCGv t2 =3D tcg_temp_new(); tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); } break; #endif default: MIPS_INVAL("r6 mul/div"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 #if defined(TARGET_MIPS64) @@ -3351,8 +3256,6 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t= opc, int rs, int rt) tcg_gen_rem_tl(cpu_HI[1], t0, t1); tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case MMI_OPC_DIVU1: @@ -3366,18 +3269,13 @@ static void gen_div1_tx79(DisasContext *ctx, uint32= _t opc, int rs, int rt) tcg_gen_remu_tl(cpu_HI[1], t0, t1); tcg_gen_ext32s_tl(cpu_LO[1], cpu_LO[1]); tcg_gen_ext32s_tl(cpu_HI[1], cpu_HI[1]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; default: MIPS_INVAL("div1 TX79"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } #endif =20 @@ -3414,8 +3312,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_rem_tl(cpu_HI[acc], t0, t1); tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DIVU: @@ -3429,8 +3325,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_remu_tl(cpu_HI[acc], t0, t1); tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]); tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_MULT: @@ -3442,8 +3336,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_muls2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case OPC_MULTU: @@ -3455,8 +3347,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_mulu2_i32(t2, t3, t2, t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; #if defined(TARGET_MIPS64) @@ -3473,8 +3363,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_LO[acc], t0, t1); tcg_gen_rem_tl(cpu_HI[acc], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DDIVU: @@ -3484,8 +3372,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t op= c, tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_i64(cpu_LO[acc], t0, t1); tcg_gen_remu_i64(cpu_HI[acc], t0, t1); - tcg_temp_free(t3); - tcg_temp_free(t2); } break; case OPC_DMULT: @@ -3505,10 +3391,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t o= pc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MADDU: @@ -3523,10 +3407,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t o= pc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MSUB: @@ -3539,10 +3421,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t o= pc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; case OPC_MSUBU: @@ -3557,20 +3437,15 @@ static void gen_muldiv(DisasContext *ctx, uint32_t = opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); - tcg_temp_free_i64(t2); } break; default: MIPS_INVAL("mul/div"); gen_reserved_instruction(ctx); - goto out; + break; } - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* @@ -3625,8 +3500,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, } tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case MMI_OPC_MULTU1: @@ -3644,8 +3517,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, } tcg_gen_ext_i32_tl(cpu_LO[acc], t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); } break; case MMI_OPC_MADD1: @@ -3661,13 +3532,11 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_= t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); if (rd) { gen_move_low32(cpu_gpr[rd], t2); } - tcg_temp_free_i64(t2); } break; case MMI_OPC_MADDU1: @@ -3685,24 +3554,18 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_= t opc, tcg_gen_mul_i64(t2, t2, t3); tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); - tcg_temp_free_i64(t3); gen_move_low32(cpu_LO[acc], t2); gen_move_high32(cpu_HI[acc], t2); if (rd) { gen_move_low32(cpu_gpr[rd], t2); } - tcg_temp_free_i64(t2); } break; default: MIPS_INVAL("mul/madd TXx9"); gen_reserved_instruction(ctx); - goto out; + break; } - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_cl(DisasContext *ctx, uint32_t opc, @@ -3924,9 +3787,6 @@ static void gen_loongson_integer(DisasContext *ctx, u= int32_t opc, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 /* Loongson multimedia instructions */ @@ -4221,7 +4081,6 @@ static void gen_loongson_multimedia(DisasContext *ctx= , int rd, int rs, int rt) tcg_gen_xor_i64(t1, t1, t2); tcg_gen_xor_i64(t2, t2, t0); tcg_gen_andc_i64(t1, t2, t1); - tcg_temp_free_i64(t2); tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); @@ -4242,7 +4101,6 @@ static void gen_loongson_multimedia(DisasContext *ctx= , int rd, int rs, int rt) tcg_gen_xor_i64(t1, t1, t2); tcg_gen_xor_i64(t2, t2, t0); tcg_gen_and_i64(t1, t1, t2); - tcg_temp_free_i64(t2); tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); @@ -4284,12 +4142,8 @@ static void gen_loongson_multimedia(DisasContext *ct= x, int rd, int rs, int rt) tcg_gen_extrl_i64_i32(t32, t64); tcg_gen_deposit_i32(fpu_fcr31, fpu_fcr31, t32, get_fp_bit(cc), 1); - - tcg_temp_free_i32(t32); - tcg_temp_free_i64(t64); } - goto no_rd; - break; + return; default: MIPS_INVAL("loongson_cp2"); gen_reserved_instruction(ctx); @@ -4297,10 +4151,6 @@ static void gen_loongson_multimedia(DisasContext *ct= x, int rd, int rs, int rt) } =20 gen_store_fpr64(ctx, t0, rd); - -no_rd: - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static void gen_loongson_lswc2(DisasContext *ctx, int rt, @@ -4328,7 +4178,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, ctx->default_tcg_memop_mask); gen_store_gpr(t1, rt); gen_store_gpr(t0, lsq_rt1); - tcg_temp_free(t1); break; case OPC_GSLQC1: check_cp1_enabled(ctx); @@ -4341,7 +4190,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, ctx->default_tcg_memop_mask); gen_store_fpr64(ctx, t1, rt); gen_store_fpr64(ctx, t0, lsq_rt1); - tcg_temp_free(t1); break; case OPC_GSSQ: t1 =3D tcg_temp_new(); @@ -4353,7 +4201,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_gpr(t1, lsq_rt1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; case OPC_GSSQC1: check_cp1_enabled(ctx); @@ -4366,7 +4213,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr64(ctx, t1, lsq_rt1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif case OPC_GSSHFL: @@ -4390,16 +4236,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); #if defined(TARGET_MIPS64) tcg_gen_extrl_i64_i32(fp0, t0); #else tcg_gen_ext32s_tl(fp0, t0); #endif gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; case OPC_GSLWRC1: check_cp1_enabled(ctx); @@ -4421,16 +4264,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); #if defined(TARGET_MIPS64) tcg_gen_extrl_i64_i32(fp0, t0); #else tcg_gen_ext32s_tl(fp0, t0); #endif gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSLDLC1: @@ -4450,9 +4290,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, tcg_gen_shl_tl(t2, t2, t1); gen_load_fpr64(ctx, t1, rt); tcg_gen_andc_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_fpr64(ctx, t0, rt); break; case OPC_GSLDRC1: @@ -4473,9 +4311,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, tcg_gen_shl_tl(t2, t2, t1); gen_load_fpr64(ctx, t1, rt); tcg_gen_and_tl(t1, t1, t2); - tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t1); gen_store_fpr64(ctx, t0, rt); break; #endif @@ -4495,8 +4331,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); - tcg_temp_free_i32(fp0); - tcg_temp_free(t1); break; case OPC_GSSWRC1: check_cp1_enabled(ctx); @@ -4506,8 +4340,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t1, fp0); gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); - tcg_temp_free_i32(fp0); - tcg_temp_free(t1); break; #if defined(TARGET_MIPS64) case OPC_GSSDLC1: @@ -4516,7 +4348,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_load_fpr64(ctx, t1, rt); gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); - tcg_temp_free(t1); break; case OPC_GSSDRC1: check_cp1_enabled(ctx); @@ -4524,7 +4355,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_base_offset_addr(ctx, t0, rs, shf_offset); gen_load_fpr64(ctx, t1, rt); gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); - tcg_temp_free(t1); break; #endif default: @@ -4538,7 +4368,6 @@ static void gen_loongson_lswc2(DisasContext *ctx, int= rt, gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } =20 /* Loongson EXT LDC2/SDC2 */ @@ -4633,7 +4462,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, tcg_gen_qemu_ld_i32(fp0, t0, ctx->mem_idx, MO_TESL | ctx->default_tcg_memop_mask); gen_store_fpr32(ctx, fp0, rt); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSLDXC1: @@ -4650,21 +4478,18 @@ static void gen_loongson_lsdc2(DisasContext *ctx, i= nt rt, t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_SB); - tcg_temp_free(t1); break; case OPC_GSSHX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; case OPC_GSSWX: t1 =3D tcg_temp_new(); gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #if defined(TARGET_MIPS64) case OPC_GSSDX: @@ -4672,7 +4497,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_load_gpr(t1, rt); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif case OPC_GSSWXC1: @@ -4680,7 +4504,6 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int= rt, gen_load_fpr32(ctx, fp0, rt); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - tcg_temp_free_i32(fp0); break; #if defined(TARGET_MIPS64) case OPC_GSSDXC1: @@ -4688,14 +4511,11 @@ static void gen_loongson_lsdc2(DisasContext *ctx, i= nt rt, gen_load_fpr64(ctx, t1, rt); tcg_gen_qemu_st_i64(t1, t0, ctx->mem_idx, MO_TEUQ | ctx->default_tcg_memop_mask); - tcg_temp_free(t1); break; #endif default: break; } - - tcg_temp_free(t0); } =20 /* Traps */ @@ -4805,8 +4625,6 @@ static void gen_trap(DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_TRAP); gen_set_label(l1); } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) @@ -5072,8 +4890,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, if (insn_bytes =3D=3D 2) { ctx->hflags |=3D MIPS_HFLAG_B16; } - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 =20 @@ -5142,13 +4958,9 @@ static void gen_bitops(DisasContext *ctx, uint32_t o= pc, int rt, fail: MIPS_INVAL("bitops"); gen_reserved_instruction(ctx); - tcg_temp_free(t0); - tcg_temp_free(t1); return; } gen_store_gpr(t0, rt); - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd) @@ -5173,8 +4985,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2= , int rt, int rd) tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); tcg_gen_or_tl(t0, t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); } break; @@ -5195,8 +5005,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2= , int rt, int rd) tcg_gen_and_tl(t0, t0, t2); tcg_gen_shli_tl(t0, t0, 8); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); } break; case OPC_DSHD: @@ -5212,18 +5020,14 @@ static void gen_bshfl(DisasContext *ctx, uint32_t o= p2, int rt, int rd) tcg_gen_shri_tl(t1, t0, 32); tcg_gen_shli_tl(t0, t0, 32); tcg_gen_or_tl(cpu_gpr[rd], t0, t1); - tcg_temp_free(t2); - tcg_temp_free(t1); } break; #endif default: MIPS_INVAL("bsfhl"); gen_reserved_instruction(ctx); - tcg_temp_free(t0); return; } - tcg_temp_free(t0); } =20 static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs, @@ -5262,7 +5066,6 @@ static void gen_align_bits(DisasContext *ctx, int wor= dsz, int rd, int rs, tcg_gen_concat_tl_i64(t2, t1, t0); tcg_gen_shri_i64(t2, t2, 32 - bits); gen_move_low32(cpu_gpr[rd], t2); - tcg_temp_free_i64(t2); } break; #if defined(TARGET_MIPS64) @@ -5273,10 +5076,7 @@ static void gen_align_bits(DisasContext *ctx, int wo= rdsz, int rd, int rs, break; #endif } - tcg_temp_free(t1); } - - tcg_temp_free(t0); } =20 void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt, int = bp) @@ -5303,7 +5103,6 @@ static void gen_bitswap(DisasContext *ctx, int opc, i= nt rd, int rt) break; #endif } - tcg_temp_free(t0); } =20 #ifndef CONFIG_USER_ONLY @@ -5321,8 +5120,6 @@ static inline void gen_mthc0_entrylo(TCGv arg, target= _ulong off) tcg_gen_concat32_i64(t1, t1, t0); #endif tcg_gen_st_i64(t1, cpu_env, off); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t0); } =20 static inline void gen_mthc0_store64(TCGv arg, target_ulong off) @@ -5334,8 +5131,6 @@ static inline void gen_mthc0_store64(TCGv arg, target= _ulong off) tcg_gen_ld_i64(t1, cpu_env, off); tcg_gen_concat32_i64(t1, t1, t0); tcg_gen_st_i64(t1, cpu_env, off); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t0); } =20 static inline void gen_mfhc0_entrylo(TCGv arg, target_ulong off) @@ -5349,7 +5144,6 @@ static inline void gen_mfhc0_entrylo(TCGv arg, target= _ulong off) tcg_gen_shri_i64(t0, t0, 32); #endif gen_move_low32(arg, t0); - tcg_temp_free_i64(t0); } =20 static inline void gen_mfhc0_load64(TCGv arg, target_ulong off, int shift) @@ -5359,7 +5153,6 @@ static inline void gen_mfhc0_load64(TCGv arg, target_= ulong off, int shift) tcg_gen_ld_i64(t0, cpu_env, off); tcg_gen_shri_i64(t0, t0, 32 + shift); gen_move_low32(arg, t0); - tcg_temp_free_i64(t0); } =20 static inline void gen_mfc0_load32(TCGv arg, target_ulong off) @@ -5368,7 +5161,6 @@ static inline void gen_mfc0_load32(TCGv arg, target_u= long off) =20 tcg_gen_ld_i32(t0, cpu_env, off); tcg_gen_ext_i32_tl(arg, t0); - tcg_temp_free_i32(t0); } =20 static inline void gen_mfc0_load64(TCGv arg, target_ulong off) @@ -5383,7 +5175,6 @@ static inline void gen_mtc0_store32(TCGv arg, target_= ulong off) =20 tcg_gen_trunc_tl_i32(t0, arg); tcg_gen_st_i32(t0, cpu_env, off); - tcg_temp_free_i32(t0); } =20 #define CP0_CHECK(c) \ @@ -5705,7 +5496,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) } #endif gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name =3D "EntryLo0"; break; @@ -5763,7 +5553,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) } #endif gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name =3D "EntryLo1"; break; @@ -6292,7 +6081,6 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int= reg, int sel) TCGv_i64 tmp =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_Ta= gLo)); gen_move_low32(arg, tmp); - tcg_temp_free_i64(tmp); } register_name =3D "TagLo"; break; @@ -8813,13 +8601,11 @@ static void gen_mftr(CPUMIPSState *env, DisasContex= t *ctx, int rt, int rd, =20 gen_load_fpr32(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 gen_load_fpr32h(ctx, fp0, rt); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } break; case 3: @@ -8836,11 +8622,9 @@ static void gen_mftr(CPUMIPSState *env, DisasContext= *ctx, int rt, int rd, } trace_mips_translate_tr("mftr", rt, u, sel, h); gen_store_gpr(t0, rd); - tcg_temp_free(t0); return; =20 die: - tcg_temp_free(t0); LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); gen_reserved_instruction(ctx); } @@ -9017,13 +8801,11 @@ static void gen_mttr(CPUMIPSState *env, DisasContex= t *ctx, int rd, int rt, =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, rd); - tcg_temp_free_i32(fp0); } else { TCGv_i32 fp0 =3D tcg_temp_new_i32(); =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32h(ctx, fp0, rd); - tcg_temp_free_i32(fp0); } break; case 3: @@ -9041,11 +8823,9 @@ static void gen_mttr(CPUMIPSState *env, DisasContext= *ctx, int rd, int rt, } } trace_mips_translate_tr("mttr", rd, u, sel, h); - tcg_temp_free(t0); return; =20 die: - tcg_temp_free(t0); LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); gen_reserved_instruction(ctx); } @@ -9071,7 +8851,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, =20 gen_load_gpr(t0, rt); gen_mtc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn =3D "mtc0"; break; @@ -9092,7 +8871,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, =20 gen_load_gpr(t0, rt); gen_dmtc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn =3D "dmtc0"; break; @@ -9112,7 +8890,6 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *= ctx, uint32_t opc, TCGv t0 =3D tcg_temp_new(); gen_load_gpr(t0, rt); gen_mthc0(ctx, t0, rd, ctx->opcode & 0x7); - tcg_temp_free(t0); } opn =3D "mthc0"; break; @@ -9246,7 +9023,7 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, =20 if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK= )) { gen_reserved_instruction(ctx); - goto out; + return; } =20 if (cc !=3D 0) { @@ -9286,7 +9063,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); tcg_gen_nand_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9297,7 +9073,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 1)); tcg_gen_or_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9312,7 +9087,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_and_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); tcg_gen_nand_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9327,7 +9101,6 @@ static void gen_compute_branch1(DisasContext *ctx, ui= nt32_t op, tcg_gen_or_i32(t0, t0, t1); tcg_gen_shri_i32(t1, fpu_fcr31, get_fp_bit(cc + 3)); tcg_gen_or_i32(t0, t0, t1); - tcg_temp_free_i32(t1); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } @@ -9337,12 +9110,10 @@ static void gen_compute_branch1(DisasContext *ctx, = uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } ctx->btarget =3D btarget; ctx->hflags |=3D MIPS_HFLAG_BDS32; - out: - tcg_temp_free_i32(t0); } =20 /* R6 CP1 Branches */ @@ -9359,7 +9130,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); - goto out; + return; } =20 gen_load_fpr64(ctx, t0, ft); @@ -9379,7 +9150,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, default: MIPS_INVAL("cp1 cond branch"); gen_reserved_instruction(ctx); - goto out; + return; } =20 tcg_gen_trunc_i64_tl(bcond, t0); @@ -9394,9 +9165,6 @@ static void gen_compute_branch1_r6(DisasContext *ctx,= uint32_t op, ctx->hflags |=3D MIPS_HFLAG_BDS32; break; } - -out: - tcg_temp_free_i64(t0); } =20 /* Coprocessor 1 (FPU) */ @@ -9624,7 +9392,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, = int rt, int fs) =20 gen_load_fpr32(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); break; @@ -9635,7 +9402,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, = int rt, int fs) =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fs); - tcg_temp_free_i32(fp0); } break; case OPC_CFC1: @@ -9665,7 +9431,6 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, = int rt, int fs) =20 gen_load_fpr32h(ctx, fp0, fs); tcg_gen_ext_i32_tl(t0, fp0); - tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); break; @@ -9676,17 +9441,13 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc= , int rt, int fs) =20 tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32h(ctx, fp0, fs); - tcg_temp_free_i32(fp0); } break; default: MIPS_INVAL("cp1 move"); gen_reserved_instruction(ctx); - goto out; + return; } - - out: - tcg_temp_free(t0); } =20 static void gen_movci(DisasContext *ctx, int rd, int rs, int cc, int tf) @@ -9710,7 +9471,6 @@ static void gen_movci(DisasContext *ctx, int rd, int = rs, int cc, int tf) t0 =3D tcg_temp_new_i32(); tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - tcg_temp_free_i32(t0); gen_load_gpr(cpu_gpr[rd], rs); gen_set_label(l1); } @@ -9733,7 +9493,6 @@ static inline void gen_movcf_s(DisasContext *ctx, int= fs, int fd, int cc, gen_load_fpr32(ctx, t0, fs); gen_store_fpr32(ctx, t0, fd); gen_set_label(l1); - tcg_temp_free_i32(t0); } =20 static inline void gen_movcf_d(DisasContext *ctx, int fs, int fd, int cc, @@ -9752,11 +9511,9 @@ static inline void gen_movcf_d(DisasContext *ctx, in= t fs, int fd, int cc, =20 tcg_gen_andi_i32(t0, fpu_fcr31, 1 << get_fp_bit(cc)); tcg_gen_brcondi_i32(cond, t0, 0, l1); - tcg_temp_free_i32(t0); fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } =20 @@ -9784,7 +9541,6 @@ static inline void gen_movcf_ps(DisasContext *ctx, in= t fs, int fd, tcg_gen_brcondi_i32(cond, t0, 0, l2); gen_load_fpr32h(ctx, t0, fs); gen_store_fpr32h(ctx, t0, fd); - tcg_temp_free_i32(t0); gen_set_label(l2); } =20 @@ -9819,10 +9575,6 @@ static void gen_sel_s(DisasContext *ctx, enum fopcod= e op1, int fd, int ft, } =20 gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(t1); } =20 static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, @@ -9856,10 +9608,6 @@ static void gen_sel_d(DisasContext *ctx, enum fopcod= e op1, int fd, int ft, } =20 gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(t1); } =20 static void gen_farith(DisasContext *ctx, enum fopcode op1, @@ -9875,9 +9623,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_add_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SUB_S: @@ -9888,9 +9634,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_sub_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MUL_S: @@ -9901,9 +9645,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_mul_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_DIV_S: @@ -9914,9 +9656,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_div_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SQRT_S: @@ -9926,7 +9666,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_sqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_ABS_S: @@ -9940,7 +9679,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_helper_float_abs_s(fp0, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MOV_S: @@ -9949,7 +9687,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, =20 gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_NEG_S: @@ -9963,7 +9700,6 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, gen_helper_float_chs_s(fp0, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_ROUND_L_S: @@ -9978,9 +9714,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, } else { gen_helper_float_round_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_TRUNC_L_S: @@ -9995,9 +9729,7 @@ static void gen_farith(DisasContext *ctx, enum fopcod= e op1, } else { gen_helper_float_trunc_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CEIL_L_S: @@ -10012,9 +9744,7 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, } else { gen_helper_float_ceil_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_FLOOR_L_S: @@ -10029,9 +9759,7 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, } else { gen_helper_float_floor_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_ROUND_W_S: @@ -10045,7 +9773,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_round_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_TRUNC_W_S: @@ -10059,7 +9786,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_trunc_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CEIL_W_S: @@ -10073,7 +9799,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_ceil_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_FLOOR_W_S: @@ -10087,7 +9812,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_helper_float_floor_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_SEL_S: @@ -10118,7 +9842,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); gen_set_label(l1); } break; @@ -10133,7 +9856,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); gen_set_label(l1); } } @@ -10145,7 +9867,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_RSQRT_S: @@ -10155,7 +9876,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MADDF_S: @@ -10169,9 +9889,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp2, fd); gen_helper_float_maddf_s(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } break; case OPC_MSUBF_S: @@ -10185,9 +9902,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp2, fd); gen_helper_float_msubf_s(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } break; case OPC_RINT_S: @@ -10197,7 +9911,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rint_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CLASS_S: @@ -10207,7 +9920,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_class_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_MIN_S: /* OPC_RECIP2_S */ @@ -10220,9 +9932,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_min_s(fp2, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RECIP2_S */ check_cp1_64bitmode(ctx); @@ -10233,9 +9942,7 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_recip2_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10249,9 +9956,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_mina_s(fp2, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RECIP1_S */ check_cp1_64bitmode(ctx); @@ -10261,7 +9965,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_recip1_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10274,8 +9977,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_max_s(fp1, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RSQRT1_S */ check_cp1_64bitmode(ctx); @@ -10285,7 +9986,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_rsqrt1_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10298,8 +9998,6 @@ static void gen_farith(DisasContext *ctx, enum fopco= de op1, gen_load_fpr32(ctx, fp1, ft); gen_helper_float_maxa_s(fp1, cpu_env, fp0, fp1); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp1); - tcg_temp_free_i32(fp0); } else { /* OPC_RSQRT2_S */ check_cp1_64bitmode(ctx); @@ -10310,9 +10008,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp0, fs); gen_load_fpr32(ctx, fp1, ft); gen_helper_float_rsqrt2_s(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } } break; @@ -10324,9 +10020,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_s(fp64, cpu_env, fp32); - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_W_S: @@ -10340,7 +10034,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_cvt_w_s(fp0, cpu_env, fp0); } gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_L_S: @@ -10355,9 +10048,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_cvt_l_s(fp64, cpu_env, fp32); } - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_PS_S: @@ -10370,10 +10061,7 @@ static void gen_farith(DisasContext *ctx, enum fop= code op1, gen_load_fpr32(ctx, fp32_0, fs); gen_load_fpr32(ctx, fp32_1, ft); tcg_gen_concat_i32_i64(fp64, fp32_1, fp32_0); - tcg_temp_free_i32(fp32_1); - tcg_temp_free_i32(fp32_0); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CMP_F_S: @@ -10408,9 +10096,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_add_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SUB_D: @@ -10422,9 +10108,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_sub_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MUL_D: @@ -10436,9 +10120,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mul_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_DIV_D: @@ -10450,9 +10132,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_div_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SQRT_D: @@ -10463,7 +10143,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_sqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ABS_D: @@ -10478,7 +10157,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_abs_d(fp0, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOV_D: @@ -10488,7 +10166,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_NEG_D: @@ -10503,7 +10180,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_chs_d(fp0, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ROUND_L_D: @@ -10518,7 +10194,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_round_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_TRUNC_L_D: @@ -10533,7 +10208,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_trunc_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CEIL_L_D: @@ -10548,7 +10222,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_ceil_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_FLOOR_L_D: @@ -10563,7 +10236,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_floor_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ROUND_W_D: @@ -10578,9 +10250,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_round_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_TRUNC_W_D: @@ -10595,9 +10265,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_trunc_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CEIL_W_D: @@ -10612,9 +10280,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_ceil_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_FLOOR_W_D: @@ -10629,9 +10295,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_floor_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_SEL_D: @@ -10662,7 +10326,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } break; @@ -10677,7 +10340,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } } @@ -10690,7 +10352,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT_D: @@ -10701,7 +10362,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MADDF_D: @@ -10715,9 +10375,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp2, fd); gen_helper_float_maddf_d(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } break; case OPC_MSUBF_D: @@ -10731,9 +10388,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp2, fd); gen_helper_float_msubf_d(fp2, cpu_env, fp0, fp1, fp2); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } break; case OPC_RINT_D: @@ -10743,7 +10397,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rint_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CLASS_D: @@ -10753,7 +10406,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_class_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MIN_D: /* OPC_RECIP2_D */ @@ -10765,8 +10417,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_min_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RECIP2_D */ check_cp1_64bitmode(ctx); @@ -10777,9 +10427,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_recip2_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10792,8 +10440,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mina_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RECIP1_D */ check_cp1_64bitmode(ctx); @@ -10803,7 +10449,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10816,8 +10461,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_max_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RSQRT1_D */ check_cp1_64bitmode(ctx); @@ -10827,7 +10470,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt1_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10840,8 +10482,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp1, ft); gen_helper_float_maxa_d(fp1, cpu_env, fp0, fp1); gen_store_fpr64(ctx, fp1, fd); - tcg_temp_free_i64(fp1); - tcg_temp_free_i64(fp0); } else { /* OPC_RSQRT2_D */ check_cp1_64bitmode(ctx); @@ -10852,9 +10492,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_rsqrt2_d(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } } break; @@ -10889,9 +10527,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_d(fp32, cpu_env, fp64); - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_W_D: @@ -10906,9 +10542,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, } else { gen_helper_float_cvt_w_d(fp32, cpu_env, fp64); } - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_L_D: @@ -10923,7 +10557,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_helper_float_cvt_l_d(fp0, cpu_env, fp0); } gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_W: @@ -10933,7 +10566,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_w(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_D_W: @@ -10944,9 +10576,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr32(ctx, fp32, fs); gen_helper_float_cvtd_w(fp64, cpu_env, fp32); - tcg_temp_free_i32(fp32); gen_store_fpr64(ctx, fp64, fd); - tcg_temp_free_i64(fp64); } break; case OPC_CVT_S_L: @@ -10957,9 +10587,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp64, fs); gen_helper_float_cvts_l(fp32, cpu_env, fp64); - tcg_temp_free_i64(fp64); gen_store_fpr32(ctx, fp32, fd); - tcg_temp_free_i32(fp32); } break; case OPC_CVT_D_L: @@ -10970,7 +10598,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtd_l(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_PS_PW: @@ -10981,7 +10608,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtps_pw(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ADD_PS: @@ -10993,9 +10619,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_add_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SUB_PS: @@ -11007,9 +10631,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_sub_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MUL_PS: @@ -11021,9 +10643,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_mul_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_ABS_PS: @@ -11034,7 +10654,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_abs_ps(fp0, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOV_PS: @@ -11044,7 +10663,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, =20 gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_NEG_PS: @@ -11055,7 +10673,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_chs_ps(fp0, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MOVCF_PS: @@ -11074,7 +10691,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } break; @@ -11089,7 +10705,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); gen_set_label(l1); } } @@ -11103,9 +10718,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); gen_helper_float_addr_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_MULR_PS: @@ -11117,9 +10730,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, ft); gen_load_fpr64(ctx, fp1, fs); gen_helper_float_mulr_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RECIP2_PS: @@ -11131,9 +10742,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_recip2_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RECIP1_PS: @@ -11144,7 +10753,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_recip1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT1_PS: @@ -11155,7 +10763,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_rsqrt1_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_RSQRT2_PS: @@ -11167,9 +10774,7 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_helper_float_rsqrt2_ps(fp0, cpu_env, fp0, fp1); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_PU: @@ -11180,7 +10785,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32h(ctx, fp0, fs); gen_helper_float_cvts_pu(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_CVT_PW_PS: @@ -11191,7 +10795,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr64(ctx, fp0, fs); gen_helper_float_cvtpw_ps(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_CVT_S_PL: @@ -11202,7 +10805,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp0, fs); gen_helper_float_cvts_pl(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_PLL_PS: @@ -11215,8 +10817,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp1, ft); gen_store_fpr32h(ctx, fp0, fd); gen_store_fpr32(ctx, fp1, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PLU_PS: @@ -11229,8 +10829,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32h(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PUL_PS: @@ -11243,8 +10841,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_PUU_PS: @@ -11257,8 +10853,6 @@ static void gen_farith(DisasContext *ctx, enum fopc= ode op1, gen_load_fpr32h(ctx, fp1, ft); gen_store_fpr32(ctx, fp1, fd); gen_store_fpr32h(ctx, fp0, fd); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); } break; case OPC_CMP_F_PS: @@ -11316,7 +10910,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); tcg_gen_trunc_tl_i32(fp0, t0); gen_store_fpr32(ctx, fp0, fd); - tcg_temp_free_i32(fp0); } break; case OPC_LDXC1: @@ -11326,7 +10919,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, TCGv_i64 fp0 =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_LUXC1: @@ -11337,7 +10929,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, =20 tcg_gen_qemu_ld_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); gen_store_fpr64(ctx, fp0, fd); - tcg_temp_free_i64(fp0); } break; case OPC_SWXC1: @@ -11346,7 +10937,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, TCGv_i32 fp0 =3D tcg_temp_new_i32(); gen_load_fpr32(ctx, fp0, fs); tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); - tcg_temp_free_i32(fp0); } break; case OPC_SDXC1: @@ -11356,7 +10946,6 @@ static void gen_flt3_ldst(DisasContext *ctx, uint32= _t opc, TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); - tcg_temp_free_i64(fp0); } break; case OPC_SUXC1: @@ -11366,11 +10955,9 @@ static void gen_flt3_ldst(DisasContext *ctx, uint3= 2_t opc, TCGv_i64 fp0 =3D tcg_temp_new_i64(); gen_load_fpr64(ctx, fp0, fs); tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEUQ); - tcg_temp_free_i64(fp0); } break; } - tcg_temp_free(t0); } =20 static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, @@ -11397,7 +10984,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, tcg_gen_br(l2); gen_set_label(l1); tcg_gen_brcondi_tl(TCG_COND_NE, t0, 4, l2); - tcg_temp_free(t0); if (cpu_is_bigendian(ctx)) { gen_load_fpr32(ctx, fp, fs); gen_load_fpr32h(ctx, fph, ft); @@ -11410,8 +10996,6 @@ static void gen_flt3_arith(DisasContext *ctx, uint3= 2_t opc, gen_store_fpr32h(ctx, fp, fd); } gen_set_label(l2); - tcg_temp_free_i32(fp); - tcg_temp_free_i32(fph); } break; case OPC_MADD_S: @@ -11425,10 +11009,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_MADD_D: @@ -11443,10 +11024,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MADD_PS: @@ -11460,10 +11038,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MSUB_S: @@ -11477,10 +11052,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_MSUB_D: @@ -11495,10 +11067,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_MSUB_PS: @@ -11512,10 +11081,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMADD_S: @@ -11529,10 +11095,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_NMADD_D: @@ -11547,10 +11110,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMADD_PS: @@ -11564,10 +11124,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMSUB_S: @@ -11581,10 +11138,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr32(ctx, fp1, ft); gen_load_fpr32(ctx, fp2, fr); gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i32(fp0); - tcg_temp_free_i32(fp1); gen_store_fpr32(ctx, fp2, fd); - tcg_temp_free_i32(fp2); } break; case OPC_NMSUB_D: @@ -11599,10 +11153,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; case OPC_NMSUB_PS: @@ -11616,10 +11167,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint= 32_t opc, gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); - tcg_temp_free_i64(fp0); - tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); - tcg_temp_free_i64(fp2); } break; default: @@ -11708,7 +11256,6 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, i= nt sel) gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } =20 static inline void clear_branch_hflags(DisasContext *ctx) @@ -11767,11 +11314,9 @@ static void gen_branch(DisasContext *ctx, int insn= _bytes) =20 tcg_gen_andi_tl(t0, btarget, 0x1); tcg_gen_trunc_tl_i32(t1, t0); - tcg_temp_free(t0); tcg_gen_andi_i32(hflags, hflags, ~(uint32_t)MIPS_HFLAG_M16= ); tcg_gen_shli_i32(t1, t1, MIPS_HFLAG_M16_SHIFT); tcg_gen_or_i32(hflags, hflags, t1); - tcg_temp_free_i32(t1); =20 tcg_gen_andi_tl(cpu_PC, btarget, ~(target_ulong)0x1); } else { @@ -11801,7 +11346,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); - goto out; + return; } =20 /* Load needed operands and calculate btarget */ @@ -11855,13 +11400,12 @@ static void gen_compute_compact_branch(DisasConte= xt *ctx, uint32_t opc, =20 gen_load_gpr(tbase, rt); gen_op_addr_add(ctx, btarget, tbase, toffset); - tcg_temp_free(tbase); } break; default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 if (bcond_compute =3D=3D 0) { @@ -11882,7 +11426,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, default: MIPS_INVAL("Compact branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* Generating branch here as compact branches don't have delay slo= t */ @@ -11972,10 +11516,6 @@ static void gen_compute_compact_branch(DisasContex= t *ctx, uint32_t opc, /* OPC_BNVC */ tcg_gen_brcondi_tl(tcg_invert_cond(TCG_COND_EQ), t4, 0= , fs); } - tcg_temp_free(input_overflow); - tcg_temp_free(t4); - tcg_temp_free(t3); - tcg_temp_free(t2); } else if (rs < rt && rs =3D=3D 0) { /* OPC_BEQZALC, OPC_BNEZALC */ if (opc =3D=3D OPC_BEQZALC) { @@ -12005,7 +11545,7 @@ static void gen_compute_compact_branch(DisasContext= *ctx, uint32_t opc, default: MIPS_INVAL("Compact conditional branch/jump"); gen_reserved_instruction(ctx); - goto out; + return; } =20 /* Generating branch here as compact branches don't have delay slo= t */ @@ -12014,10 +11554,6 @@ static void gen_compute_compact_branch(DisasContex= t *ctx, uint32_t opc, =20 ctx->hflags |=3D MIPS_HFLAG_FBNSLOT; } - -out: - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 void gen_addiupc(DisasContext *ctx, int rx, int imm, @@ -12037,8 +11573,6 @@ void gen_addiupc(DisasContext *ctx, int rx, int imm, if (!is_64_bit) { tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); } - - tcg_temp_free(t0); } =20 static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base, @@ -12048,8 +11582,6 @@ static void gen_cache_operation(DisasContext *ctx, = uint32_t op, int base, TCGv t1 =3D tcg_temp_new(); gen_base_offset_addr(ctx, t1, base, offset); gen_helper_cache(cpu_env, t1, t0); - tcg_temp_free(t1); - tcg_temp_free_i32(t0); } =20 static inline bool is_uhi(DisasContext *ctx, int sdbbp_code) @@ -12077,9 +11609,6 @@ void gen_ldxs(DisasContext *ctx, int base, int inde= x, int rd) =20 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); gen_store_gpr(t1, rd); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_sync(int stype) @@ -12183,7 +11712,6 @@ static void gen_mips_lx(DisasContext *ctx, uint32_t= opc, break; #endif } - tcg_temp_free(t0); } =20 static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op= 2, @@ -12397,7 +11925,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, TCGv_i32 sa_t =3D tcg_const_i32(v2); gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, cpu_gpr[ret]); - tcg_temp_free_i32(sa_t); break; } case OPC_PRECR_SRA_R_PH_W: @@ -12406,7 +11933,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, TCGv_i32 sa_t =3D tcg_const_i32(v2); gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, cpu_gpr[ret]); - tcg_temp_free_i32(sa_t); break; } case OPC_PRECRQ_PH_W: @@ -12595,7 +12121,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, { TCGv_i32 ret_t =3D tcg_const_i32(ret); gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); - tcg_temp_free_i32(ret_t); break; } case OPC_PRECR_SRA_R_QH_PW: @@ -12603,7 +12128,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, { TCGv_i32 sa_v =3D tcg_const_i32(ret); gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); - tcg_temp_free_i32(sa_v); break; } case OPC_PRECRQ_OB_QH: @@ -12630,9 +12154,6 @@ static void gen_mipsdsp_arith(DisasContext *ctx, ui= nt32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, @@ -12872,10 +12393,6 @@ static void gen_mipsdsp_shift(DisasContext *ctx, u= int32_t opc, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t= op2, @@ -13182,10 +12699,6 @@ static void gen_mipsdsp_multiply(DisasContext *ctx= , uint32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free_i32(t0); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t = op2, @@ -13322,8 +12835,6 @@ static void gen_mipsdsp_bitinsn(DisasContext *ctx, = uint32_t op1, uint32_t op2, break; #endif } - tcg_temp_free(t0); - tcg_temp_free(val_t); } =20 static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, @@ -13506,10 +13017,6 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext = *ctx, break; #endif } - - tcg_temp_free(t1); - tcg_temp_free(v1_t); - tcg_temp_free(v2_t); } =20 static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, @@ -13597,7 +13104,6 @@ static void gen_mipsdsp_append(CPUMIPSState *env, D= isasContext *ctx, break; #endif } - tcg_temp_free(t0); } =20 static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t = op2, @@ -13814,10 +13320,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx,= uint32_t op1, uint32_t op2, break; #endif } - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(v1_t); } =20 /* End MIPSDSP functions. */ @@ -14668,9 +14170,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) gen_load_gpr(t1, rs); =20 gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); break; } default: /* Invalid */ @@ -14940,9 +14439,6 @@ static void decode_opc_special3_legacy(CPUMIPSState= *env, DisasContext *ctx) gen_load_gpr(t1, rs); =20 gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); break; } default: /* Invalid */ @@ -15169,8 +14665,6 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) gen_load_gpr(t0, rt); gen_load_gpr(t1, rs); gen_helper_fork(t0, t1); - tcg_temp_free(t0); - tcg_temp_free(t1); } break; case OPC_YIELD: @@ -15181,7 +14675,6 @@ static void decode_opc_special3(CPUMIPSState *env, = DisasContext *ctx) gen_load_gpr(t0, rs); gen_helper_yield(t0, cpu_env, t0); gen_store_gpr(t0, rd); - tcg_temp_free(t0); } break; default: @@ -15424,7 +14917,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) gen_reserved_instruction(ctx); break; } - tcg_temp_free(t0); } #endif /* !CONFIG_USER_ONLY */ break; @@ -15872,7 +15364,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, Di= sasContext *ctx) TCGv t0 =3D tcg_temp_new(); gen_load_gpr(t0, rs); tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); - tcg_temp_free(t0); } #else gen_reserved_instruction(ctx); --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lgBa2ERsQgrO6e/WAUiGru/VeOh/EJOtLRcCdLzGBVc=; b=otqBSvPmnfdKY1Iz7U7v6MdYMw6A/SMC2fGUMiKJjVjPqeBwhWn01MdLYX/zObBP93 NED2qpgY8iamd5WaVOU6ZvUVGJ5r/j1iUKgH5vduajU2Bfggo5FXcJg8T/q8QDDsyL+K m/oBBCp0XhUu4CoCvE1uqKVyxVQGmvzyhnSPlR8ODw/3+/mQy1zowlWkaEPe8Rs1QMj3 9oqhQ1WNRVi9+eOEqPsbnwCpFQaLqiQIRyjrGVxWUv96bCHH8o/2SYf9dLL4ilyjM1Up B1SsyrocG3HOrfEPXqmCEOetMZpeL/UTLIoq9wYVtMkYLZyB3Md9dJsMmz514+AfZnWO Cc/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lgBa2ERsQgrO6e/WAUiGru/VeOh/EJOtLRcCdLzGBVc=; b=bi+aUOgTTkQe5X9vAp2JrRarJjDCO8pBfM2HipTexsEWCx+3q1StQek8z1/TfkWHoq 5Yd9JWkLPv7soMVwYHJkoPFb/+bXdV/s40l31Axpybddo9fqTELIft6GXJmrF3G3A+nc qQs54YjMJTLV5oKUbxtqOQ2v+h+QjyZ1ImlskiWDfJ688+QqjJAnNqgKXEPBhngbG/TN G8jwCKbUeogpXrvPyFNwQtvr6eupptiwJHw/1rG3Xyri5kDvUrVSZoYmqr6KTmzTAOK9 nwHNBMv5lkEabTHgnyHZ2FTnlFIeZixdAQp1AR0+5IvqxpMYqHQOHZySH5612gw5+tEa gl3g== X-Gm-Message-State: AO0yUKVY3hvvbj3UAfws+hjHdlUUnrcUbLgHj3XRDz1vbz+g33ofv5ez qv8Or0n/v0+RiIxR7ocDR7t3UO63clu/ur8BcesECA== X-Google-Smtp-Source: AK7set/MmyPOQ8CJO2gpyDOrFPDBmG7lqsLcPSbQ5hTN8gUu9evM07LCzbsB4EXBZeWrhX7b5srXMA== X-Received: by 2002:a05:6a21:3284:b0:cd:1709:8d57 with SMTP id yt4-20020a056a21328400b000cd17098d57mr7377037pzb.1.1677953953593; Sat, 04 Mar 2023 10:19:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-s390x@nongnu.org Subject: [PATCH v3 13/20] target/s390x: Drop free_compare Date: Sat, 4 Mar 2023 10:18:53 -0800 Message-Id: <20230304181900.1097116-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954001511100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Remove the g1 and g2 members of DisasCompare, as they were used to track which temps needed to be freed. Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: David Hildenbrand Cc: Ilya Leoshkevich Cc: Thomas Huth Cc: qemu-s390x@nongnu.org --- target/s390x/tcg/translate.c | 46 +----------------------------------- 1 file changed, 1 insertion(+), 45 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 811049ea28..76a1233946 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -156,8 +156,6 @@ struct DisasContext { typedef struct { TCGCond cond:8; bool is_64; - bool g1; - bool g2; union { struct { TCGv_i64 a, b; } s64; struct { TCGv_i32 a, b; } s32; @@ -722,7 +720,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) c->cond =3D (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER); c->u.s32.a =3D cc_op; c->u.s32.b =3D cc_op; - c->g1 =3D c->g2 =3D true; c->is_64 =3D false; return; } @@ -839,7 +836,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) =20 /* Load up the arguments of the comparison. */ c->is_64 =3D true; - c->g1 =3D c->g2 =3D false; switch (old_cc_op) { case CC_OP_LTGT0_32: c->is_64 =3D false; @@ -861,13 +857,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) case CC_OP_FLOGR: c->u.s64.a =3D cc_dst; c->u.s64.b =3D tcg_constant_i64(0); - c->g1 =3D true; break; case CC_OP_LTGT_64: case CC_OP_LTUGTU_64: c->u.s64.a =3D cc_src; c->u.s64.b =3D cc_dst; - c->g1 =3D c->g2 =3D true; break; =20 case CC_OP_TM_32: @@ -882,7 +876,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_SUBU: c->is_64 =3D true; c->u.s64.b =3D tcg_constant_i64(0); - c->g1 =3D true; switch (mask) { case 8 | 2: case 4 | 1: /* result */ @@ -900,7 +893,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_STATIC: c->is_64 =3D false; c->u.s32.a =3D cc_op; - c->g1 =3D true; switch (mask) { case 0x8 | 0x4 | 0x2: /* cc !=3D 3 */ cond =3D TCG_COND_NE; @@ -916,7 +908,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case 0x8 | 0x2: /* cc =3D=3D 0 || cc =3D=3D 2 =3D> (cc & 1) =3D=3D= 0 */ cond =3D TCG_COND_EQ; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -935,7 +926,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case 0x4 | 0x1: /* cc =3D=3D 1 || cc =3D=3D 3 =3D> (cc & 1) !=3D 0= */ cond =3D TCG_COND_NE; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -959,7 +949,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) default: /* CC is masked by something else: (8 >> cc) & mask. */ cond =3D TCG_COND_NE; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); @@ -974,24 +963,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c= , uint32_t mask) c->cond =3D cond; } =20 -static void free_compare(DisasCompare *c) -{ - if (!c->g1) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.a); - } else { - tcg_temp_free_i32(c->u.s32.a); - } - } - if (!c->g2) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.b); - } else { - tcg_temp_free_i32(c->u.s32.b); - } - } -} - /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ /* Define the insn format enumeration. */ #define F0(N) FMT_##N, @@ -1302,7 +1273,6 @@ static DisasJumpType help_branch(DisasContext *s, Dis= asCompare *c, } =20 egress: - free_compare(c); return ret; } =20 @@ -1612,8 +1582,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasO= ps *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_subi_i64(t, regs[r1], 1); @@ -1635,8 +1603,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOp= s *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t, regs[r1], 32); @@ -1659,8 +1625,6 @@ static DisasJumpType op_bct64(DisasContext *s, DisasO= ps *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D true; - c.g1 =3D true; - c.g2 =3D false; =20 tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a =3D regs[r1]; @@ -1680,8 +1644,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOp= s *o) =20 c.cond =3D (s->insn->data ? TCG_COND_LE : TCG_COND_GT); c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_add_i64(t, regs[r1], regs[r3]); @@ -1708,15 +1670,12 @@ static DisasJumpType op_bx64(DisasContext *s, Disas= Ops *o) =20 if (r1 =3D=3D (r3 | 1)) { c.u.s64.b =3D load_reg(r3 | 1); - c.g2 =3D false; } else { c.u.s64.b =3D regs[r3 | 1]; - c.g2 =3D true; } =20 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]); c.u.s64.a =3D regs[r1]; - c.g1 =3D true; =20 return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1731,7 +1690,7 @@ static DisasJumpType op_cj(DisasContext *s, DisasOps = *o) if (s->insn->data) { c.cond =3D tcg_unsigned_cond(c.cond); } - c.is_64 =3D c.g1 =3D c.g2 =3D true; + c.is_64 =3D true; c.u.s64.a =3D o->in1; c.u.s64.b =3D o->in2; =20 @@ -2925,13 +2884,11 @@ static DisasJumpType op_loc(DisasContext *s, DisasO= ps *o) if (c.is_64) { tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b, o->in2, o->in1); - free_compare(&c); } else { TCGv_i32 t32 =3D tcg_temp_new_i32(); TCGv_i64 t, z; =20 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b); - free_compare(&c); =20 t =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t, t32); @@ -4022,7 +3979,6 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps= *o) } else { tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab); } - free_compare(&c); =20 r1 =3D get_field(s, r1); a =3D get_address(s, 0, get_field(s, b2), get_field(s, d2)); --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954120; cv=none; d=zohomail.com; s=zohoarc; b=WSG79ciLtaB+6UFkyIr/co1tu/KUnmd0qtlnyytfgRwpzQ00PgbZHgb2PoxwQg/aKifrm0xgWSMGlUnapdqVCqoDGbJdLnGhSOfVkwY14PE2IQ+aWv3oIdM0bduWec9iToAPtBOqJ21CSlC08VHH13cf4AuzWbbyljAfVd+K4aE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954120; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g36GpeUog2TtO1bEjoJZmGi00IFE+7wtku8td+fIKj8=; b=SNcKhtle9HpwboxpG4WJufxMowP0xE2vGkU6+5OvZ9SP1tjgDZDJe2sqPlT8YndTjOWjqqzJVYkRA28FNQfgtmvhyQXaFHtE2Ve7h3W1Qifi8haARNfU3Rxxfma+NlW1N7TsgOEaNx5PB3Om4jQUyOjP26ZVVICYNRdVYXkAlGw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1677954120051629.5629875652236; Sat, 4 Mar 2023 10:22:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTi-0006Wv-MO; Sat, 04 Mar 2023 13:19:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTb-0006Vh-7N for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:23 -0500 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTV-0003OQ-U4 for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:22 -0500 Received: by mail-pg1-x52b.google.com with SMTP id d6so3310158pgu.2 for ; Sat, 04 Mar 2023 10:19:15 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953954; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g36GpeUog2TtO1bEjoJZmGi00IFE+7wtku8td+fIKj8=; b=QxzcYbqrh1+kAywgNtMWpNHitMrldo9rcI5nwewef8eG0wXNVOwh0Yrl90J1r2Ykpd LA/Bi2s1yoAmKIHgiqdtSrX3R3fbsZBOD3a4BIxqky/IkbMxioAiAl4YmWGHqgivZkmM Zvh4ss1+eHc4JxHSdo3jYHtz0VcvRpOpNEGIzFl8KHN/PcMx4gS0QvWUWhOb/EbVzowN YWcmlC4nk+hg3LQ2Q5ciYU0/r+aYrXnXEXzbUFbywW38Rdq2Ij/FZKXieiQ2Rd9P0DGj tpk6XsrhjesQkkVAoQyqWUgyhWBXjodTnh2R0pHaz4zB4i0+X7D6AJzhHgaYKBX7yVHi eZbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953954; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g36GpeUog2TtO1bEjoJZmGi00IFE+7wtku8td+fIKj8=; b=vpDC9bqjVQqiM7qirq2wJ182i4PUP1QgCAL+acPytGQ3DvOzO9nA45QNSAAmdKIFAA XDwDIpNnhp9xr0biKgLJhTa6oHTZw2UPkFS++W1Km1H5viCHd8MvWjuNKZ6bDy97x2Oz +OEcQthgBSTn1MK2YloP8Ju7241979ZbUI7WwhCZvc7mfPxYypiz1L4Mqd+D4UFPRzGI f8HkTrUsW+GrhUCH3kzhB1nPPdVhyIyjtpUEzJ03Ht5s0cyxTVExkQKDwli9yTzekRyr nSmTp4ie98l5eZ0ODl04gqwvTSigLEOq8innei2iQKsOGoh0B1FOV0EjHkWyzdrnKjuY ldhw== X-Gm-Message-State: AO0yUKWfpXKWnppocFQC/Ld64Lv2tHCFxov18y/xcAmi2hMaKtDWn1JV 7mEPEYLCwDyx189XXjwAs4sUanTg3gUlz/0b31VHCA== X-Google-Smtp-Source: AK7set92d0dXhty0LV3Uap6pjxHn97S/WEjPIE5A6P+Ih/ssNP3vrsxhdlo2WFNS5f/TpeQ9DudMVQ== X-Received: by 2002:a62:5251:0:b0:619:b116:d1f5 with SMTP id g78-20020a625251000000b00619b116d1f5mr2137488pfb.7.1677953954552; Sat, 04 Mar 2023 10:19:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-s390x@nongnu.org Subject: [PATCH v3 14/20] target/s390x: Drop tcg_temp_free from translate_vx.c.inc Date: Sat, 4 Mar 2023 10:18:54 -0800 Message-Id: <20230304181900.1097116-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954120885100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: David Hildenbrand Cc: Ilya Leoshkevich Cc: Thomas Huth Cc: qemu-s390x@nongnu.org --- target/s390x/tcg/translate_vx.c.inc | 143 ---------------------------- 1 file changed, 143 deletions(-) diff --git a/target/s390x/tcg/translate_vx.c.inc b/target/s390x/tcg/transla= te_vx.c.inc index 3fadc82e5c..43dfbfd03f 100644 --- a/target/s390x/tcg/translate_vx.c.inc +++ b/target/s390x/tcg/translate_vx.c.inc @@ -183,8 +183,6 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8= _t reg, TCGv_i64 enr, /* generate the final ptr by adding cpu_env */ tcg_gen_trunc_i64_ptr(ptr, tmp); tcg_gen_add_ptr(ptr, ptr, cpu_env); - - tcg_temp_free_i64(tmp); } =20 #define gen_gvec_2(v1, v2, gen) \ @@ -272,13 +270,6 @@ static void gen_gvec128_3_i64(gen_gvec128_3_i64_fn fn,= uint8_t d, uint8_t a, fn(dl, dh, al, ah, bl, bh); write_vec_element_i64(dh, d, 0, ES_64); write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); } =20 typedef void (*gen_gvec128_4_i64_fn)(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, @@ -305,15 +296,6 @@ static void gen_gvec128_4_i64(gen_gvec128_4_i64_fn fn,= uint8_t d, uint8_t a, fn(dl, dh, al, ah, bl, bh, cl, ch); write_vec_element_i64(dh, d, 0, ES_64); write_vec_element_i64(dl, d, 1, ES_64); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(dl); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(al); - tcg_temp_free_i64(bh); - tcg_temp_free_i64(bl); - tcg_temp_free_i64(ch); - tcg_temp_free_i64(cl); } =20 static void gen_addi2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, TCGv_i64 = ah, @@ -351,7 +333,6 @@ static DisasJumpType op_vge(DisasContext *s, DisasOps *= o) =20 tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -386,7 +367,6 @@ static DisasJumpType op_vgbm(DisasContext *s, DisasOps = *o) write_vec_element_i64(t, get_field(s, v1), 0, ES_64); tcg_gen_movi_i64(t, generate_byte_mask(i2)); write_vec_element_i64(t, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t); } return DISAS_NEXT; } @@ -427,8 +407,6 @@ static DisasJumpType op_vl(DisasContext *s, DisasOps *o) tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -451,7 +429,6 @@ static DisasJumpType op_vlrep(DisasContext *s, DisasOps= *o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -469,7 +446,6 @@ static DisasJumpType op_vlebr(DisasContext *s, DisasOps= *o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -486,7 +462,6 @@ static DisasJumpType op_vlbrrep(DisasContext *s, DisasO= ps *o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); gen_gvec_dup_i64(es, get_field(s, v1), tmp); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -518,7 +493,6 @@ static DisasJumpType op_vllebrz(DisasContext *s, DisasO= ps *o) =20 write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); write_vec_element_i64(tcg_constant_i64(0), get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -572,9 +546,6 @@ static DisasJumpType op_vlbr(DisasContext *s, DisasOps = *o) write: write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -592,7 +563,6 @@ static DisasJumpType op_vle(DisasContext *s, DisasOps *= o) tmp =3D tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); write_vec_element_i64(tmp, get_field(s, v1), enr, es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -647,8 +617,6 @@ static DisasJumpType op_vler(DisasContext *s, DisasOps = *o) =20 write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -688,8 +656,6 @@ static DisasJumpType op_vlgv(DisasContext *s, DisasOps = *o) default: g_assert_not_reached(); } - tcg_temp_free_ptr(ptr); - return DISAS_NEXT; } =20 @@ -730,7 +696,6 @@ static DisasJumpType op_vllez(DisasContext *s, DisasOps= *o) tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es); gen_gvec_dup_imm(es, get_field(s, v1), 0); write_vec_element_i64(t, get_field(s, v1), enr, es); - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -768,9 +733,6 @@ static DisasJumpType op_vlm(DisasContext *s, DisasOps *= o) =20 /* Store the last element, loaded first */ write_vec_element_i64(t0, v1, 1, ES_64); - - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); return DISAS_NEXT; } =20 @@ -794,8 +756,6 @@ static DisasJumpType op_vlbb(DisasContext *s, DisasOps = *o) =20 tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vll(cpu_env, a0, o->addr1, bytes); - tcg_temp_free_i64(bytes); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } =20 @@ -835,8 +795,6 @@ static DisasJumpType op_vlvg(DisasContext *s, DisasOps = *o) default: g_assert_not_reached(); } - tcg_temp_free_ptr(ptr); - return DISAS_NEXT; } =20 @@ -856,7 +814,6 @@ static DisasJumpType op_vll(DisasContext *s, DisasOps *= o) tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vll(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } =20 @@ -898,7 +855,6 @@ static DisasJumpType op_vmr(DisasContext *s, DisasOps *= o) write_vec_element_i64(tmp, v1, dst_idx, es); } } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -974,7 +930,6 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *= o) } write_vec_element_i64(tmp, v1, dst_idx, dst_es); } - tcg_temp_free_i64(tmp); } else { gen_gvec_3_ool(v1, v2, v3, 0, vpk[es - 1]); } @@ -1004,8 +959,6 @@ static DisasJumpType op_vpdi(DisasContext *s, DisasOps= *o) read_vec_element_i64(t1, get_field(s, v3), i3, ES_64); write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); return DISAS_NEXT; } =20 @@ -1057,7 +1010,6 @@ static DisasJumpType op_vsce(DisasContext *s, DisasOp= s *o) =20 read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1098,7 +1050,6 @@ static DisasJumpType op_vseg(DisasContext *s, DisasOp= s *o) write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64); read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN); write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1116,7 +1067,6 @@ static DisasJumpType op_vst(DisasContext *s, DisasOps= *o) gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEUQ); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1134,7 +1084,6 @@ static DisasJumpType op_vstebr(DisasContext *s, Disas= Ops *o) tmp =3D tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_LE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1189,9 +1138,6 @@ write: tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_LEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_LEUQ); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -1209,7 +1155,6 @@ static DisasJumpType op_vste(DisasContext *s, DisasOp= s *o) tmp =3D tcg_temp_new_i64(); read_vec_element_i64(tmp, get_field(s, v1), enr, es); tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1251,9 +1196,6 @@ static DisasJumpType op_vster(DisasContext *s, DisasO= ps *o) tcg_gen_qemu_st_i64(t0, o->addr1, get_mem_index(s), MO_TEUQ); gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); tcg_gen_qemu_st_i64(t1, o->addr1, get_mem_index(s), MO_TEUQ); - - tcg_temp_free(t0); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -1284,7 +1226,6 @@ static DisasJumpType op_vstm(DisasContext *s, DisasOp= s *o) } gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8); } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1297,7 +1238,6 @@ static DisasJumpType op_vstl(DisasContext *s, DisasOp= s *o) tcg_gen_addi_i64(o->in2, o->in2, 1); tcg_gen_addi_ptr(a0, cpu_env, v1_offs); gen_helper_vstl(cpu_env, a0, o->addr1, o->in2); - tcg_temp_free_ptr(a0); return DISAS_NEXT; } =20 @@ -1335,7 +1275,6 @@ static DisasJumpType op_vup(DisasContext *s, DisasOps= *o) write_vec_element_i64(tmp, v1, dst_idx, dst_es); } } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -1377,10 +1316,6 @@ static void gen_acc(TCGv_i64 d, TCGv_i64 a, TCGv_i64= b, uint8_t es) /* Isolate and shift the carry into position */ tcg_gen_and_i64(d, d, msb_mask); tcg_gen_shri_i64(d, d, msb_bit_nr); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static void gen_acc8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1399,7 +1334,6 @@ static void gen_acc_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b) =20 tcg_gen_add_i32(t, a, b); tcg_gen_setcond_i32(TCG_COND_LTU, d, t, b); - tcg_temp_free_i32(t); } =20 static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) @@ -1408,7 +1342,6 @@ static void gen_acc_i64(TCGv_i64 d, TCGv_i64 a, TCGv_= i64 b) =20 tcg_gen_add_i64(t, a, b); tcg_gen_setcond_i64(TCG_COND_LTU, d, t, b); - tcg_temp_free_i64(t); } =20 static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TCGv_i64 al, @@ -1422,9 +1355,6 @@ static void gen_acc2_i64(TCGv_i64 dl, TCGv_i64 dh, TC= Gv_i64 al, tcg_gen_add2_i64(tl, th, th, zero, ah, zero); tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); } =20 static DisasJumpType op_vacc(DisasContext *s, DisasOps *o) @@ -1460,8 +1390,6 @@ static void gen_ac2_i64(TCGv_i64 dl, TCGv_i64 dh, TCG= v_i64 al, TCGv_i64 ah, tcg_gen_extract_i64(tl, cl, 0, 1); tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); tcg_gen_add2_i64(dl, dh, dl, dh, tl, zero); - - tcg_temp_free_i64(tl); } =20 static DisasJumpType op_vac(DisasContext *s, DisasOps *o) @@ -1490,9 +1418,6 @@ static void gen_accc2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, TCGv_i64 ah, tcg_gen_add2_i64(tl, th, th, zero, ah, zero); tcg_gen_add2_i64(tl, dl, tl, th, bh, zero); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } =20 static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o) @@ -1533,9 +1458,6 @@ static void gen_avg_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b) tcg_gen_addi_i64(t0, t0, 1); tcg_gen_shri_i64(t0, t0, 1); tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) @@ -1550,10 +1472,6 @@ static void gen_avg_i64(TCGv_i64 dl, TCGv_i64 al, TC= Gv_i64 bl) tcg_gen_add2_i64(dl, dh, al, ah, bl, bh); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); - tcg_temp_free_i64(ah); - tcg_temp_free_i64(bh); } =20 static DisasJumpType op_vavg(DisasContext *s, DisasOps *o) @@ -1586,9 +1504,6 @@ static void gen_avgl_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b) tcg_gen_addi_i64(t0, t0, 1); tcg_gen_shri_i64(t0, t0, 1); tcg_gen_extrl_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); } =20 static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TCGv_i64 bl) @@ -1599,8 +1514,6 @@ static void gen_avgl_i64(TCGv_i64 dl, TCGv_i64 al, TC= Gv_i64 bl) tcg_gen_add2_i64(dl, dh, al, zero, bl, zero); gen_addi2_i64(dl, dh, dl, dh, 1); tcg_gen_extract2_i64(dl, dl, dh, 1); - - tcg_temp_free_i64(dh); } =20 static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o) @@ -1635,9 +1548,6 @@ static DisasJumpType op_vcksm(DisasContext *s, DisasO= ps *o) } gen_gvec_dup_imm(ES_32, get_field(s, v1), 0); write_vec_element_i32(sum, get_field(s, v1), 1, ES_32); - - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(sum); return DISAS_NEXT; } =20 @@ -1682,9 +1592,6 @@ static DisasJumpType op_vc(DisasContext *s, DisasOps = *o) read_vec_element_i64(high, get_field(s, v1), 0, ES_64); read_vec_element_i64(low, get_field(s, v1), 1, ES_64); gen_op_update2_cc_i64(s, CC_OP_VC, low, high); - - tcg_temp_free_i64(low); - tcg_temp_free_i64(high); } return DISAS_NEXT; } @@ -1853,8 +1760,6 @@ static void gen_mal_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b, TCGv_i32 c) =20 tcg_gen_mul_i32(t0, a, b); tcg_gen_add_i32(d, t0, c); - - tcg_temp_free_i32(t0); } =20 static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) @@ -1869,10 +1774,6 @@ static void gen_mah_i32(TCGv_i32 d, TCGv_i32 a, TCGv= _i32 b, TCGv_i32 c) tcg_gen_mul_i64(t0, t0, t1); tcg_gen_add_i64(t0, t0, t2); tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b, TCGv_i32 c) @@ -1887,10 +1788,6 @@ static void gen_malh_i32(TCGv_i32 d, TCGv_i32 a, TCG= v_i32 b, TCGv_i32 c) tcg_gen_mul_i64(t0, t0, t1); tcg_gen_add_i64(t0, t0, t2); tcg_gen_extrh_i64_i32(d, t0); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); } =20 static DisasJumpType op_vma(DisasContext *s, DisasOps *o) @@ -1974,7 +1871,6 @@ static void gen_mh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i= 32 b) TCGv_i32 t =3D tcg_temp_new_i32(); =20 tcg_gen_muls2_i32(t, d, a, b); - tcg_temp_free_i32(t); } =20 static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) @@ -1982,7 +1878,6 @@ static void gen_mlh_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b) TCGv_i32 t =3D tcg_temp_new_i32(); =20 tcg_gen_mulu2_i32(t, d, a, b); - tcg_temp_free_i32(t); } =20 static DisasJumpType op_vm(DisasContext *s, DisasOps *o) @@ -2099,11 +1994,6 @@ static DisasJumpType op_vmsl(DisasContext *s, DisasO= ps *o) /* Store final result into v1. */ write_vec_element_i64(h1, get_field(s, v1), 0, ES_64); write_vec_element_i64(l1, get_field(s, v1), 1, ES_64); - - tcg_temp_free_i64(l1); - tcg_temp_free_i64(h1); - tcg_temp_free_i64(l2); - tcg_temp_free_i64(h2); return DISAS_NEXT; } =20 @@ -2169,8 +2059,6 @@ static void gen_rim_i32(TCGv_i32 d, TCGv_i32 a, TCGv_= i32 b, int32_t c) tcg_gen_and_i32(t, t, b); tcg_gen_andc_i32(d, d, b); tcg_gen_or_i32(d, d, t); - - tcg_temp_free_i32(t); } =20 static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, int64_t c) @@ -2181,8 +2069,6 @@ static void gen_rim_i64(TCGv_i64 d, TCGv_i64 a, TCGv_= i64 b, int64_t c) tcg_gen_and_i64(t, t, b); tcg_gen_andc_i64(d, d, b); tcg_gen_or_i64(d, d, t); - - tcg_temp_free_i64(t); } =20 static DisasJumpType op_verim(DisasContext *s, DisasOps *o) @@ -2291,7 +2177,6 @@ static DisasJumpType op_ves(DisasContext *s, DisasOps= *o) default: g_assert_not_reached(); } - tcg_temp_free_i32(shift); } return DISAS_NEXT; } @@ -2311,7 +2196,6 @@ static DisasJumpType gen_vsh_by_byte(DisasContext *s,= DisasOps *o, read_vec_element_i64(shift, get_field(s, v3), 7, ES_8); tcg_gen_andi_i64(shift, shift, byte ? 0x78 : 7); gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2), shift, 0, gen); - tcg_temp_free_i64(shift); } return DISAS_NEXT; } @@ -2367,10 +2251,6 @@ static DisasJumpType op_vsld(DisasContext *s, DisasO= ps *o) =20 write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); return DISAS_NEXT; } =20 @@ -2397,10 +2277,6 @@ static DisasJumpType op_vsrd(DisasContext *s, DisasO= ps *o) =20 write_vec_element_i64(t0, get_field(s, v1), 0, ES_64); write_vec_element_i64(t1, get_field(s, v1), 1, ES_64); - - tcg_temp_free(t0); - tcg_temp_free(t1); - tcg_temp_free(t2); return DISAS_NEXT; } =20 @@ -2445,9 +2321,6 @@ static void gen_scbi2_i64(TCGv_i64 dl, TCGv_i64 dh, T= CGv_i64 al, /* "invert" the result: -1 -> 0; 0 -> 1 */ tcg_gen_addi_i64(dl, th, 1); tcg_gen_mov_i64(dh, zero); - - tcg_temp_free_i64(th); - tcg_temp_free_i64(tl); } =20 static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o) @@ -2482,8 +2355,6 @@ static void gen_sbi2_i64(TCGv_i64 dl, TCGv_i64 dh, TC= Gv_i64 al, TCGv_i64 ah, tcg_gen_not_i64(tl, bl); tcg_gen_not_i64(th, bh); gen_ac2_i64(dl, dh, al, ah, tl, th, cl, ch); - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } =20 static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o) @@ -2508,9 +2379,6 @@ static void gen_sbcbi2_i64(TCGv_i64 dl, TCGv_i64 dh, = TCGv_i64 al, TCGv_i64 ah, tcg_gen_not_i64(tl, bl); tcg_gen_not_i64(th, bh); gen_accc2_i64(dl, dh, al, ah, tl, th, cl, ch); - - tcg_temp_free_i64(tl); - tcg_temp_free_i64(th); } =20 static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o) @@ -2550,8 +2418,6 @@ static DisasJumpType op_vsumg(DisasContext *s, DisasO= ps *o) } write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64); } - tcg_temp_free_i64(sum); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -2580,10 +2446,6 @@ static DisasJumpType op_vsumq(DisasContext *s, Disas= Ops *o) } write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64); write_vec_element_i64(suml, get_field(s, v1), 1, ES_64); - - tcg_temp_free_i64(sumh); - tcg_temp_free_i64(suml); - tcg_temp_free_i64(tmpl); return DISAS_NEXT; } =20 @@ -2611,8 +2473,6 @@ static DisasJumpType op_vsum(DisasContext *s, DisasOp= s *o) } write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32); } - tcg_temp_free_i32(sum); - tcg_temp_free_i32(tmp); return DISAS_NEXT; } =20 @@ -3399,9 +3259,6 @@ static DisasJumpType op_vfpso(DisasContext *s, DisasO= ps *o) read_vec_element_i64(tmp, v2, 1, ES_64); write_vec_element_i64(tmp, v1, 1, ES_64); } - - tcg_temp_free_i64(tmp); - return DISAS_NEXT; } =20 --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954014; cv=none; d=zohomail.com; s=zohoarc; b=jtExDtyvMQ3wdw6Tb0T823k8VcKrSmR5zUwvjQYnW7pP2RW3J3M7SA4PZ5a269SrYmTT+QT7Nzrx2Qr98p5flEbC2ZiItY7Fpxk97WLKn5lnj3LxMyGKvvUabnt3UpLLfZhQLgUkw88L3Q/t863ZjxaVWKnvfC+oR1qIUNEnXjQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954014; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZMRi6iTabBuqewshsFpmAL1bTzHQn7PKicyf96FuaOQ=; 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Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: David Hildenbrand Cc: Ilya Leoshkevich Cc: Thomas Huth Cc: qemu-s390x@nongnu.org --- target/s390x/tcg/translate.c | 105 ----------------------------------- 1 file changed, 105 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 76a1233946..beccd3429e 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -306,8 +306,6 @@ static TCGv_i128 load_freg_128(int reg) TCGv_i128 r =3D tcg_temp_new_i128(); =20 tcg_gen_concat_i64_i128(r, l, h); - tcg_temp_free_i64(h); - tcg_temp_free_i64(l); return r; } =20 @@ -1263,10 +1261,8 @@ static DisasJumpType help_branch(DisasContext *s, Di= sasCompare *c, TCGv_i64 z =3D tcg_constant_i64(0); tcg_gen_setcond_i32(c->cond, t0, c->u.s32.a, c->u.s32.b); tcg_gen_extu_i32_i64(t1, t0); - tcg_temp_free_i32(t0); tcg_gen_movcond_i64(TCG_COND_NE, psw_addr, t1, z, cdest, next); per_branch_cond(s, TCG_COND_NE, t1, z); - tcg_temp_free_i64(t1); } =20 ret =3D DISAS_PC_UPDATED; @@ -1525,7 +1521,6 @@ static void save_link_info(DisasContext *s, DisasOps = *o) tcg_gen_extu_i32_i64(t, cc_op); tcg_gen_shli_i64(t, t, 28); tcg_gen_or_i64(o->out, o->out, t); - tcg_temp_free_i64(t); } =20 static DisasJumpType op_bal(DisasContext *s, DisasOps *o) @@ -1589,7 +1584,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasO= ps *o) c.u.s32.a =3D tcg_temp_new_i32(); c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); - tcg_temp_free_i64(t); =20 return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1611,7 +1605,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOp= s *o) c.u.s32.a =3D tcg_temp_new_i32(); c.u.s32.b =3D tcg_constant_i32(0); tcg_gen_extrl_i64_i32(c.u.s32.a, t); - tcg_temp_free_i64(t); =20 return help_branch(s, &c, 1, imm, o->in2); } @@ -1652,7 +1645,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOp= s *o) tcg_gen_extrl_i64_i32(c.u.s32.a, t); tcg_gen_extrl_i64_i32(c.u.s32.b, regs[r3 | 1]); store_reg32_i64(r1, t); - tcg_temp_free_i64(t); =20 return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1971,11 +1963,9 @@ static DisasJumpType op_cksm(DisasContext *s, DisasO= ps *o) gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); tcg_gen_extr_i128_i64(o->out, len, pair); - tcg_temp_free_i128(pair); =20 tcg_gen_add_i64(regs[r2], regs[r2], len); tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len); - tcg_temp_free_i64(len); =20 return DISAS_NEXT; } @@ -2077,7 +2067,6 @@ static DisasJumpType op_clm(DisasContext *s, DisasOps= *o) tcg_gen_extrl_i64_i32(t1, o->in1); gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2); set_cc_static(s); - tcg_temp_free_i32(t1); return DISAS_NEXT; } =20 @@ -2087,7 +2076,6 @@ static DisasJumpType op_clst(DisasContext *s, DisasOp= s *o) =20 gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); tcg_gen_extr_i128_i64(o->in2, o->in1, pair); - tcg_temp_free_i128(pair); =20 set_cc_static(s); return DISAS_NEXT; @@ -2099,7 +2087,6 @@ static DisasJumpType op_cps(DisasContext *s, DisasOps= *o) tcg_gen_andi_i64(t, o->in1, 0x8000000000000000ull); tcg_gen_andi_i64(o->out, o->in2, 0x7fffffffffffffffull); tcg_gen_or_i64(o->out, o->out, t); - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -2115,14 +2102,12 @@ static DisasJumpType op_cs(DisasContext *s, DisasOp= s *o) addr =3D get_address(s, 0, b2, d2); tcg_gen_atomic_cmpxchg_i64(o->out, addr, o->in2, o->in1, get_mem_index(s), s->insn->data | MO_ALIGN); - tcg_temp_free_i64(addr); =20 /* Are the memory and expected values (un)equal? Note that this setco= nd produces the output CC value, thus the NE sense of the test. */ cc =3D tcg_temp_new_i64(); tcg_gen_setcond_i64(TCG_COND_NE, cc, o->in2, o->out); tcg_gen_extrl_i64_i32(cc_op, cc); - tcg_temp_free_i64(cc); set_cc_static(s); =20 return DISAS_NEXT; @@ -2182,7 +2167,6 @@ static DisasJumpType op_csp(DisasContext *s, DisasOps= *o) tcg_gen_andi_i64(addr, o->in2, -1ULL << (mop & MO_SIZE)); tcg_gen_atomic_cmpxchg_i64(old, addr, o->in1, o->out2, get_mem_index(s), mop | MO_ALIGN); - tcg_temp_free_i64(addr); =20 /* Are the memory and expected values (un)equal? */ cc =3D tcg_temp_new_i64(); @@ -2196,14 +2180,12 @@ static DisasJumpType op_csp(DisasContext *s, DisasO= ps *o) } else { tcg_gen_mov_i64(o->out, old); } - tcg_temp_free_i64(old); =20 /* If the comparison was equal, and the LSB of R2 was set, then we need to flush the TLB (for all cpus). */ tcg_gen_xori_i64(cc, cc, 1); tcg_gen_and_i64(cc, cc, o->in2); tcg_gen_brcondi_i64(TCG_COND_EQ, cc, 0, lab); - tcg_temp_free_i64(cc); =20 gen_helper_purge(cpu_env); gen_set_label(lab); @@ -2218,9 +2200,7 @@ static DisasJumpType op_cvd(DisasContext *s, DisasOps= *o) TCGv_i32 t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, o->in1); gen_helper_cvd(t1, t2); - tcg_temp_free_i32(t2); tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s)); - tcg_temp_free_i64(t1); return DISAS_NEXT; } =20 @@ -2322,7 +2302,6 @@ static DisasJumpType op_divs64(DisasContext *s, Disas= Ops *o) =20 gen_helper_divs64(t, cpu_env, o->in1, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); - tcg_temp_free_i128(t); return DISAS_NEXT; } =20 @@ -2332,7 +2311,6 @@ static DisasJumpType op_divu64(DisasContext *s, Disas= Ops *o) =20 gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, t); - tcg_temp_free_i128(t); return DISAS_NEXT; } =20 @@ -2387,8 +2365,6 @@ static DisasJumpType op_epsw(DisasContext *s, DisasOp= s *o) if (r2 !=3D 0) { store_reg32_i64(r2, psw_mask); } - - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -2528,7 +2504,6 @@ static DisasJumpType op_icm(DisasContext *s, DisasOps= *o) =20 tcg_gen_movi_i64(tmp, ccm); gen_op_update2_cc_i64(s, CC_OP_ICM, tmp, o->out); - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -2551,8 +2526,6 @@ static DisasJumpType op_ipm(DisasContext *s, DisasOps= *o) tcg_gen_extu_i32_i64(t2, cc_op); tcg_gen_deposit_i64(t1, t1, t2, 4, 60); tcg_gen_deposit_i64(o->out, o->out, t1, 24, 8); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NEXT; } =20 @@ -2892,11 +2865,9 @@ static DisasJumpType op_loc(DisasContext *s, DisasOp= s *o) =20 t =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t, t32); - tcg_temp_free_i32(t32); =20 z =3D tcg_constant_i64(0); tcg_gen_movcond_i64(TCG_COND_NE, o->out, t, z, o->in2, o->in1); - tcg_temp_free_i64(t); } =20 return DISAS_NEXT; @@ -2953,8 +2924,6 @@ static DisasJumpType op_lpsw(DisasContext *s, DisasOp= s *o) /* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */ tcg_gen_shli_i64(t1, t1, 32); gen_helper_load_psw(cpu_env, t1, t2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NORETURN; } =20 @@ -2971,8 +2940,6 @@ static DisasJumpType op_lpswe(DisasContext *s, DisasO= ps *o) tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s)); gen_helper_load_psw(cpu_env, t1, t2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); return DISAS_NORETURN; } #endif @@ -2997,7 +2964,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) if (unlikely(r1 =3D=3D r3)) { tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32_i64(r1, t1); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3012,8 +2978,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) =20 /* Only two registers to read. */ if (((r1 + 1) & 15) =3D=3D r3) { - tcg_temp_free(t2); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3026,9 +2990,6 @@ static DisasJumpType op_lm32(DisasContext *s, DisasOp= s *o) tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32_i64(r1, t1); } - tcg_temp_free(t2); - tcg_temp_free(t1); - return DISAS_NEXT; } =20 @@ -3043,7 +3004,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) if (unlikely(r1 =3D=3D r3)) { tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32h_i64(r1, t1); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3058,8 +3018,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) =20 /* Only two registers to read. */ if (((r1 + 1) & 15) =3D=3D r3) { - tcg_temp_free(t2); - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3072,9 +3030,6 @@ static DisasJumpType op_lmh(DisasContext *s, DisasOps= *o) tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s)); store_reg32h_i64(r1, t1); } - tcg_temp_free(t2); - tcg_temp_free(t1); - return DISAS_NEXT; } =20 @@ -3098,11 +3053,9 @@ static DisasJumpType op_lm64(DisasContext *s, DisasO= ps *o) tcg_gen_addi_i64(t2, o->in2, 8 * ((r3 - r1) & 15)); tcg_gen_qemu_ld64(regs[r3], t2, get_mem_index(s)); tcg_gen_mov_i64(regs[r1], t1); - tcg_temp_free(t2); =20 /* Only two registers to read. */ if (((r1 + 1) & 15) =3D=3D r3) { - tcg_temp_free(t1); return DISAS_NEXT; } =20 @@ -3114,8 +3067,6 @@ static DisasJumpType op_lm64(DisasContext *s, DisasOp= s *o) tcg_gen_add_i64(o->in2, o->in2, t1); tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s)); } - tcg_temp_free(t1); - return DISAS_NEXT; } =20 @@ -3137,8 +3088,6 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps= *o) a2 =3D get_address(s, 0, get_field(s, b2), get_field(s, d2)); tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN); tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN); - tcg_temp_free_i64(a1); - tcg_temp_free_i64(a2); =20 /* ... and indicate that we performed them while interlocked. */ gen_op_movi_cc(s, 0); @@ -3246,8 +3195,6 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasO= ps *o) } =20 tcg_gen_st32_i64(ar1, cpu_env, offsetof(CPUS390XState, aregs[1])); - tcg_temp_free_i64(ar1); - return DISAS_NEXT; } =20 @@ -3466,7 +3413,6 @@ static DisasJumpType op_maeb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg32_i64(get_field(s, r3)); gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3474,7 +3420,6 @@ static DisasJumpType op_madb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg(get_field(s, r3)); gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3482,7 +3427,6 @@ static DisasJumpType op_mseb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg32_i64(get_field(s, r3)); gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3490,7 +3434,6 @@ static DisasJumpType op_msdb(DisasContext *s, DisasOp= s *o) { TCGv_i64 r3 =3D load_freg(get_field(s, r3)); gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3); - tcg_temp_free_i64(r3); return DISAS_NEXT; } =20 @@ -3501,7 +3444,6 @@ static DisasJumpType op_nabs(DisasContext *s, DisasOp= s *o) =20 tcg_gen_neg_i64(n, o->in2); tcg_gen_movcond_i64(TCG_COND_GE, o->out, o->in2, z, n, o->in2); - tcg_temp_free_i64(n); return DISAS_NEXT; } =20 @@ -3836,9 +3778,6 @@ static DisasJumpType op_rll32(DisasContext *s, DisasO= ps *o) tcg_gen_extrl_i64_i32(t2, o->in2); tcg_gen_rotl_i32(to, t1, t2); tcg_gen_extu_i32_i64(o->out, to); - tcg_temp_free_i32(t1); - tcg_temp_free_i32(t2); - tcg_temp_free_i32(to); return DISAS_NEXT; } =20 @@ -3993,12 +3932,10 @@ static DisasJumpType op_soc(DisasContext *s, DisasO= ps *o) h =3D tcg_temp_new_i64(); tcg_gen_shri_i64(h, regs[r1], 32); tcg_gen_qemu_st32(h, a, get_mem_index(s)); - tcg_temp_free_i64(h); break; default: g_assert_not_reached(); } - tcg_temp_free_i64(a); =20 gen_set_label(lab); return DISAS_NEXT; @@ -4015,9 +3952,6 @@ static DisasJumpType op_sla(DisasContext *s, DisasOps= *o) t =3D o->in1; } gen_op_update2_cc_i64(s, CC_OP_SLA, t, o->in2); - if (s->insn->data =3D=3D 31) { - tcg_temp_free_i64(t); - } tcg_gen_shl_i64(o->out, o->in1, o->in2); /* The arithmetic left shift is curious in that it does not affect the sign bit. Copy that over from the source unchanged. */ @@ -4084,8 +4018,6 @@ static DisasJumpType op_srnmt(DisasContext *s, DisasO= ps *o) tcg_gen_ld32u_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); tcg_gen_deposit_i64(tmp, tmp, o->addr1, 4, 3); tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUS390XState, fpc)); - - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -4126,8 +4058,6 @@ static DisasJumpType op_ectg(DisasContext *s, DisasOp= s *o) =20 /* store second operand in GR1 */ tcg_gen_mov_i64(regs[1], o->in2); - - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -4187,9 +4117,6 @@ static DisasJumpType op_stcke(DisasContext *s, DisasO= ps *o) tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s)); tcg_gen_addi_i64(o->in2, o->in2, 8); tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s)); - tcg_temp_free_i64(c1); - tcg_temp_free_i64(c2); - tcg_temp_free_i64(todpr); /* ??? We don't implement clock states. */ gen_op_movi_cc(s, 0); return DISAS_NEXT; @@ -4403,7 +4330,6 @@ static DisasJumpType op_stnosm(DisasContext *s, Disas= Ops *o) t =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t, psw_mask, 56); tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s)); - tcg_temp_free_i64(t); =20 if (s->fields.op =3D=3D 0xac) { tcg_gen_andi_i64(psw_mask, psw_mask, @@ -4514,7 +4440,6 @@ static DisasJumpType op_stcm(DisasContext *s, DisasOp= s *o) } break; } - tcg_temp_free_i64(tmp); return DISAS_NEXT; } =20 @@ -4558,8 +4483,6 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOp= s *o) tcg_gen_add_i64(o->in2, o->in2, t4); r1 =3D (r1 + 1) & 15; } - - tcg_temp_free_i64(t); return DISAS_NEXT; } =20 @@ -4746,7 +4669,6 @@ static DisasJumpType op_tre(DisasContext *s, DisasOps= *o) =20 gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); tcg_gen_extr_i128_i64(o->out2, o->out, pair); - tcg_temp_free_i128(pair); set_cc_static(s); return DISAS_NEXT; } @@ -4792,7 +4714,6 @@ static DisasJumpType op_trXX(DisasContext *s, DisasOp= s *o) } gen_helper_trXX(cc_op, cpu_env, r1, r2, tst, sizes); =20 - tcg_temp_free_i32(tst); set_cc_static(s); return DISAS_NEXT; } @@ -5299,7 +5220,6 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o) store_reg32_i64(r1 + 1, o->out); tcg_gen_shri_i64(t, o->out, 32); store_reg32_i64(r1, t); - tcg_temp_free_i64(t); } #define SPEC_wout_r1_D32 SPEC_r1_even =20 @@ -6425,31 +6345,6 @@ static DisasJumpType translate_one(CPUS390XState *en= v, DisasContext *s) } } =20 - /* Free any temporaries created by the helpers. */ - if (o.out && !o.g_out) { - tcg_temp_free_i64(o.out); - } - if (o.out2 && !o.g_out2) { - tcg_temp_free_i64(o.out2); - } - if (o.in1 && !o.g_in1) { - tcg_temp_free_i64(o.in1); - } - if (o.in2 && !o.g_in2) { - tcg_temp_free_i64(o.in2); - } - if (o.addr1) { - tcg_temp_free_i64(o.addr1); - } - if (o.out_128) { - tcg_temp_free_i128(o.out_128); - } - if (o.in1_128) { - tcg_temp_free_i128(o.in1_128); - } - if (o.in2_128) { - tcg_temp_free_i128(o.in2_128); - } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret =3D=3D DISAS_NEXT)) { ret =3D DISAS_TOO_MANY; --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677954127; cv=none; d=zohomail.com; s=zohoarc; b=AD6nKiaOo16Z9XEFuFys8O/NLK7UnVsx0uJ1BaCk355jMQgqxAwOmhLzIe5Pz+1hKIsUu0o/jSgVaFz7lyAkqWDsJAc/aNx5Zf5fmx05P+jxm6nVfx/eeLxMyFxRU+HF1yopdWF5hrqMv6a7Ahm4mHtCH5ZWFN40BUr59NY64G4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677954127; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iTwpX71LYq/RTJCaFN4Ey+fij6djZh42xCt7K+NhOLc=; b=KOUT/tMBDWX5DX5SUWJCMGxrUvMkiPQxIhr6BrJ6NBGG2tLfytkoDWeXqPq7fJGBIauzv4CXlIzMQguTIU/fPzZmrwueHH+C1TDzViGXqV5dgFhJGS3+dMDpwTLBsddKi3LmZm1WgHlC0FwoZtB7XTY3CDXAQhBBRSSNpUfOwvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167795412767088.15635359000112; Sat, 4 Mar 2023 10:22:07 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTi-0006XO-TO; Sat, 04 Mar 2023 13:19:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTZ-0006Th-4O for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:21 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTV-0003Pj-UO for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:20 -0500 Received: by mail-pj1-x1031.google.com with SMTP id m20-20020a17090ab79400b00239d8e182efso9287061pjr.5 for ; Sat, 04 Mar 2023 10:19:17 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iTwpX71LYq/RTJCaFN4Ey+fij6djZh42xCt7K+NhOLc=; b=bKj4+BjEXHWryA0qy9We2LbhclnBJq7pISJZrnUXYLaxgbX8jyru+kdgQTs9qnHs9B Q/BCQ+uXB+tExGyIjHoYjOC4eD+Pvv3Hzb9gXia/WLIDvEeopMqbdDASG5z/CHT+zBRz qCg6cjLzKf43EPJaMIVu1zcaFU1AXczVXHJBWOK+FbvXGYVvzuWpVk11oLXXo8FSlRBj v6Q+zXLAjVafgJ8ZC6ZOgDTyrr+KzhwhBSiY9XPVUZo78BvsIMklqzIv168hH+D9pQ7q ZG6cjQto2u3Yc3Bf+N2M7DKHGb7J+u4X/XV4L7w+1dHBqMwQdy5TK+S81FVf6tUd0a0N Mp/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953956; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iTwpX71LYq/RTJCaFN4Ey+fij6djZh42xCt7K+NhOLc=; b=F7FS176rapQ0CyPgt+dFMjEul6ce5CiBZ5xatd5xY0QLOgvy3cy4GZNVmiZIIXDAIG rM/STqESwhPQn927j0ykOXELGX+Q1aDKyNIPBYnCsYJwDSogO1jssbUgIv9/KkJOLSzY 3hmFsKJtzd2Mq32smG9YZOm3JQFehzUBdnEpEAQ21YQ2wQmqBrLV7tBL740ahXQjaKyO QUbkIMgI5CQF7fRQXkJECe9p4DU8L5I0xU+E0CCC8GdfnhdzNoqEdFc1H227E8Y4j2a5 Lri4qH9ItSAyT89i70Mzm62o0Tz/UqGfKcYuB+2LbvBwof/JLj/4gj9k7gJaHq94YLPO sT+Q== X-Gm-Message-State: AO0yUKVr4aTzItDPHgZVTrXx4tm6peht6JiT4FeHPPvZbW0JItC8hZ92 a4xwFlSrxE2p5kwUtbjqAfdixMW6HkWWvMgk8FTwxA== X-Google-Smtp-Source: AK7set+kx8MGWBIFlFRUfwKfLPzWwnnbCOynD5nUgF7IfaZSfUeeucjFu5G5OXUOYZmh079pzaG9cg== X-Received: by 2002:a05:6a20:8e28:b0:cd:7fcf:11a6 with SMTP id y40-20020a056a208e2800b000cd7fcf11a6mr6344368pzj.48.1677953956048; Sat, 04 Mar 2023 10:19:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-s390x@nongnu.org Subject: [PATCH v3 16/20] target/s390x: Remove assert vs g_in2 Date: Sat, 4 Mar 2023 10:18:56 -0800 Message-Id: <20230304181900.1097116-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954128776100003 Content-Type: text/plain; charset="utf-8" These were trying to determine if o->in2 was available for use as a temporary. It's better to just allocate a new one. Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: David Hildenbrand Cc: Ilya Leoshkevich Cc: Thomas Huth Cc: qemu-s390x@nongnu.org --- target/s390x/tcg/translate.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index beccd3429e..c431903c67 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1428,11 +1428,11 @@ static DisasJumpType op_andi(DisasContext *s, Disas= Ops *o) int shift =3D s->insn->data & 0xff; int size =3D s->insn->data >> 8; uint64_t mask =3D ((1ull << size) - 1) << shift; + TCGv_i64 t =3D tcg_temp_new_i64(); =20 - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_ori_i64(o->in2, o->in2, ~mask); - tcg_gen_and_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_ori_i64(t, t, ~mask); + tcg_gen_and_i64(o->out, o->in1, t); =20 /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); @@ -3520,10 +3520,10 @@ static DisasJumpType op_ori(DisasContext *s, DisasO= ps *o) int shift =3D s->insn->data & 0xff; int size =3D s->insn->data >> 8; uint64_t mask =3D ((1ull << size) - 1) << shift; + TCGv_i64 t =3D tcg_temp_new_i64(); =20 - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_or_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_or_i64(o->out, o->in1, t); =20 /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); @@ -4832,10 +4832,10 @@ static DisasJumpType op_xori(DisasContext *s, Disas= Ops *o) int shift =3D s->insn->data & 0xff; int size =3D s->insn->data >> 8; uint64_t mask =3D ((1ull << size) - 1) << shift; + TCGv_i64 t =3D tcg_temp_new_i64(); =20 - assert(!o->g_in2); - tcg_gen_shli_i64(o->in2, o->in2, shift); - tcg_gen_xor_i64(o->out, o->in1, o->in2); + tcg_gen_shli_i64(t, o->in2, shift); + tcg_gen_xor_i64(o->out, o->in1, t); =20 /* Produce the CC from only the bits manipulated. */ tcg_gen_andi_i64(cc_dst, o->out, mask); --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1677953991; cv=none; d=zohomail.com; s=zohoarc; b=KO0s9HeT2ZsM1jPxQfQAvjOoJl1PqAUDw5QoVPKJ1v4ARUOg1RCCnQWC0K+HjA60eWA6UxkOSZcvKvJUSvo4mpzCDVxDLvYQCdHaU7JmeblR96iIe2GAL2HunETiZXeVR4DMTSggoyKiI+QHqw+NbfBvu1o9LyZDeZKQOOQCpTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1677953991; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eUy1JZzTuPGot+rHAkA2NlK/qSoLXklkglokMU7FjFM=; b=kzD7eJYxEehpE5Hh91sQ/iz9Fm2LYVe6GKS5i2b4vnMcSlXOT3nCNlDyPBxg4ACbVrpZEgtCPekVv1k9iQBG0PWjFJR3aaU1EFgK+gzYhNVNjEXXbMAKEBTeXtECf/qFhTIHlw0VKHf8ZLWTqd67ENXLt5lKuCX8wtOOEB1bVw8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167795399094168.51221104808371; Sat, 4 Mar 2023 10:19:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pYWTh-0006Wp-3J; Sat, 04 Mar 2023 13:19:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pYWTa-0006VA-EY for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:22 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pYWTW-0003Q7-C3 for qemu-devel@nongnu.org; Sat, 04 Mar 2023 13:19:22 -0500 Received: by mail-pg1-x536.google.com with SMTP id bn17so3285777pgb.10 for ; Sat, 04 Mar 2023 10:19:17 -0800 (PST) Received: from stoup.. ([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eUy1JZzTuPGot+rHAkA2NlK/qSoLXklkglokMU7FjFM=; b=PSmetU192pX5NhrBoJffrp8d03rM8C6z0DYtTxZ7y+SdQjOPJ/db37V8Z0GU3Lv3GA I3HNDqn6lQjZwynsYOyDj/Fy4Jkff58DrLPo5R+FxNzmXTdKW1He+rY2Ph0nOgIQvqkd vYGFCqs87G/JU+rs8kIlk84Fh8JrKKdFwNS8VWUaaXGknlNmW+GYae79onnMOqvV+Bgr n4yFrVoUOHluW309Py4wtcSzDajNqAc+U6wYQyLyINxgWD0ryWFhOFqFf5ERWnuMByc2 ZtCAfSivTid/cIquPAsmqHXKkQFAcGIfERLlvi48wIfqAg2nDb2YLFT95LKL3u05Q6+u 40pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eUy1JZzTuPGot+rHAkA2NlK/qSoLXklkglokMU7FjFM=; b=p8d1KUSYdC5GE7LWSCuIMSdc6iIFncgnXhgqRVVW55LSr+91lcuB2EOqRvNT/OhuXY vwlmpQ/wHwfjb3Oivxd8wW9tpU3ppF7OMqw3Rmj0jUoKiffevKLdtPCQ5Mu85VbuMxql VdWLouTWDd07bgZfT4eFQQb8bePTC7dxK0HOc7QXk2IMn15BWgmiEuynMmk4mVeHEk5U W2RQhN3El/otoAD/NTwy1m9KvkbG0zmw4y7Aj+vfHEXqEm/FeFENxD8rOzXhQn/alKls Kl6hDxqb9JW4xFfS0TPAOQJFHaZwe0WUEeoQywZsJEFqUww0k1R5rF/vVANTlKid5miH WTpw== X-Gm-Message-State: AO0yUKW1lek4zcnN5NZudknAzOrxgWgG/b7vnczAasFy31Q9zDcWzgWK kDizmodCVpRPTFNLZvb4ne1TC/8oc1PXIBmrZEmqCA== X-Google-Smtp-Source: AK7set/JgSGE0bs6vptGSrkDgQw3UY7UwBMOvcr1tr2EVk/4Fhi5XWPgdfHNisKIr/yu5P6AzGKcbA== X-Received: by 2002:a62:1b89:0:b0:5db:ba81:dd9f with SMTP id b131-20020a621b89000000b005dbba81dd9fmr5529561pfb.30.1677953956891; Sat, 04 Mar 2023 10:19:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-s390x@nongnu.org Subject: [PATCH v3 17/20] target/s390x: Remove g_out, g_out2, g_in1, g_in2 from DisasContext Date: Sat, 4 Mar 2023 10:18:57 -0800 Message-Id: <20230304181900.1097116-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677953991513100001 Content-Type: text/plain; charset="utf-8" These fields are no longer read, so remove them and the writes. Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: David Hildenbrand Cc: Ilya Leoshkevich Cc: Thomas Huth Cc: qemu-s390x@nongnu.org --- target/s390x/tcg/translate.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index c431903c67..9974162527 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1061,7 +1061,6 @@ static const DisasFormatInfo format_info[] =3D { them, and store them back. See the "in1", "in2", "prep", "wout" sets of routines below for more details. */ typedef struct { - bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; TCGv_i128 out_128, in1_128, in2_128; @@ -3159,9 +3158,7 @@ static DisasJumpType op_mc(DisasContext *s, DisasOps = *o) static DisasJumpType op_mov2(DisasContext *s, DisasOps *o) { o->out =3D o->in2; - o->g_out =3D o->g_in2; o->in2 =3D NULL; - o->g_in2 =3D false; return DISAS_NEXT; } =20 @@ -3171,9 +3168,7 @@ static DisasJumpType op_mov2e(DisasContext *s, DisasO= ps *o) TCGv ar1 =3D tcg_temp_new_i64(); =20 o->out =3D o->in2; - o->g_out =3D o->g_in2; o->in2 =3D NULL; - o->g_in2 =3D false; =20 switch (s->base.tb->flags & FLAG_MASK_ASC) { case PSW_ASC_PRIMARY >> FLAG_MASK_PSW_SHIFT: @@ -3202,11 +3197,8 @@ static DisasJumpType op_movx(DisasContext *s, DisasO= ps *o) { o->out =3D o->in1; o->out2 =3D o->in2; - o->g_out =3D o->g_in1; - o->g_out2 =3D o->g_in2; o->in1 =3D NULL; o->in2 =3D NULL; - o->g_in1 =3D o->g_in2 =3D false; return DISAS_NEXT; } =20 @@ -3708,7 +3700,6 @@ static DisasJumpType op_rosbg(DisasContext *s, DisasO= ps *o) /* If this is a test-only form, arrange to discard the result. */ if (i3 & 0x80) { o->out =3D tcg_temp_new_i64(); - o->g_out =3D false; } =20 i3 &=3D 63; @@ -4874,7 +4865,6 @@ static DisasJumpType op_zero2(DisasContext *s, DisasO= ps *o) { o->out =3D tcg_const_i64(0); o->out2 =3D o->out; - o->g_out2 =3D true; return DISAS_NEXT; } =20 @@ -5142,7 +5132,6 @@ static void prep_new_x(DisasContext *s, DisasOps *o) static void prep_r1(DisasContext *s, DisasOps *o) { o->out =3D regs[get_field(s, r1)]; - o->g_out =3D true; } #define SPEC_prep_r1 0 =20 @@ -5151,7 +5140,6 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) int r1 =3D get_field(s, r1); o->out =3D regs[r1]; o->out2 =3D regs[r1 + 1]; - o->g_out =3D o->g_out2 =3D true; } #define SPEC_prep_r1_P SPEC_r1_even =20 @@ -5375,7 +5363,6 @@ static void in1_r1(DisasContext *s, DisasOps *o) static void in1_r1_o(DisasContext *s, DisasOps *o) { o->in1 =3D regs[get_field(s, r1)]; - o->g_in1 =3D true; } #define SPEC_in1_r1_o 0 =20 @@ -5409,7 +5396,6 @@ static void in1_r1p1(DisasContext *s, DisasOps *o) static void in1_r1p1_o(DisasContext *s, DisasOps *o) { o->in1 =3D regs[get_field(s, r1) + 1]; - o->g_in1 =3D true; } #define SPEC_in1_r1p1_o SPEC_r1_even =20 @@ -5464,7 +5450,6 @@ static void in1_r3(DisasContext *s, DisasOps *o) static void in1_r3_o(DisasContext *s, DisasOps *o) { o->in1 =3D regs[get_field(s, r3)]; - o->g_in1 =3D true; } #define SPEC_in1_r3_o 0 =20 @@ -5595,7 +5580,6 @@ static void in1_m1_64(DisasContext *s, DisasOps *o) static void in2_r1_o(DisasContext *s, DisasOps *o) { o->in2 =3D regs[get_field(s, r1)]; - o->g_in2 =3D true; } #define SPEC_in2_r1_o 0 =20 @@ -5630,7 +5614,6 @@ static void in2_r2(DisasContext *s, DisasOps *o) static void in2_r2_o(DisasContext *s, DisasOps *o) { o->in2 =3D regs[get_field(s, r2)]; - o->g_in2 =3D true; } #define SPEC_in2_r2_o 0 =20 --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FjUs7IQ5pTMPhZROb//xSGJhTy4N7fZxkBAMa560Dx4=; b=CnyHI3B4vL1GFoaSd4P6wIx+Mf3rmcJXvto3rMUYu77EiZ88LFOKXH6Jw2bXBStxkf VHN2LfM6JMLX2xKkdOvj+gdUJMoEFMxUY2BaEf8RVQ63CqDdajpi8jiE+H803nWVjJ2g JTTgqGIrcpdSP/TI7z9F7SpLft1d3D3d62mH3OGUktP/Rz8NhrO+tkOgAFEfdwsaCdso WmGohkYurU8EsiZvcmqZFFtNk205lvKZFS1wTNCOvv5FkNS/T4CVYhnJLRETNfmbD4yj 2OI4E7VIqn7H8ohXnaVbKCxHRm7H6kgglQpCMAQO3I+ckXjw+f/5flE9mI4CpoNC5NHa 7xRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FjUs7IQ5pTMPhZROb//xSGJhTy4N7fZxkBAMa560Dx4=; b=RFvYTcT8EItPAgGiLTqHlxXcOfuBLQXmsvt3CZshh08c+/uA42aACBJW7I1Cz7v/d1 QMMfDDe+QiZ70naNPGMb6rnhSUSraNiqhtll6eHXp1STDbtdT0UpUsPvDn6u69zNoK6p xzJf4/G0vP5Gd/d32XrvsEWw628tSiCcbugrdhT6EuET3HSEQRtQMkusiesDuWfG4lEJ iktNwmQQbewo7md/sc5W3KppQB7ZQVrl9SNae7h+nApEAAI9lttX9AxBWi4yDOK6Xm1M L4pSO5oamHjKm9wnsxDHvr0vjx0tIQ6J6oC5Bc4/wtZqPSMXx6FBNiU4gPnTIkP/IImy 3bmg== X-Gm-Message-State: AO0yUKXvmkiU7hXY7V9ds0hfsf+zcfwf5BjG/kTSubf55qWj+9uX6cxU c8BxXIjmYu4JsIRBljaqkGzSH4TFUO7gAphm16MN5mO4 X-Google-Smtp-Source: AK7set/hurtbxY1yLlquy0BEnj8bRr10Q0D3ZiD/D8Qxngzv4Ei4c7YZhXireb4XkpiLVYaytDv9CA== X-Received: by 2002:a05:6a20:c512:b0:cd:947a:a48 with SMTP id gm18-20020a056a20c51200b000cd947a0a48mr4867845pzb.25.1677953957839; Sat, 04 Mar 2023 10:19:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Bastian Koppelmann Subject: [PATCH v3 18/20] target/tricore: Drop tcg_temp_free Date: Sat, 4 Mar 2023 10:18:58 -0800 Message-Id: <20230304181900.1097116-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1043.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954022297100003 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Bastian Koppelmann --- target/tricore/translate.c | 540 +------------------------------------ 1 file changed, 4 insertions(+), 536 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 176ea96b2b..127f9a989a 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -126,7 +126,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) #define gen_helper_1arg(name, arg) do { \ TCGv_i32 helper_tmp =3D tcg_const_i32(arg); \ gen_helper_##name(cpu_env, helper_tmp); \ - tcg_temp_free_i32(helper_tmp); \ } while (0) =20 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ @@ -137,9 +136,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) tcg_gen_ext16s_tl(arg01, arg0); \ tcg_gen_ext16s_tl(arg11, arg1); \ gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ @@ -152,10 +148,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int= flags) tcg_gen_sari_tl(arg11, arg1, 16); \ tcg_gen_ext16s_tl(arg10, arg1); \ gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg10); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ @@ -168,10 +160,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int= flags) tcg_gen_sari_tl(arg10, arg1, 16); \ tcg_gen_ext16s_tl(arg11, arg1); \ gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg10); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ @@ -182,9 +170,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) tcg_gen_ext16s_tl(arg00, arg0); \ tcg_gen_sari_tl(arg11, arg1, 16); \ gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ - tcg_temp_free(arg00); \ - tcg_temp_free(arg01); \ - tcg_temp_free(arg11); \ } while (0) =20 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ @@ -194,9 +179,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) tcg_gen_concat_i32_i64(arg1, al1, ah1); \ gen_helper_##name(ret, arg1, arg2); \ tcg_gen_extr_i64_i32(rl, rh, ret); \ - \ - tcg_temp_free_i64(ret); \ - tcg_temp_free_i64(arg1); \ } while (0) =20 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ @@ -204,8 +186,6 @@ void tricore_cpu_dump_state(CPUState *cs, FILE *f, int = flags) \ gen_helper_##name(ret, cpu_env, arg1, arg2); \ tcg_gen_extr_i64_i32(rl, rh, ret); \ - \ - tcg_temp_free_i64(ret); \ } while (0) =20 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) @@ -229,7 +209,6 @@ static inline void gen_offset_ld(DisasContext *ctx, TCG= v r1, TCGv r2, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, con); tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); - tcg_temp_free(temp); } =20 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, @@ -238,7 +217,6 @@ static inline void gen_offset_st(DisasContext *ctx, TCG= v r1, TCGv r2, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, r2, con); tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); - tcg_temp_free(temp); } =20 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *= ctx) @@ -247,8 +225,6 @@ static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv addr= ess, DisasContext *ctx) =20 tcg_gen_concat_i32_i64(temp, rl, rh); tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEUQ); - - tcg_temp_free_i64(temp); } =20 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, @@ -257,7 +233,6 @@ static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv = base, int16_t con, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, base, con); gen_st_2regs_64(rh, rl, temp, ctx); - tcg_temp_free(temp); } =20 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *= ctx) @@ -267,8 +242,6 @@ static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv addr= ess, DisasContext *ctx) tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEUQ); /* write back to two 32 bit regs */ tcg_gen_extr_i64_i32(rl, rh, temp); - - tcg_temp_free_i64(temp); } =20 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, @@ -277,7 +250,6 @@ static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv = base, int16_t con, TCGv temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, base, con); gen_ld_2regs_64(rh, rl, temp, ctx); - tcg_temp_free(temp); } =20 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t of= f, @@ -287,7 +259,6 @@ static void gen_st_preincr(DisasContext *ctx, TCGv r1, = TCGv r2, int16_t off, tcg_gen_addi_tl(temp, r2, off); tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); tcg_gen_mov_tl(r2, temp); - tcg_temp_free(temp); } =20 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t of= f, @@ -297,7 +268,6 @@ static void gen_ld_preincr(DisasContext *ctx, TCGv r1, = TCGv r2, int16_t off, tcg_gen_addi_tl(temp, r2, off); tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); tcg_gen_mov_tl(r2, temp); - tcg_temp_free(temp); } =20 /* M(EA, word) =3D (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32= ]); */ @@ -317,9 +287,6 @@ static void gen_ldmst(DisasContext *ctx, int ereg, TCGv= ea) tcg_gen_or_tl(temp, temp, temp2); /* M(EA, word) =3D temp; */ tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 /* tmp =3D M(EA, word); @@ -332,8 +299,6 @@ static void gen_swap(DisasContext *ctx, int reg, TCGv e= a) tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); tcg_gen_mov_tl(cpu_gpr_d[reg], temp); - - tcg_temp_free(temp); } =20 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) @@ -345,9 +310,6 @@ static void gen_cmpswap(DisasContext *ctx, int reg, TCG= v ea) cpu_gpr_d[reg], temp); tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); tcg_gen_mov_tl(cpu_gpr_d[reg], temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) @@ -362,10 +324,6 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TC= Gv ea) tcg_gen_or_tl(temp2, temp2, temp3); tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); tcg_gen_mov_tl(cpu_gpr_d[reg], temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 =20 @@ -447,9 +405,6 @@ static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(t0); } =20 static inline void @@ -476,11 +431,6 @@ gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_i64(ret, result); - - tcg_temp_free(temp); - tcg_temp_free_i64(result); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static inline void @@ -527,11 +477,6 @@ gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_lo= w, TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free(temp4); } =20 /* ret =3D r2 + (r1 * r3); */ @@ -564,17 +509,12 @@ static inline void gen_madd32_d(TCGv ret, TCGv r1, TC= Gv r2, TCGv r3) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_madd32_d(ret, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void @@ -603,11 +543,6 @@ gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCG= v r2_low, TCGv r2_high, /* write back the result */ tcg_gen_mov_tl(ret_low, t3); tcg_gen_mov_tl(ret_high, t4); - - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); } =20 static inline void @@ -638,10 +573,6 @@ gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -650,7 +581,6 @@ gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCG= v r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -659,7 +589,6 @@ gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -686,9 +615,6 @@ gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TC= Gv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_add_tl, tcg_gen_add_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -715,9 +641,6 @@ gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_sub_tl, tcg_gen_add_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -751,11 +674,6 @@ gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, gen_add64_d(temp64_2, temp64_3, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); @@ -792,12 +710,6 @@ gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); - } =20 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); @@ -834,12 +746,6 @@ gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); - } =20 static inline void @@ -872,10 +778,6 @@ gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_lo= w, TCGv r1_high, TCGv r2, =20 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 =20 @@ -905,11 +807,6 @@ gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, gen_add64_d(temp64_3, temp64_2, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void @@ -936,10 +833,6 @@ gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low,= TCGv r1_high, TCGv r2, tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 static inline void @@ -963,9 +856,6 @@ gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv= r2, TCGv r3, uint32_t n, break; } gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -977,9 +867,6 @@ gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint= 32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1005,10 +892,6 @@ gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, = uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 =20 @@ -1033,9 +916,6 @@ gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TC= Gv r2, TCGv r3, break; } gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1047,9 +927,6 @@ gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, ui= nt32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1075,10 +952,6 @@ gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,= uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1086,7 +959,6 @@ gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint3= 2_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1094,7 +966,6 @@ gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint= 32_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1145,13 +1016,6 @@ gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv ar= g3, uint32_t n, tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -1169,9 +1033,6 @@ gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_add_d(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1189,9 +1050,6 @@ gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv = arg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_adds(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1219,12 +1077,6 @@ gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, gen_add64_d(t3, t1, t2); /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t3); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1251,11 +1103,6 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCG= v arg1_high, TCGv arg2, =20 gen_helper_add64_ssov(t1, cpu_env, t1, t2); tcg_gen_extr_i64_i32(rl, rh, t1); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 static inline void @@ -1294,9 +1141,6 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv ar= g1_high, TCGv arg2, tcg_gen_shli_tl(temp, temp, 31); /* negate v bit, if special condition */ tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t4); @@ -1307,11 +1151,6 @@ gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -1330,10 +1169,6 @@ gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n, tcg_gen_sari_i64(t2, t2, up_shift - n); =20 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -1346,10 +1181,8 @@ gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv = arg1_high, TCGv arg2, tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); tcg_gen_extr_i64_i32(rl, rh, r1); - - tcg_temp_free_i64(r1); - tcg_temp_free(temp); } + /* ret =3D r2 - (r1 * r3); */ static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) { @@ -1381,17 +1214,12 @@ static inline void gen_msub32_d(TCGv ret, TCGv r1, = TCGv r2, TCGv r3) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_msub32_d(ret, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1420,11 +1248,6 @@ gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, /* write back the result */ tcg_gen_mov_tl(ret_low, t3); tcg_gen_mov_tl(ret_high, t4); - - tcg_temp_free(t1); - tcg_temp_free(t2); - tcg_temp_free(t3); - tcg_temp_free(t4); } =20 static inline void @@ -1433,7 +1256,6 @@ gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1462,10 +1284,6 @@ gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, = TCGv r2_low, TCGv r2_high, tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); } =20 static inline void @@ -1474,15 +1292,14 @@ gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1= , TCGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) { TCGv temp =3D tcg_const_i32(r2); gen_add_d(ret, r1, temp); - tcg_temp_free(temp); } + /* calculate the carry bit too */ static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) { @@ -1505,16 +1322,12 @@ static inline void gen_add_CC(TCGv ret, TCGv r1, TC= Gv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(t0); } =20 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_add_CC(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) @@ -1541,17 +1354,12 @@ static inline void gen_addc_CC(TCGv ret, TCGv r1, T= CGv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(t0); - tcg_temp_free(carry); } =20 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_addc_CC(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, @@ -1585,12 +1393,6 @@ static inline void gen_cond_add(TCGCond cond, TCGv r= 1, TCGv r2, TCGv r3, tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); /* write back result */ tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); - - tcg_temp_free(t0); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(result); - tcg_temp_free(mask); } =20 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, @@ -1598,7 +1400,6 @@ static inline void gen_condi_add(TCGCond cond, TCGv r= 1, int32_t r2, { TCGv temp =3D tcg_const_i32(r2); gen_cond_add(cond, r1, temp, r3, r4); - tcg_temp_free(temp); } =20 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) @@ -1620,9 +1421,6 @@ static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv = r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(temp); - tcg_temp_free(result); } =20 static inline void @@ -1649,11 +1447,6 @@ gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_i64(ret, result); - - tcg_temp_free(temp); - tcg_temp_free_i64(result); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); } =20 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) @@ -1677,9 +1470,6 @@ static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv= r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(result); - tcg_temp_free(temp); } =20 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) @@ -1687,7 +1477,6 @@ static inline void gen_subc_CC(TCGv ret, TCGv r1, TCG= v r2) TCGv temp =3D tcg_temp_new(); tcg_gen_not_tl(temp, r2); gen_addc_CC(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, @@ -1721,12 +1510,6 @@ static inline void gen_cond_sub(TCGCond cond, TCGv r= 1, TCGv r2, TCGv r3, tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); /* write back result */ tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); - - tcg_temp_free(t0); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(result); - tcg_temp_free(mask); } =20 static inline void @@ -1753,9 +1536,6 @@ gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, = TCGv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_sub_tl, tcg_gen_sub_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1790,11 +1570,6 @@ gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1823,11 +1598,6 @@ gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, gen_sub64_d(temp64_3, temp64_2, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void @@ -1854,10 +1624,6 @@ gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_lo= w, TCGv r1_high, TCGv r2, tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 static inline void @@ -1881,9 +1647,6 @@ gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TC= Gv r2, TCGv r3, uint32_t n, break; } gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1895,9 +1658,6 @@ gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, ui= nt32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1921,9 +1681,6 @@ gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, T= CGv r2, TCGv r3, break; } gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -1935,9 +1692,6 @@ gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, u= int32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -1945,7 +1699,6 @@ gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint= 32_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void @@ -1953,15 +1706,12 @@ gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, u= int32_t n) { TCGv temp =3D tcg_const_i32(n); gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); - tcg_temp_free(temp); } =20 static inline void gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, uint32_t up_shift) { - TCGv temp =3D tcg_temp_new(); - TCGv temp2 =3D tcg_temp_new(); TCGv temp3 =3D tcg_temp_new(); TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); @@ -1997,14 +1747,6 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv ar= g3, uint32_t n, tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -2022,9 +1764,6 @@ gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_sub_d(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -2042,9 +1781,6 @@ gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv = arg3, uint32_t n) tcg_gen_sub_tl(temp, temp, temp2); } gen_subs(ret, arg1, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -2072,12 +1808,6 @@ gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv= arg1_high, TCGv arg2, gen_sub64_d(t3, t1, t2); /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t3); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -2104,11 +1834,6 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCG= v arg1_high, TCGv arg2, =20 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); tcg_gen_extr_i64_i32(rl, rh, t1); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); } =20 static inline void @@ -2147,9 +1872,6 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv ar= g1_high, TCGv arg2, tcg_gen_shli_tl(temp, temp, 31); /* negate v bit, if special condition */ tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } /* write back result */ tcg_gen_extr_i64_i32(rl, rh, t4); @@ -2160,11 +1882,6 @@ gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); /* calc SAV */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -2188,11 +1905,6 @@ gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv a= rg3, uint32_t n, tcg_gen_add_i64(t3, t3, t4); =20 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); - - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); - tcg_temp_free_i64(t3); - tcg_temp_free_i64(t4); } =20 static inline void @@ -2205,9 +1917,6 @@ gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv a= rg1_high, TCGv arg2, tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); tcg_gen_extr_i64_i32(rl, rh, r1); - - tcg_temp_free_i64(r1); - tcg_temp_free(temp); } =20 static inline void @@ -2234,9 +1943,6 @@ gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low= , TCGv r1_high, TCGv r2, tcg_gen_extr_i64_i32(temp, temp2, temp64); gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, tcg_gen_add_tl, tcg_gen_sub_tl); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2270,11 +1976,6 @@ gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_l= ow, TCGv r1_high, TCGv r2, gen_sub64_d(temp64_2, temp64_3, temp64); /* write back result */ tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); - tcg_temp_free_i64(temp64_3); } =20 static inline void @@ -2300,10 +2001,6 @@ gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3,= uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2338,11 +2035,6 @@ gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_l= ow, TCGv r1_high, TCGv r2, tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); /* combine av bits */ tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2375,10 +2067,6 @@ gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_= low, TCGv r1_high, TCGv r2, =20 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - - tcg_temp_free(temp); - tcg_temp_free_i64(temp64); - tcg_temp_free_i64(temp64_2); } =20 static inline void @@ -2404,10 +2092,6 @@ gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3= , uint32_t n, uint32_t mode) tcg_gen_andi_tl(temp2, r1, 0xffff0000); tcg_gen_shli_tl(temp, r1, 16); gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free_i64(temp64); } =20 static inline void gen_abs(TCGv ret, TCGv r1) @@ -2449,23 +2133,18 @@ static inline void gen_absdif(TCGv ret, TCGv r1, TC= Gv r2) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* write back result */ tcg_gen_mov_tl(ret, result); - - tcg_temp_free(temp); - tcg_temp_free(result); } =20 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_absdif(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_absdif_ssov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) @@ -2486,16 +2165,12 @@ static inline void gen_mul_i32s(TCGv ret, TCGv r1, = TCGv r2) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(high); - tcg_temp_free(low); } =20 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_mul_i32s(ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv= r2) @@ -2517,7 +2192,6 @@ static inline void gen_muli_i64s(TCGv ret_low, TCGv r= et_high, TCGv r1, { TCGv temp =3D tcg_const_i32(con); gen_mul_i64s(ret_low, ret_high, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv= r2) @@ -2539,41 +2213,35 @@ static inline void gen_muli_i64u(TCGv ret_low, TCGv= ret_high, TCGv r1, { TCGv temp =3D tcg_const_i32(con); gen_mul_i64u(ret_low, ret_high, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_mul_ssov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_mul_suov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static void gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_= shift) { - TCGv temp =3D tcg_temp_new(); TCGv_i64 temp_64 =3D tcg_temp_new_i64(); TCGv_i64 temp2_64 =3D tcg_temp_new_i64(); =20 @@ -2626,9 +2294,6 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uin= t32_t n, uint32_t up_shift) } /* calc sav overflow bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - tcg_temp_free(temp); - tcg_temp_free_i64(temp_64); - tcg_temp_free_i64(temp2_64); } =20 static void @@ -2651,8 +2316,6 @@ gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t= n) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc sav overflow bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); } =20 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) @@ -2679,8 +2342,6 @@ static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2= , uint32_t n) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* cut halfword off */ tcg_gen_andi_tl(ret, ret, 0xffff0000); - - tcg_temp_free(temp); } =20 static inline void @@ -2691,7 +2352,6 @@ gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2700,7 +2360,6 @@ gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -2711,7 +2370,6 @@ gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2720,21 +2378,18 @@ gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1= , TCGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); - tcg_temp_free(temp); } =20 static inline void @@ -2745,7 +2400,6 @@ gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TC= Gv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2754,7 +2408,6 @@ gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static inline void @@ -2765,7 +2418,6 @@ gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, T= CGv r2_low, TCGv r2_high, tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); - tcg_temp_free_i64(temp64); } =20 static inline void @@ -2774,7 +2426,6 @@ gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, = TCGv r2_low, TCGv r2_high, { TCGv temp =3D tcg_const_i32(con); gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); - tcg_temp_free(temp); } =20 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) @@ -2787,9 +2438,6 @@ static void gen_saturate(TCGv ret, TCGv arg, int32_t = up, int32_t low) =20 /* ret =3D (sat_neg > up ) ? up : sat_neg; */ tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); - - tcg_temp_free(sat_neg); - tcg_temp_free(temp); } =20 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) @@ -2797,7 +2445,6 @@ static void gen_saturate_u(TCGv ret, TCGv arg, int32_= t up) TCGv temp =3D tcg_const_i32(up); /* sat_neg =3D (arg > up ) ? up : arg; */ tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); - tcg_temp_free(temp); } =20 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) @@ -2826,9 +2473,6 @@ static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shif= tcount) gen_shi(temp_low, temp_low, shiftcount); gen_shi(ret, temp_high, shiftcount); tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); - - tcg_temp_free(temp_low); - tcg_temp_free(temp_high); } } =20 @@ -2837,7 +2481,6 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shif= t_count) uint32_t msk, msk_start; TCGv temp =3D tcg_temp_new(); TCGv temp2 =3D tcg_temp_new(); - TCGv t_0 =3D tcg_const_i32(0); =20 if (shift_count =3D=3D 0) { /* Clear PSW.C and PSW.V */ @@ -2868,9 +2511,6 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shif= t_count) tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); /* do shift */ tcg_gen_shli_tl(ret, r1, shift_count); - - tcg_temp_free(t_max); - tcg_temp_free(t_min); } else { /* clear PSW.V */ tcg_gen_movi_tl(cpu_PSW_V, 0); @@ -2885,10 +2525,6 @@ static void gen_shaci(TCGv ret, TCGv r1, int32_t shi= ft_count) tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); /* calc sav overflow bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(t_0); } =20 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) @@ -2900,7 +2536,6 @@ static void gen_shasi(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_shas(ret, r1, temp); - tcg_temp_free(temp); } =20 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) @@ -2917,9 +2552,6 @@ static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shi= ft_count) tcg_gen_shli_tl(low, r1, shift_count); tcg_gen_shli_tl(ret, high, shift_count); tcg_gen_deposit_tl(ret, ret, low, 0, 16); - - tcg_temp_free(low); - tcg_temp_free(high); } else { low =3D tcg_temp_new(); high =3D tcg_temp_new(); @@ -2928,11 +2560,7 @@ static void gen_sha_hi(TCGv ret, TCGv r1, int32_t sh= ift_count) tcg_gen_sari_tl(low, low, -shift_count); tcg_gen_sari_tl(ret, r1, -shift_count); tcg_gen_deposit_tl(ret, ret, low, 0, 16); - - tcg_temp_free(low); - tcg_temp_free(high); } - } =20 /* ret =3D {ret[30:0], (r1 cond r2)}; */ @@ -2944,16 +2572,12 @@ static void gen_sh_cond(int cond, TCGv ret, TCGv r1= , TCGv r2) tcg_gen_shli_tl(temp, ret, 1); tcg_gen_setcond_tl(cond, temp2, r1, r2); tcg_gen_or_tl(ret, temp, temp2); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_sh_cond(cond, ret, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) @@ -2965,14 +2589,12 @@ static inline void gen_addsi(TCGv ret, TCGv r1, int= 32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_add_ssov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) { TCGv temp =3D tcg_const_i32(con); gen_helper_add_suov(ret, cpu_env, r1, temp); - tcg_temp_free(temp); } =20 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) @@ -3002,9 +2624,6 @@ static inline void gen_bit_2op(TCGv ret, TCGv r1, TCG= v r2, (*op2)(temp1 , ret, temp1); =20 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); } =20 /* ret =3D r1[pos1] op1 r2[pos2]; */ @@ -3023,9 +2642,6 @@ static inline void gen_bit_1op(TCGv ret, TCGv r1, TCG= v r2, (*op1)(ret, temp1, temp2); =20 tcg_gen_andi_tl(ret, ret, 0x1); - - tcg_temp_free(temp1); - tcg_temp_free(temp2); } =20 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv= r2, @@ -3041,9 +2657,6 @@ static inline void gen_accumulating_cond(int cond, TC= Gv ret, TCGv r1, TCGv r2, (*op)(temp, temp, temp2); /* ret =3D {ret[31:1], temp} */ tcg_gen_deposit_tl(ret, ret, temp, 0, 1); - - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void @@ -3052,7 +2665,6 @@ gen_accumulating_condi(int cond, TCGv ret, TCGv r1, i= nt32_t con, { TCGv temp =3D tcg_const_i32(con); gen_accumulating_cond(cond, ret, r1, temp, op); - tcg_temp_free(temp); } =20 /* ret =3D (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ @@ -3089,11 +2701,6 @@ static inline void gen_eqany_bi(TCGv ret, TCGv r1, i= nt32_t con) tcg_gen_or_tl(ret, b0, b1); tcg_gen_or_tl(ret, ret, b2); tcg_gen_or_tl(ret, ret, b3); - - tcg_temp_free(b0); - tcg_temp_free(b1); - tcg_temp_free(b2); - tcg_temp_free(b3); } =20 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) @@ -3111,10 +2718,8 @@ static inline void gen_eqany_hi(TCGv ret, TCGv r1, i= nt32_t con) =20 /* combine them */ tcg_gen_or_tl(ret, h0, h1); - - tcg_temp_free(h0); - tcg_temp_free(h1); } + /* mask =3D ((1 << width) -1) << pos; ret =3D (r1 & ~mask) | (r2 << pos) & mask); */ static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv= pos) @@ -3132,10 +2737,6 @@ static inline void gen_insert(TCGv ret, TCGv r1, TCG= v r2, TCGv width, TCGv pos) tcg_gen_and_tl(temp, temp, mask); tcg_gen_andc_tl(temp2, r1, mask); tcg_gen_or_tl(ret, temp, temp2); - - tcg_temp_free(mask); - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) @@ -3144,8 +2745,6 @@ static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv = r1) =20 gen_helper_bsplit(temp, r1); tcg_gen_extr_i64_i32(rl, rh, temp); - - tcg_temp_free_i64(temp); } =20 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) @@ -3154,8 +2753,6 @@ static inline void gen_unpack(TCGv rl, TCGv rh, TCGv = r1) =20 gen_helper_unpack(temp, r1); tcg_gen_extr_i64_i32(rl, rh, temp); - - tcg_temp_free_i64(temp); } =20 static inline void @@ -3169,8 +2766,6 @@ gen_dvinit_b(DisasContext *ctx, TCGv rl, TCGv rh, TCG= v r1, TCGv r2) gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); } tcg_gen_extr_i64_i32(rl, rh, ret); - - tcg_temp_free_i64(ret); } =20 static inline void @@ -3184,8 +2779,6 @@ gen_dvinit_h(DisasContext *ctx, TCGv rl, TCGv rh, TCG= v r1, TCGv r2) gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); } tcg_gen_extr_i64_i32(rl, rh, ret); - - tcg_temp_free_i64(ret); } =20 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) @@ -3200,7 +2793,6 @@ static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg= _high) /* calc SAV bit */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); tcg_gen_movi_tl(cpu_PSW_V, 0); - tcg_temp_free(temp); } =20 static void gen_calc_usb_mulr_h(TCGv arg) @@ -3215,7 +2807,6 @@ static void gen_calc_usb_mulr_h(TCGv arg) tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); /* clear V bit */ tcg_gen_movi_tl(cpu_PSW_V, 0); - tcg_temp_free(temp); } =20 /* helpers for generating program flow micro-ops */ @@ -3245,9 +2836,6 @@ static void generate_trap(DisasContext *ctx, int clas= s, int tin) gen_save_pc(ctx->base.pc_next); gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); ctx->base.is_jmp =3D DISAS_NORETURN; - - tcg_temp_free(classtemp); - tcg_temp_free(tintemp); } =20 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r= 1, @@ -3267,7 +2855,6 @@ static inline void gen_branch_condi(DisasContext *ctx= , TCGCond cond, TCGv r1, { TCGv temp =3D tcg_const_i32(r2); gen_branch_cond(ctx, cond, r1, temp, address); - tcg_temp_free(temp); } =20 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) @@ -3289,8 +2876,6 @@ static void gen_fcall_save_ctx(DisasContext *ctx) tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); tcg_gen_movi_tl(cpu_gpr_a[11], ctx->pc_succ_insn); tcg_gen_mov_tl(cpu_gpr_a[10], temp); - - tcg_temp_free(temp); } =20 static void gen_fret(DisasContext *ctx) @@ -3303,8 +2888,6 @@ static void gen_fret(DisasContext *ctx) tcg_gen_mov_tl(cpu_PC, temp); tcg_gen_exit_tb(NULL, 0); ctx->base.is_jmp =3D DISAS_NORETURN; - - tcg_temp_free(temp); } =20 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, @@ -3350,13 +2933,11 @@ static void gen_compute_branch(DisasContext *ctx, u= int32_t opc, int r1, temp =3D tcg_temp_new(); tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); - tcg_temp_free(temp); break; case OPC1_16_SBRN_JNZ_T: temp =3D tcg_temp_new(); tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); - tcg_temp_free(temp); break; /* SBR-format jumps */ case OPC1_16_SBR_JEQ: @@ -3474,7 +3055,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); } - tcg_temp_free(temp); break; /* BRN format */ case OPCM_32_BRN_JTT: @@ -3488,7 +3068,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, } else { gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); } - tcg_temp_free(temp); break; /* BRR Format */ case OPCM_32_BRR_EQ_NEQ: @@ -3553,8 +3132,6 @@ static void gen_compute_branch(DisasContext *ctx, uin= t32_t opc, int r1, tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); } - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPCM_32_BRR_JNZ: if (MASK_OP_BRR_OP2(ctx->opcode) =3D=3D OPC2_32_BRR_JNZ_A) { @@ -3609,16 +3186,12 @@ static void decode_src_opc(DisasContext *ctx, int o= p1) temp2 =3D tcg_const_tl(const4); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, temp2, cpu_gpr_d[r1]); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC1_16_SRC_CMOVN: temp =3D tcg_const_tl(0); temp2 =3D tcg_const_tl(const4); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, temp2, cpu_gpr_d[r1]); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC1_16_SRC_EQ: tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], @@ -3685,13 +3258,11 @@ static void decode_srr_opc(DisasContext *ctx, int o= p1) temp =3D tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, cpu_gpr_d[r2], cpu_gpr_d[r1]); - tcg_temp_free(temp); break; case OPC1_16_SRR_CMOVN: temp =3D tcg_const_tl(0); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, cpu_gpr_d[r2], cpu_gpr_d[r1]); - tcg_temp_free(temp); break; case OPC1_16_SRR_EQ: tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], @@ -3952,7 +3523,6 @@ static void decode_sr_accu(DisasContext *ctx) tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); /* calc sav */ tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); - tcg_temp_free(temp); break; case OPC2_16_SR_SAT_B: gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); @@ -4047,7 +3617,6 @@ static void decode_16Bit_opc(DisasContext *ctx) temp =3D tcg_temp_new(); tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; /* SLRO-format */ case OPC1_16_SLRO_LD_A: @@ -4239,8 +3808,6 @@ static void decode_abs_ldw(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); } =20 static void decode_abs_ldb(DisasContext *ctx) @@ -4272,8 +3839,6 @@ static void decode_abs_ldb(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); } =20 static void decode_abs_ldst_swap(DisasContext *ctx) @@ -4299,8 +3864,6 @@ static void decode_abs_ldst_swap(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); } =20 static void decode_abs_ldst_context(DisasContext *ctx) @@ -4360,7 +3923,6 @@ static void decode_abs_store(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_abs_storeb_h(DisasContext *ctx) @@ -4386,7 +3948,6 @@ static void decode_abs_storeb_h(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 /* Bit-format */ @@ -4486,7 +4047,6 @@ static void decode_bit_insert(DisasContext *ctx) tcg_gen_not_tl(temp, temp); } tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); - tcg_temp_free(temp); } =20 static void decode_bit_logical_t2(DisasContext *ctx) @@ -4604,7 +4164,6 @@ static void decode_bit_sh_logic1(DisasContext *ctx) } tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); - tcg_temp_free(temp); } =20 static void decode_bit_sh_logic2(DisasContext *ctx) @@ -4645,7 +4204,6 @@ static void decode_bit_sh_logic2(DisasContext *ctx) } tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); - tcg_temp_free(temp); } =20 /* BO-format */ @@ -4743,7 +4301,6 @@ static void decode_bo_addrmode_post_pre_base(DisasCon= text *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_DA_SHORTOFF: CHECK_REG_PAIR(r1); @@ -4761,7 +4318,6 @@ static void decode_bo_addrmode_post_pre_base(DisasCon= text *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_H_SHORTOFF: gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); @@ -4778,7 +4334,6 @@ static void decode_bo_addrmode_post_pre_base(DisasCon= text *ctx) temp =3D tcg_temp_new(); tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_Q_POSTINC: temp =3D tcg_temp_new(); @@ -4786,13 +4341,11 @@ static void decode_bo_addrmode_post_pre_base(DisasC= ontext *ctx) tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_Q_PREINC: temp =3D tcg_temp_new(); tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); - tcg_temp_free(temp); break; case OPC2_32_BO_ST_W_SHORTOFF: gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); @@ -4915,9 +4468,6 @@ static void decode_bo_addrmode_bitreverse_circular(Di= sasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 static void decode_bo_addrmode_ld_post_pre_base(DisasContext *ctx) @@ -4982,7 +4532,6 @@ static void decode_bo_addrmode_ld_post_pre_base(Disas= Context *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_LD_DA_SHORTOFF: CHECK_REG_PAIR(r1); @@ -5000,7 +4549,6 @@ static void decode_bo_addrmode_ld_post_pre_base(Disas= Context *ctx) tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); tcg_gen_mov_tl(cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_BO_LD_H_SHORTOFF: gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); @@ -5167,9 +4715,6 @@ static void decode_bo_addrmode_ld_bitreverse_circular= (DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 static void decode_bo_addrmode_stctx_post_pre_base(DisasContext *ctx) @@ -5178,7 +4723,7 @@ static void decode_bo_addrmode_stctx_post_pre_base(Di= sasContext *ctx) uint32_t off10; int r1, r2; =20 - TCGv temp, temp2; + TCGv temp; =20 r1 =3D MASK_OP_BO_S1D(ctx->opcode); r2 =3D MASK_OP_BO_S2(ctx->opcode); @@ -5187,7 +4732,6 @@ static void decode_bo_addrmode_stctx_post_pre_base(Di= sasContext *ctx) =20 =20 temp =3D tcg_temp_new(); - temp2 =3D tcg_temp_new(); =20 switch (op2) { case OPC2_32_BO_LDLCX_SHORTOFF: @@ -5260,8 +4804,6 @@ static void decode_bo_addrmode_stctx_post_pre_base(Di= sasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void decode_bo_addrmode_ldmst_bitreverse_circular(DisasContext *ctx) @@ -5320,10 +4862,6 @@ static void decode_bo_addrmode_ldmst_bitreverse_circ= ular(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); } =20 static void decode_bol_opc(DisasContext *ctx, int32_t op1) @@ -5341,13 +4879,11 @@ static void decode_bol_opc(DisasContext *ctx, int32= _t op1) temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); - tcg_temp_free(temp); break; case OPC1_32_BOL_LD_W_LONGOFF: temp =3D tcg_temp_new(); tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); - tcg_temp_free(temp); break; case OPC1_32_BOL_LEA_LONGOFF: tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); @@ -5474,7 +5010,6 @@ static void decode_rc_logical_shift(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_rc_accumulator(DisasContext *ctx) @@ -5674,7 +5209,6 @@ static void decode_rc_accumulator(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_rc_serviceroutine(DisasContext *ctx) @@ -5764,7 +5298,6 @@ static void decode_rcpw_insert(DisasContext *ctx) if (pos + width <=3D 32) { temp =3D tcg_const_i32(const4); tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, wi= dth); - tcg_temp_free(temp); } break; default: @@ -5807,14 +5340,10 @@ static void decode_rcrw_insert(DisasContext *ctx) tcg_gen_movi_tl(temp2, const4); tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], temp2, temp, temp3); - - tcg_temp_free(temp3); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 /* RCR format */ @@ -5847,16 +5376,12 @@ static void decode_rcr_cond_select(DisasContext *ct= x) temp2 =3D tcg_const_i32(const9); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp2); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC2_32_RCR_SELN: temp =3D tcg_const_i32(0); temp2 =3D tcg_const_i32(const9); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp2); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -6236,8 +5761,6 @@ static void decode_rr_accumulator(DisasContext *ctx) tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); - - tcg_temp_free(temp); } else { generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } @@ -6377,13 +5900,10 @@ static void decode_rr_logical_shift(DisasContext *c= tx) { uint32_t op2; int r3, r2, r1; - TCGv temp; =20 r3 =3D MASK_OP_RR_D(ctx->opcode); r2 =3D MASK_OP_RR_S2(ctx->opcode); r1 =3D MASK_OP_RR_S1(ctx->opcode); - - temp =3D tcg_temp_new(); op2 =3D MASK_OP_RR_OP2(ctx->opcode); =20 switch (op2) { @@ -6448,7 +5968,6 @@ static void decode_rr_logical_shift(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 static void decode_rr_address(DisasContext *ctx) @@ -6471,14 +5990,12 @@ static void decode_rr_address(DisasContext *ctx) temp =3D tcg_temp_new(); tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); - tcg_temp_free(temp); break; case OPC2_32_RR_ADDSC_AT: temp =3D tcg_temp_new(); tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); - tcg_temp_free(temp); break; case OPC2_32_RR_EQ_A: tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], @@ -6598,10 +6115,6 @@ static void decode_rr_divide(DisasContext *ctx) /* write result */ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); break; case OPC2_32_RR_DVINIT_H: CHECK_REG_PAIR(r3); @@ -6631,9 +6144,6 @@ static void decode_rr_divide(DisasContext *ctx) /* write result */ tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); - tcg_temp_free(temp); - tcg_temp_free(temp2); - tcg_temp_free(temp3); break; case OPC2_32_RR_DVINIT: temp =3D tcg_temp_new(); @@ -6655,8 +6165,6 @@ static void decode_rr_divide(DisasContext *ctx) tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); /* sign extend to high reg */ tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); - tcg_temp_free(temp); - tcg_temp_free(temp2); break; case OPC2_32_RR_DVINIT_U: /* overflow =3D (D[b] =3D=3D 0) */ @@ -6758,7 +6266,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MUL_H_32_LU: temp64 =3D tcg_temp_new_i64(); @@ -6766,7 +6273,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MUL_H_32_UL: temp64 =3D tcg_temp_new_i64(); @@ -6774,7 +6280,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MUL_H_32_UU: temp64 =3D tcg_temp_new_i64(); @@ -6782,7 +6287,6 @@ static void decode_rr1_mul(DisasContext *ctx) GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_LL: temp64 =3D tcg_temp_new_i64(); @@ -6793,7 +6297,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_LU: temp64 =3D tcg_temp_new_i64(); @@ -6804,7 +6307,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_UL: temp64 =3D tcg_temp_new_i64(); @@ -6815,7 +6317,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); break; case OPC2_32_RR1_MULM_H_64_UU: temp64 =3D tcg_temp_new_i64(); @@ -6826,8 +6327,6 @@ static void decode_rr1_mul(DisasContext *ctx) tcg_gen_movi_tl(cpu_PSW_V, 0); /* reset AV bit */ tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); - tcg_temp_free_i64(temp64); - break; case OPC2_32_RR1_MULR_H_16_LL: GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],= n); @@ -6848,7 +6347,6 @@ static void decode_rr1_mul(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(n); } =20 static void decode_rr1_mulq(DisasContext *ctx) @@ -6918,8 +6416,6 @@ static void decode_rr1_mulq(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 /* RR2 format */ @@ -7009,7 +6505,6 @@ static void decode_rrpw_extract_insert(DisasContext *= ctx) tcg_gen_movi_tl(temp, ((1u << width) - 1) << pos); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); - tcg_temp_free(temp); } =20 break; @@ -7058,13 +6553,11 @@ static void decode_rrr_cond_select(DisasContext *ct= x) temp =3D tcg_const_i32(0); tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2]); - tcg_temp_free(temp); break; case OPC2_32_RRR_SELN: temp =3D tcg_const_i32(0); tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2]); - tcg_temp_free(temp); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); @@ -7577,8 +7070,6 @@ static void decode_rrr1_maddq_h(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void decode_rrr1_maddsu_h(DisasContext *ctx) @@ -8061,8 +7552,6 @@ static void decode_rrr1_msubq_h(DisasContext *ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); - tcg_temp_free(temp2); } =20 static void decode_rrr1_msubad_h(DisasContext *ctx) @@ -8257,7 +7746,6 @@ static void decode_rrrr_extract_insert(DisasContext *= ctx) */ tcg_gen_movcond_tl(TCG_COND_EQ, msw, tmp_pos, zero, zero, msw); tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, msw); - tcg_temp_free(msw); } break; case OPC2_32_RRRR_EXTR: @@ -8285,8 +7773,6 @@ static void decode_rrrr_extract_insert(DisasContext *= ctx) default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(tmp_pos); - tcg_temp_free(tmp_width); } =20 /* RRRW format */ @@ -8332,8 +7818,6 @@ static void decode_rrrw_extract_insert(DisasContext *= ctx) tcg_gen_shl_tl(temp2, temp2, temp); tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); - - tcg_temp_free(temp2); break; case OPC2_32_RRRW_INSERT: temp2 =3D tcg_temp_new(); @@ -8341,13 +7825,10 @@ static void decode_rrrw_extract_insert(DisasContext= *ctx) tcg_gen_movi_tl(temp, width); tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp= 2); - - tcg_temp_free(temp2); break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } - tcg_temp_free(temp); } =20 /* SYS Format*/ @@ -8400,7 +7881,6 @@ static void decode_sys_interrupts(DisasContext *ctx) gen_set_label(l1); tcg_gen_exit_tb(NULL, 0); ctx->base.is_jmp =3D DISAS_NORETURN; - tcg_temp_free(tmp); } else { /* generate privilege trap */ } @@ -8482,9 +7962,6 @@ static void decode_32Bit_opc(DisasContext *ctx) =20 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); - - tcg_temp_free(temp2); - tcg_temp_free(temp); break; case OPC1_32_ABS_LD_Q: address =3D MASK_OP_ABS_OFF18(ctx->opcode); @@ -8493,8 +7970,6 @@ static void decode_32Bit_opc(DisasContext *ctx) =20 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); - - tcg_temp_free(temp); break; case OPC1_32_ABS_LEA: address =3D MASK_OP_ABS_OFF18(ctx->opcode); @@ -8514,9 +7989,6 @@ static void decode_32Bit_opc(DisasContext *ctx) tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); tcg_gen_ori_tl(temp2, temp2, (b << bpos)); tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); - - tcg_temp_free(temp); - tcg_temp_free(temp2); break; /* B-format */ case OPC1_32_B_CALL: @@ -8647,10 +8119,6 @@ static void decode_32Bit_opc(DisasContext *ctx) tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); =20 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); - - tcg_temp_free(temp); - tcg_temp_free(temp2); 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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rAuqxA36Y6eIMbqTaItNtybIRt8MHKjxNOtHQ8E3QbI=; b=OHJ4vhrmjd4sSrdAZYix7fGj9RhdqIJ91qEagdnhOpDahJjvFeZYjaihvdObOLCWPP UEWajW7MX9szVSUmVf07okJ7IvyKiEeyg2MDDiM1XRyQ/n+t79AgsAxZMEn2ELDiBxUR MtowVZvAYBBTP7vOPJufqhk2v8oGXXuBqEsZwKfAtB0mQhPURyLqKwU4Oa7lfjHjW+9y b2RvYUgNqywKSIJ0V8mSqTjdnxe7HTBM0zp7a/aI9EbCzXMYUEdmgRhJJpOjiyffYo0n 6zrebh/CycydAcKMU5qCf4cGE2JMyKqDApVuZGJWIjRJlJXCPDOf3ezxN0Y9aN5ydv3d Y3EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rAuqxA36Y6eIMbqTaItNtybIRt8MHKjxNOtHQ8E3QbI=; b=YteaVUfTzX2q7T/uXRJ3qKH8ZWnRsnoKt9A5FTb6v6LXOhBMyYE1Qhg2P0ytGfKFtY C1OTGUnX+4EGzYtVJnDf5EQWLIrdXeEiJWplKMn9sidKX+4EU/Bk9XiGV3CxZn5lf+c3 PQvTBSrU8U9Xpms1xskmz2/956HkddCkyVUWsQ7NioN/2fri2KjtnlpR4hXskCfP9i7x 3s98JWxrzLoROSZwOTgBWbGz3Ayy9ER6wyU4h5DcS5U6HdON1nUqbn/eNnNeMnoOKB4M tdyt76xZvc+o6WPdyD1RwLFkPYLqJmWFATc50v50Pe52eUDXrQ6CqPe8IfdEh3JwVFCG M58A== X-Gm-Message-State: AO0yUKXgxotQGtwo/ufdJC6wRrP1ykLLelf7prUrGcfUOxNqeLGcAniV pRnp7ux81VdIm8JWppSbQBlv405WCvc6iKPJ0aROOk+a X-Google-Smtp-Source: AK7set/Q3Y/ikF0cXr+q7gk4HPjno9BzXaXRg3nkO3INlBQ+k7uhZOY2Uw4wJQfraOkFaMcwkqOeqg== X-Received: by 2002:a62:3813:0:b0:5a8:9858:750a with SMTP id f19-20020a623813000000b005a89858750amr6159174pfa.13.1677953958646; Sat, 04 Mar 2023 10:19:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Stefan Hajnoczi Subject: [PATCH v3 19/20] tracing: remove transform.py Date: Sat, 4 Mar 2023 10:18:59 -0800 Message-Id: <20230304181900.1097116-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x541.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954098697100003 This file, and a couple of uses, got left behind when the tcg stuff was removed from tracetool. Fixes: 126d4123c50a ("tracing: excise the tcg related from tracetool") Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Stefan Hajnoczi --- Cc: Stefan Hajnoczi --- meson.build | 1 - scripts/tracetool/__init__.py | 23 ----- scripts/tracetool/transform.py | 168 --------------------------------- 3 files changed, 192 deletions(-) delete mode 100644 scripts/tracetool/transform.py diff --git a/meson.build b/meson.build index e533d6c95b..6bcab8bf0d 100644 --- a/meson.build +++ b/meson.build @@ -2861,7 +2861,6 @@ tracetool_depends =3D files( 'scripts/tracetool/format/log_stap.py', 'scripts/tracetool/format/stap.py', 'scripts/tracetool/__init__.py', - 'scripts/tracetool/transform.py', 'scripts/tracetool/vcpu.py' ) =20 diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__init__.py index 5393c7fc5c..33cf85e2b0 100644 --- a/scripts/tracetool/__init__.py +++ b/scripts/tracetool/__init__.py @@ -18,7 +18,6 @@ =20 import tracetool.format import tracetool.backend -import tracetool.transform =20 =20 def error_write(*lines): @@ -190,18 +189,6 @@ def casted(self): """List of argument names casted to their type.""" return ["(%s)%s" % (type_, name) for type_, name in self._args] =20 - def transform(self, *trans): - """Return a new Arguments instance with transformed types. - - The types in the resulting Arguments instance are transformed acco= rding - to tracetool.transform.transform_type. - """ - res =3D [] - for type_, name in self._args: - res.append((tracetool.transform.transform_type(type_, *trans), - name)) - return Arguments(res) - =20 class Event(object): """Event description. @@ -358,16 +345,6 @@ def api(self, fmt=3DNone): fmt =3D Event.QEMU_TRACE return fmt % {"name": self.name, "NAME": self.name.upper()} =20 - def transform(self, *trans): - """Return a new Event with transformed Arguments.""" - return Event(self.name, - list(self.properties), - self.fmt, - self.args.transform(*trans), - self.lineno, - self.filename, - self) - =20 def read_events(fobj, fname): """Generate the output for the given (format, backends) pair. diff --git a/scripts/tracetool/transform.py b/scripts/tracetool/transform.py deleted file mode 100644 index ea8b27799d..0000000000 --- a/scripts/tracetool/transform.py +++ /dev/null @@ -1,168 +0,0 @@ -# -*- coding: utf-8 -*- - -""" -Type-transformation rules. -""" - -__author__ =3D "Llu=C3=ADs Vilanova " -__copyright__ =3D "Copyright 2012-2016, Llu=C3=ADs Vilanova " -__license__ =3D "GPL version 2 or (at your option) any later version" - -__maintainer__ =3D "Stefan Hajnoczi" -__email__ =3D "stefanha@redhat.com" - - -def _transform_type(type_, trans): - if isinstance(trans, str): - return trans - elif isinstance(trans, dict): - if type_ in trans: - return _transform_type(type_, trans[type_]) - elif None in trans: - return _transform_type(type_, trans[None]) - else: - return type_ - elif callable(trans): - return trans(type_) - else: - raise ValueError("Invalid type transformation rule: %s" % trans) - - -def transform_type(type_, *trans): - """Return a new type transformed according to the given rules. - - Applies each of the transformation rules in trans in order. - - If an element of trans is a string, return it. - - If an element of trans is a function, call it with type_ as its only - argument. - - If an element of trans is a dict, search type_ in its keys. If type_ is - a key, use the value as a transformation rule for type_. Otherwise, if - None is a key use the value as a transformation rule for type_. - - Otherwise, return type_. - - Parameters - ---------- - type_ : str - Type to transform. - trans : list of function or dict - Type transformation rules. - """ - if len(trans) =3D=3D 0: - raise ValueError - res =3D type_ - for t in trans: - res =3D _transform_type(res, t) - return res - - -################################################## -# tcg -> host - -def _tcg_2_host(type_): - if type_ =3D=3D "TCGv": - # force a fixed-size type (target-independent) - return "uint64_t" - else: - return type_ - -TCG_2_HOST =3D { - "TCGv_i32": "uint32_t", - "TCGv_i64": "uint64_t", - "TCGv_ptr": "void *", - None: _tcg_2_host, - } - - -################################################## -# host -> host compatible with tcg sizes - -HOST_2_TCG_COMPAT =3D { - "uint8_t": "uint32_t", - "uint16_t": "uint32_t", - } - - -################################################## -# host/tcg -> tcg - -def _host_2_tcg(type_): - if type_.startswith("TCGv"): - return type_ - raise ValueError("Don't know how to translate '%s' into a TCG type\n" = % type_) - -HOST_2_TCG =3D { - "uint32_t": "TCGv_i32", - "uint64_t": "TCGv_i64", - "void *" : "TCGv_ptr", - "CPUArchState *": "TCGv_env", - None: _host_2_tcg, - } - - -################################################## -# tcg -> tcg helper definition - -def _tcg_2_helper_def(type_): - if type_ =3D=3D "TCGv": - return "target_ulong" - else: - return type_ - -TCG_2_TCG_HELPER_DEF =3D { - "TCGv_i32": "uint32_t", - "TCGv_i64": "uint64_t", - "TCGv_ptr": "void *", - None: _tcg_2_helper_def, - } - - -################################################## -# tcg -> tcg helper declaration - -def _tcg_2_tcg_helper_decl_error(type_): - raise ValueError("Don't know how to translate type '%s' into a TCG hel= per declaration type\n" % type_) - -TCG_2_TCG_HELPER_DECL =3D { - "TCGv" : "tl", - "TCGv_ptr": "ptr", - "TCGv_i32": "i32", - "TCGv_i64": "i64", - "TCGv_env": "env", - None: _tcg_2_tcg_helper_decl_error, - } - - -################################################## -# host/tcg -> tcg temporal constant allocation - -def _host_2_tcg_tmp_new(type_): - if type_.startswith("TCGv"): - return "tcg_temp_new_nop" - raise ValueError("Don't know how to translate type '%s' into a TCG tem= poral allocation" % type_) - -HOST_2_TCG_TMP_NEW =3D { - "uint32_t": "tcg_const_i32", - "uint64_t": "tcg_const_i64", - "void *" : "tcg_const_ptr", - None: _host_2_tcg_tmp_new, - } - - -################################################## -# host/tcg -> tcg temporal constant deallocation - -def _host_2_tcg_tmp_free(type_): - if type_.startswith("TCGv"): - return "tcg_temp_free_nop" - raise ValueError("Don't know how to translate type '%s' into a TCG tem= poral deallocation" % type_) - -HOST_2_TCG_TMP_FREE =3D { - "uint32_t": "tcg_temp_free_i32", - "uint64_t": "tcg_temp_free_i64", - "void *" : "tcg_temp_free_ptr", - None: _host_2_tcg_tmp_free, - } --=20 2.34.1 From nobody Wed May 8 15:09:19 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+8CMysm0nZW0ujd2x2qIzUk6AQce3kuPNlTpMMrNJw0=; b=p0hOZog9ngz3FphXfy2+eOPxNfLFLCNy9Hc02HYy4HjOdpdz9H37d9H3bCRPSzqBZo DjeibyCQVb7noFIptLR/QbxM0wBizeNASN//M7cHd2O8FWxu2PxU6oa+BX06EjDY/psL vUXI3IEFOabnWFQIeoJAc7fByxCDw1yx2+WtnbfAbyZ630P5YcVzxKyHt8SraDNQL4Q1 PZmY5aH2zaSNPfmLc1I/1J3fQ95woU6ZAqolVOa9a68+iC0IenNJbNHZBtLs/fSYs2/X KAwCrrl96x70GIh97Vvft9HvTtNHG6l1enHqvldvdfjDl8cIggD93LxY0Jib9chmwikj s9ZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953959; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+8CMysm0nZW0ujd2x2qIzUk6AQce3kuPNlTpMMrNJw0=; b=n8iP8TxXZhBittFv410AWBP0FVtVAMtI3/PgoisG8gnkXVL2fSQBU/pDtFPzrRRUdj PLIhvZ+PR4PMbcvvGJDgFJbDFdPgO9MuVOCiL9BJp88/aXFZ5ojDjIz0iSJYva8QW1rf +uNe/oAjRAeae21B6yPhMvGUOoxU8BU/6jsK6TppmiW0yrrICAiH7ipU9LKO90oxeHs7 9/0vKzDuiyrm031pO/5ynxlRKYpivPwrfUS8Y93sYRUmt/Blk+oyuTgvlv8V3nEtqh6n UNcWvfML6lFNG4JLxa7TpoVdP69slr9rwEzu+UBGnxYGZmrh0Hq0nV/NQq6clsLkkD6t M7hA== X-Gm-Message-State: AO0yUKWrpBa+6ZyFmgYaIUu9fs3AYxrl/5UAE/C1SSNKo6prsDwpkzKK HkrQYFjQrdM4Kpz4pUCb1eU+CyNI7zA53TsnkPxs7A== X-Google-Smtp-Source: AK7set/NxMhS05YC7ZzgJqwPrbUuz92EIHoCuXx0ryHPS1WFJUogGAasmxx2gTaS0I10rdI0sMOm1g== X-Received: by 2002:a62:5243:0:b0:5dc:6dec:e9d0 with SMTP id g64-20020a625243000000b005dc6dece9d0mr5436149pfb.3.1677953959362; Sat, 04 Mar 2023 10:19:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Peter Maydell Subject: [PATCH v3 20/20] tcg: Create tcg/tcg-temp-internal.h Date: Sat, 4 Mar 2023 10:19:00 -0800 Message-Id: <20230304181900.1097116-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: 0 X-Spam_score: -0.1 X-Spam_bar: / X-Spam_report: (-0.1 / 5.0 requ) BAYES_00=-1.9, BITCOIN_OBFU_SUBJ=1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FUZZY_BITCOIN=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954014340100001 Content-Type: text/plain; charset="utf-8" Move the tcg_temp_free_* and tcg_temp_ebb_new_* declarations and inlines to the new header. These are private to the implementation, and will prevent tcg_temp_free_* from creeping back into the guest front ends. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/tcg/tcg-temp-internal.h | 83 +++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 54 --------------------- accel/tcg/plugin-gen.c | 1 + tcg/tcg-op-gvec.c | 1 + tcg/tcg-op-vec.c | 1 + tcg/tcg-op.c | 1 + tcg/tcg.c | 1 + 7 files changed, 88 insertions(+), 54 deletions(-) create mode 100644 include/tcg/tcg-temp-internal.h diff --git a/include/tcg/tcg-temp-internal.h b/include/tcg/tcg-temp-interna= l.h new file mode 100644 index 0000000000..dded2917e5 --- /dev/null +++ b/include/tcg/tcg-temp-internal.h @@ -0,0 +1,83 @@ +/* + * TCG internals related to TCG temp allocation + * + * Copyright (c) 2008 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef TCG_TEMP_INTERNAL_H +#define TCG_TEMP_INTERNAL_H + +/* + * Allocation and freeing of EBB temps is reserved to TCG internals + */ + +void tcg_temp_free_internal(TCGTemp *); + +static inline void tcg_temp_free_i32(TCGv_i32 arg) +{ + tcg_temp_free_internal(tcgv_i32_temp(arg)); +} + +static inline void tcg_temp_free_i64(TCGv_i64 arg) +{ + tcg_temp_free_internal(tcgv_i64_temp(arg)); +} + +static inline void tcg_temp_free_i128(TCGv_i128 arg) +{ + tcg_temp_free_internal(tcgv_i128_temp(arg)); +} + +static inline void tcg_temp_free_ptr(TCGv_ptr arg) +{ + tcg_temp_free_internal(tcgv_ptr_temp(arg)); +} + +static inline void tcg_temp_free_vec(TCGv_vec arg) +{ + tcg_temp_free_internal(tcgv_vec_temp(arg)); +} + +static inline TCGv_i32 tcg_temp_ebb_new_i32(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB); + return temp_tcgv_i32(t); +} + +static inline TCGv_i64 tcg_temp_ebb_new_i64(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB); + return temp_tcgv_i64(t); +} + +static inline TCGv_i128 tcg_temp_ebb_new_i128(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB); + return temp_tcgv_i128(t); +} + +static inline TCGv_ptr tcg_temp_ebb_new_ptr(void) +{ + TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB); + return temp_tcgv_ptr(t); +} + +#endif /* TCG_TEMP_FREE_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index e8f73115ec..43ce4bfa7d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -855,35 +855,9 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t= start, intptr_t size); TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); -void tcg_temp_free_internal(TCGTemp *); TCGv_vec tcg_temp_new_vec(TCGType type); TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); =20 -static inline void tcg_temp_free_i32(TCGv_i32 arg) -{ - tcg_temp_free_internal(tcgv_i32_temp(arg)); -} - -static inline void tcg_temp_free_i64(TCGv_i64 arg) -{ - tcg_temp_free_internal(tcgv_i64_temp(arg)); -} - -static inline void tcg_temp_free_i128(TCGv_i128 arg) -{ - tcg_temp_free_internal(tcgv_i128_temp(arg)); -} - -static inline void tcg_temp_free_ptr(TCGv_ptr arg) -{ - tcg_temp_free_internal(tcgv_ptr_temp(arg)); -} - -static inline void tcg_temp_free_vec(TCGv_vec arg) -{ - tcg_temp_free_internal(tcgv_vec_temp(arg)); -} - static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offse= t, const char *name) { @@ -891,13 +865,6 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr= reg, intptr_t offset, return temp_tcgv_i32(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_i32 tcg_temp_ebb_new_i32(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I32, TEMP_EBB); - return temp_tcgv_i32(t); -} - static inline TCGv_i32 tcg_temp_new_i32(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); @@ -911,26 +878,12 @@ static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_pt= r reg, intptr_t offset, return temp_tcgv_i64(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_i64 tcg_temp_ebb_new_i64(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I64, TEMP_EBB); - return temp_tcgv_i64(t); -} - static inline TCGv_i64 tcg_temp_new_i64(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); return temp_tcgv_i64(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_i128 tcg_temp_ebb_new_i128(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, TEMP_EBB); - return temp_tcgv_i128(t); -} - static inline TCGv_i128 tcg_temp_new_i128(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); @@ -944,13 +897,6 @@ static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr= reg, intptr_t offset, return temp_tcgv_ptr(t); } =20 -/* Used only by tcg infrastructure: tcg-op.c or plugin-gen.c */ -static inline TCGv_ptr tcg_temp_ebb_new_ptr(void) -{ - TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_EBB); - return temp_tcgv_ptr(t); -} - static inline TCGv_ptr tcg_temp_new_ptr(void) { TCGTemp *t =3D tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index c42a436c0c..5efb8db258 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -44,6 +44,7 @@ */ #include "qemu/osdep.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" #include "exec/plugin-gen.h" diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 291a65c4bf..047a832f44 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 966d41d65a..0f023f42c6 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f2269a1b91..53e96b5b69 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -25,6 +25,7 @@ #include "qemu/osdep.h" #include "exec/exec-all.h" #include "tcg/tcg.h" +#include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" #include "exec/plugin-gen.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 07127bb276..a64f18db99 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -59,6 +59,7 @@ #include "elf.h" #include "exec/log.h" #include "tcg/tcg-ldst.h" +#include "tcg/tcg-temp-internal.h" #include "tcg-internal.h" #include "accel/tcg/perf.h" =20 --=20 2.34.1