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([2602:ae:154a:9f01:62b1:64d8:8207:f04e]) by smtp.gmail.com with ESMTPSA id 25-20020aa79259000000b005d866d184b5sm3529668pfp.46.2023.03.04.10.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Mar 2023 10:19:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1677953953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lgBa2ERsQgrO6e/WAUiGru/VeOh/EJOtLRcCdLzGBVc=; b=otqBSvPmnfdKY1Iz7U7v6MdYMw6A/SMC2fGUMiKJjVjPqeBwhWn01MdLYX/zObBP93 NED2qpgY8iamd5WaVOU6ZvUVGJ5r/j1iUKgH5vduajU2Bfggo5FXcJg8T/q8QDDsyL+K m/oBBCp0XhUu4CoCvE1uqKVyxVQGmvzyhnSPlR8ODw/3+/mQy1zowlWkaEPe8Rs1QMj3 9oqhQ1WNRVi9+eOEqPsbnwCpFQaLqiQIRyjrGVxWUv96bCHH8o/2SYf9dLL4ilyjM1Up B1SsyrocG3HOrfEPXqmCEOetMZpeL/UTLIoq9wYVtMkYLZyB3Md9dJsMmz514+AfZnWO Cc/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677953953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lgBa2ERsQgrO6e/WAUiGru/VeOh/EJOtLRcCdLzGBVc=; b=bi+aUOgTTkQe5X9vAp2JrRarJjDCO8pBfM2HipTexsEWCx+3q1StQek8z1/TfkWHoq 5Yd9JWkLPv7soMVwYHJkoPFb/+bXdV/s40l31Axpybddo9fqTELIft6GXJmrF3G3A+nc qQs54YjMJTLV5oKUbxtqOQ2v+h+QjyZ1ImlskiWDfJ688+QqjJAnNqgKXEPBhngbG/TN G8jwCKbUeogpXrvPyFNwQtvr6eupptiwJHw/1rG3Xyri5kDvUrVSZoYmqr6KTmzTAOK9 nwHNBMv5lkEabTHgnyHZ2FTnlFIeZixdAQp1AR0+5IvqxpMYqHQOHZySH5612gw5+tEa gl3g== X-Gm-Message-State: AO0yUKVY3hvvbj3UAfws+hjHdlUUnrcUbLgHj3XRDz1vbz+g33ofv5ez qv8Or0n/v0+RiIxR7ocDR7t3UO63clu/ur8BcesECA== X-Google-Smtp-Source: AK7set/MmyPOQ8CJO2gpyDOrFPDBmG7lqsLcPSbQ5hTN8gUu9evM07LCzbsB4EXBZeWrhX7b5srXMA== X-Received: by 2002:a05:6a21:3284:b0:cd:1709:8d57 with SMTP id yt4-20020a056a21328400b000cd17098d57mr7377037pzb.1.1677953953593; Sat, 04 Mar 2023 10:19:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: David Hildenbrand , Ilya Leoshkevich , Thomas Huth , qemu-s390x@nongnu.org Subject: [PATCH v3 13/20] target/s390x: Drop free_compare Date: Sat, 4 Mar 2023 10:18:53 -0800 Message-Id: <20230304181900.1097116-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230304181900.1097116-1-richard.henderson@linaro.org> References: <20230304181900.1097116-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1677954001511100001 Content-Type: text/plain; charset="utf-8" Translators are no longer required to free tcg temporaries. Remove the g1 and g2 members of DisasCompare, as they were used to track which temps needed to be freed. Signed-off-by: Richard Henderson Acked-by: David Hildenbrand Reviewed-by: Ilya Leoshkevich --- Cc: David Hildenbrand Cc: Ilya Leoshkevich Cc: Thomas Huth Cc: qemu-s390x@nongnu.org --- target/s390x/tcg/translate.c | 46 +----------------------------------- 1 file changed, 1 insertion(+), 45 deletions(-) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 811049ea28..76a1233946 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -156,8 +156,6 @@ struct DisasContext { typedef struct { TCGCond cond:8; bool is_64; - bool g1; - bool g2; union { struct { TCGv_i64 a, b; } s64; struct { TCGv_i32 a, b; } s32; @@ -722,7 +720,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) c->cond =3D (mask ? TCG_COND_ALWAYS : TCG_COND_NEVER); c->u.s32.a =3D cc_op; c->u.s32.b =3D cc_op; - c->g1 =3D c->g2 =3D true; c->is_64 =3D false; return; } @@ -839,7 +836,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) =20 /* Load up the arguments of the comparison. */ c->is_64 =3D true; - c->g1 =3D c->g2 =3D false; switch (old_cc_op) { case CC_OP_LTGT0_32: c->is_64 =3D false; @@ -861,13 +857,11 @@ static void disas_jcc(DisasContext *s, DisasCompare *= c, uint32_t mask) case CC_OP_FLOGR: c->u.s64.a =3D cc_dst; c->u.s64.b =3D tcg_constant_i64(0); - c->g1 =3D true; break; case CC_OP_LTGT_64: case CC_OP_LTUGTU_64: c->u.s64.a =3D cc_src; c->u.s64.b =3D cc_dst; - c->g1 =3D c->g2 =3D true; break; =20 case CC_OP_TM_32: @@ -882,7 +876,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_SUBU: c->is_64 =3D true; c->u.s64.b =3D tcg_constant_i64(0); - c->g1 =3D true; switch (mask) { case 8 | 2: case 4 | 1: /* result */ @@ -900,7 +893,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) case CC_OP_STATIC: c->is_64 =3D false; c->u.s32.a =3D cc_op; - c->g1 =3D true; switch (mask) { case 0x8 | 0x4 | 0x2: /* cc !=3D 3 */ cond =3D TCG_COND_NE; @@ -916,7 +908,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case 0x8 | 0x2: /* cc =3D=3D 0 || cc =3D=3D 2 =3D> (cc & 1) =3D=3D= 0 */ cond =3D TCG_COND_EQ; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -935,7 +926,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) break; case 0x4 | 0x1: /* cc =3D=3D 1 || cc =3D=3D 3 =3D> (cc & 1) !=3D 0= */ cond =3D TCG_COND_NE; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_andi_i32(c->u.s32.a, cc_op, 1); @@ -959,7 +949,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c,= uint32_t mask) default: /* CC is masked by something else: (8 >> cc) & mask. */ cond =3D TCG_COND_NE; - c->g1 =3D false; c->u.s32.a =3D tcg_temp_new_i32(); c->u.s32.b =3D tcg_constant_i32(0); tcg_gen_shr_i32(c->u.s32.a, tcg_constant_i32(8), cc_op); @@ -974,24 +963,6 @@ static void disas_jcc(DisasContext *s, DisasCompare *c= , uint32_t mask) c->cond =3D cond; } =20 -static void free_compare(DisasCompare *c) -{ - if (!c->g1) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.a); - } else { - tcg_temp_free_i32(c->u.s32.a); - } - } - if (!c->g2) { - if (c->is_64) { - tcg_temp_free_i64(c->u.s64.b); - } else { - tcg_temp_free_i32(c->u.s32.b); - } - } -} - /* =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D */ /* Define the insn format enumeration. */ #define F0(N) FMT_##N, @@ -1302,7 +1273,6 @@ static DisasJumpType help_branch(DisasContext *s, Dis= asCompare *c, } =20 egress: - free_compare(c); return ret; } =20 @@ -1612,8 +1582,6 @@ static DisasJumpType op_bct32(DisasContext *s, DisasO= ps *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_subi_i64(t, regs[r1], 1); @@ -1635,8 +1603,6 @@ static DisasJumpType op_bcth(DisasContext *s, DisasOp= s *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_shri_i64(t, regs[r1], 32); @@ -1659,8 +1625,6 @@ static DisasJumpType op_bct64(DisasContext *s, DisasO= ps *o) =20 c.cond =3D TCG_COND_NE; c.is_64 =3D true; - c.g1 =3D true; - c.g2 =3D false; =20 tcg_gen_subi_i64(regs[r1], regs[r1], 1); c.u.s64.a =3D regs[r1]; @@ -1680,8 +1644,6 @@ static DisasJumpType op_bx32(DisasContext *s, DisasOp= s *o) =20 c.cond =3D (s->insn->data ? TCG_COND_LE : TCG_COND_GT); c.is_64 =3D false; - c.g1 =3D false; - c.g2 =3D false; =20 t =3D tcg_temp_new_i64(); tcg_gen_add_i64(t, regs[r1], regs[r3]); @@ -1708,15 +1670,12 @@ static DisasJumpType op_bx64(DisasContext *s, Disas= Ops *o) =20 if (r1 =3D=3D (r3 | 1)) { c.u.s64.b =3D load_reg(r3 | 1); - c.g2 =3D false; } else { c.u.s64.b =3D regs[r3 | 1]; - c.g2 =3D true; } =20 tcg_gen_add_i64(regs[r1], regs[r1], regs[r3]); c.u.s64.a =3D regs[r1]; - c.g1 =3D true; =20 return help_branch(s, &c, is_imm, imm, o->in2); } @@ -1731,7 +1690,7 @@ static DisasJumpType op_cj(DisasContext *s, DisasOps = *o) if (s->insn->data) { c.cond =3D tcg_unsigned_cond(c.cond); } - c.is_64 =3D c.g1 =3D c.g2 =3D true; + c.is_64 =3D true; c.u.s64.a =3D o->in1; c.u.s64.b =3D o->in2; =20 @@ -2925,13 +2884,11 @@ static DisasJumpType op_loc(DisasContext *s, DisasO= ps *o) if (c.is_64) { tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b, o->in2, o->in1); - free_compare(&c); } else { TCGv_i32 t32 =3D tcg_temp_new_i32(); TCGv_i64 t, z; =20 tcg_gen_setcond_i32(c.cond, t32, c.u.s32.a, c.u.s32.b); - free_compare(&c); =20 t =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(t, t32); @@ -4022,7 +3979,6 @@ static DisasJumpType op_soc(DisasContext *s, DisasOps= *o) } else { tcg_gen_brcond_i32(c.cond, c.u.s32.a, c.u.s32.b, lab); } - free_compare(&c); =20 r1 =3D get_field(s, r1); a =3D get_address(s, 0, get_field(s, b2), get_field(s, d2)); --=20 2.34.1