target/arm/cpu64.c | 2 ++ target/arm/cpu_tcg.c | 66 ++++++++++++++++++++++++++++++++++++++++++ target/arm/internals.h | 2 ++ 3 files changed, 70 insertions(+)
Add implementation defined registers for neoverse-n1 which
would be accessed by TF-A. Since there is no DSU in Qemu,
CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
target/arm/cpu64.c | 2 ++
target/arm/cpu_tcg.c | 66 ++++++++++++++++++++++++++++++++++++++++++
target/arm/internals.h | 2 ++
3 files changed, 70 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4066950da1..a6ae7cafac 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -1094,6 +1094,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
/* From D5.1 AArch64 PMU register summary */
cpu->isar.reset_pmcr_el0 = 0x410c3000;
+
+ define_neoverse_n1_cp_reginfo(cpu);
}
static void aarch64_host_initfn(Object *obj)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index df0c45e523..40ec120eb2 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -150,6 +150,72 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
{
define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
}
+
+static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
+ { .name = "ATCR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ATCR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ATCR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ATCR_EL12", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "AVTCR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR2_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUACTLR3_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /*
+ * Report CPUCFR_EL1.SCU as 1, as we do not implement the DSU
+ * (and in particular its system registers).
+ */
+ { .name = "CPUCFR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
+ .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 4 },
+ { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0x961563010 },
+ { .name = "CPUPCR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 1,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPMR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 3,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPOR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 2,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPSELR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "CPUPWRCTLR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ERXPFGCDN_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 2,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ERXPFGCTL_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "ERXPFGF_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+};
+
+void define_neoverse_n1_cp_reginfo(ARMCPU *cpu)
+{
+ define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo);
+}
#endif /* !CONFIG_USER_ONLY */
/* CPU models. These are not needed for the AArch64 linux-user build. */
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 3c7341e774..0c393e971a 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1356,8 +1356,10 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
#ifdef CONFIG_USER_ONLY
static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+static inline void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) {}
#else
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+void define_neoverse_n1_cp_reginfo(ARMCPU *cpu);
#endif
bool el_is_in_host(CPUARMState *env, int el);
--
2.37.3On 3/6/23 18:14, Chen Baozi wrote:
> Add implementation defined registers for neoverse-n1 which
> would be accessed by TF-A. Since there is no DSU in Qemu,
> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
>
> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
> ---
> target/arm/cpu64.c | 2 ++
> target/arm/cpu_tcg.c | 66 ++++++++++++++++++++++++++++++++++++++++++
> target/arm/internals.h | 2 ++
> 3 files changed, 70 insertions(+)
You really need to base on upstream master, as these files have moved.
>
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 4066950da1..a6ae7cafac 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -1094,6 +1094,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
>
> /* From D5.1 AArch64 PMU register summary */
> cpu->isar.reset_pmcr_el0 = 0x410c3000;
> +
> + define_neoverse_n1_cp_reginfo(cpu);
> }
>
> static void aarch64_host_initfn(Object *obj)
> diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
> index df0c45e523..40ec120eb2 100644
> --- a/target/arm/cpu_tcg.c
> +++ b/target/arm/cpu_tcg.c
> @@ -150,6 +150,72 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
> {
> define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
> }
> +
> +static const ARMCPRegInfo neoverse_n1_cp_reginfo[] = {
This belongs in target/arm/tcg/cpu64.c, adjacent to or inside aarch64_neoverse_n1_initfn.
You do not want to match the placement of define_cortex_a72_a57_a53_cp_reginfo, because
that has a more complex usage across aarch64 kvm and tcg, along with arm32 "-cpu max".
> diff --git a/target/arm/internals.h b/target/arm/internals.h
> index 3c7341e774..0c393e971a 100644
> --- a/target/arm/internals.h
> +++ b/target/arm/internals.h
> @@ -1356,8 +1356,10 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp);
>
> #ifdef CONFIG_USER_ONLY
> static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
> +static inline void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) {}
> #else
> void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
> +void define_neoverse_n1_cp_reginfo(ARMCPU *cpu);
No need for a public declaration at all.
r~
On 3/6/23 18:29, Richard Henderson wrote: > On 3/6/23 18:14, Chen Baozi wrote: >> Add implementation defined registers for neoverse-n1 which >> would be accessed by TF-A. Since there is no DSU in Qemu, >> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. >> >> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> >> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> >> --- >> target/arm/cpu64.c | 2 ++ >> target/arm/cpu_tcg.c | 66 ++++++++++++++++++++++++++++++++++++++++++ >> target/arm/internals.h | 2 ++ >> 3 files changed, 70 insertions(+) > > You really need to base on upstream master, as these files have moved. I beg your pardon, my mistake. Only half of the patch set which moves these files was applied. I had to do my own rebase around file movement today, but these three are not yet affected. But do be aware that there is a potential conflict out there. My comments re the placement of the array still apply. r~
Hi Richard, > On Mar 7, 2023, at 10:33, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 3/6/23 18:29, Richard Henderson wrote: >> On 3/6/23 18:14, Chen Baozi wrote: >>> Add implementation defined registers for neoverse-n1 which >>> would be accessed by TF-A. Since there is no DSU in Qemu, >>> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. >>> >>> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> >>> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> >>> --- >>> target/arm/cpu64.c | 2 ++ >>> target/arm/cpu_tcg.c | 66 ++++++++++++++++++++++++++++++++++++++++++ >>> target/arm/internals.h | 2 ++ >>> 3 files changed, 70 insertions(+) >> You really need to base on upstream master, as these files have moved. > > I beg your pardon, my mistake. Only half of the patch set which moves these files was applied. I had to do my own rebase around file movement today, but these three are not yet affected. Never mind. I was aware of that. Waiting for them to be applied and then rework. > > But do be aware that there is a potential conflict out there. > > My comments re the placement of the array still apply. Ack. Cheers, Baozi.
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