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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id l8-20020a05600c4f0800b003b47b80cec3sm20355206wmq.42.2023.03.07.15.47.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:47:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0ZS9Hm8J7/tF46vAhSaD/WOKp+pKvbrSu7YOys7K80I=; b=P7g+FLLz4AJ2opVR43X9JdFJbtL+N2SE1dGOBVQn+KkSwYDAxSqfyalHC8/23Ci48j Oa/UqZsWee535+I0qpr0MnHbnRVj+pLShDI7PCNerkhFy5wy9zBVKbEsdYWuc7oIx+5o r4EOjnY4wGXfn73Dx9yqhP4BTKyJS7nX/kmXfK5aq9OgjTW1yW/CmTtOs3pCDEy7sC7w vWAzbBa+mIKnfmA7sgPr4EcLwAb97ZImSySLQbu3Yl2aXHhXkPDPMKDdfxcZBOF23qja Sc6dSSKw8/0KEXJzTH841qqlXeSNJBZMC89GjMZG5lrvdGgd1xTZ0ZSrGWwEYBk/w/P2 mhfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0ZS9Hm8J7/tF46vAhSaD/WOKp+pKvbrSu7YOys7K80I=; b=Gw58PjCI23N6MF3SGwIHSrLc9DW5DwCpCQuPwOeZIU174Ar8uNp7SfjUYJ8CK1cN4Z J/TE9esnfhDkddbZ2doVNzp8Wzf38acFN9DhCLj7I0K18ArfYmwIjA3Gfrlxcw5dzriC SrQ4JkSKeQYrMm3xAbNPnvMjDVowzy+Ip+LjLihw5Tbn77DJizUudwnAuyp64JZCUHsk vtuC1kss64oBJ8CUnY78MjmJMQlkUrUO9s/tjYWJHOqYdTYtNh/MsuKzuf7G/l9bxk+Z MUzv9zwcUepOZnwPG0Z05r8G2SpvmuJGAkwgr1BbgJ90uDGQ3KSpUItZZPjwvlenoH1M jbZw== X-Gm-Message-State: AO0yUKU2fpQQINBl+18uRyGZbbq4gjfrG0MJLMNioszoX/QB3jX3JwAM 0ppI365ux1k6iTlosG+OOIc6eTPEHdHnlVTTJkM= X-Google-Smtp-Source: AK7set8Iw1icsQw3OgpBNHBCVFh9HTpfKk8VAMygAiFo/jc4lCuZR/5OgzEfw89nIrqUsOIMc/2hAw== X-Received: by 2002:a05:600c:3b10:b0:3eb:399d:ab18 with SMTP id m16-20020a05600c3b1000b003eb399dab18mr15059809wms.35.1678232839786; Tue, 07 Mar 2023 15:47:19 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/20] docs/system: Remove "mips" board from target-mips.rst Date: Wed, 8 Mar 2023 00:46:52 +0100 Message-Id: <20230307234711.55375-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232903677100005 From: Jiaxun Yang This board had been removed long ago in commit f169413c27 ("hw/mips: Remove the 'r4k' machine") Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230202132138.30945-2-jiaxun.yang@flygoat.com> [PMD: Mention commit f169413c27] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/target-mips.rst | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/docs/system/target-mips.rst b/docs/system/target-mips.rst index 138441bdec..83239fb9df 100644 --- a/docs/system/target-mips.rst +++ b/docs/system/target-mips.rst @@ -8,8 +8,6 @@ endian options, ``qemu-system-mips``, ``qemu-system-mipsel`` ``qemu-system-mips64`` and ``qemu-system-mips64el``. Five different machine types are emulated: =20 -- A generic ISA PC-like machine \"mips\" - - The MIPS Malta prototype board \"malta\" =20 - An ACER Pica \"pica61\". This machine needs the 64-bit emulator. @@ -19,18 +17,6 @@ machine types are emulated: - A MIPS Magnum R4000 machine \"magnum\". This machine needs the 64-bit emulator. =20 -The generic emulation is supported by Debian 'Etch' and is able to -install Debian into a virtual disk image. The following devices are -emulated: - -- A range of MIPS CPUs, default is the 24Kf - -- PC style serial port - -- PC style IDE disk - -- NE2000 network card - The Malta emulation supports the following devices: =20 - Core board with MIPS 24Kf CPU and Galileo system controller --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232912; cv=none; d=zohomail.com; s=zohoarc; b=em/1fO6weWqpXbtq+xZbs2aA+WeSBFrGG2xh6ffRlv/Q4VxurHqPhG0TSVeQiz5WnjxLNv4gSnCPgt/R8pNQ8onzPaJ6cCoYQUtw0CRduIxQpa2jLxXdfDD6JKHAJum2lKtWgbYCLgHzKRlkhWeO1YchU8Kuir1ila7bMYQlWHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232912; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5kv47cNquk8yhKac7MEnq6L9Leh5mHoeFVxotW6dHYI=; b=dyZ+dp2Dzp9Ebi4tjzSJ4d4gdZPq/yIMwGNhetSlNiHp5Ah89qoFxm/FWfKORvFR6QiWB8mWubfd9SFE1PlLUu8MdWM2+aVOp3xXXRValprhQodvrs3bGTlsprXoT40iSZDAmlKPznAIcMpV9nlFQ0wRkU3AmVkmHDSot86HXa4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167823291219790.73651220271006; Tue, 7 Mar 2023 15:48:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh1m-0008PI-En; Tue, 07 Mar 2023 18:47:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh1l-0008P4-EX for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:29 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh1j-0002fG-4P for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:29 -0500 Received: by mail-wm1-x336.google.com with SMTP id m25-20020a7bcb99000000b003e7842b75f2so154046wmi.3 for ; Tue, 07 Mar 2023 15:47:26 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id u12-20020a05600c00cc00b003e1202744f2sm17648526wmm.31.2023.03.07.15.47.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:47:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5kv47cNquk8yhKac7MEnq6L9Leh5mHoeFVxotW6dHYI=; b=ZX8YkVJEV+wwuOC34Sc65TVRiVOC4ItVRt8E5WT0VZSX9Q5NM0VtQDhnbo5/jobKJX eBM6EnLYtm0TA0x7hvOZOuiFb/R4zqkRG5ngmN6kBwBDjq735D0nwP+5pCnHdknFgg1+ hD5eEoDBGce/u+8HpPyrE1zPUhr68RW5aVly/E9kYfe8n3O/PUXucd7pjoLVDWomXb/h dFAsDQdwNE5NM+xXGIskvA1Yqbkc9cciZu7w5gS5EHE60QI1oL3vh6JRMR7BxDwNp76+ 6rquXO3Nbn3YDoVHQXk8cElXF/JfNViT+calwzAWAum/zRoL3lJNpJOF0CmztTkW1WwR I5Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232845; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5kv47cNquk8yhKac7MEnq6L9Leh5mHoeFVxotW6dHYI=; b=Q7PdLxiHR4of/0H4BmdjKasoZrUg6dGqlTuzo2hjwaMzPxSPOSZIqfXq8rcYuV6DMv jCljJ7Het4e1f52Y0UGe69Ipke9D2aoCxUyDXyto2UrqiMn+IHPff/yUr8eDCoxFt8jN /LG0UOCclOm2ZkxMx7A4VfItWtZSHXF1yF0GW5g1JlG5QH7ti6PPdBnN25lrMe5+hNLc ftuN49Mq730Qf74KgytZJXflihU8Dt4OMEe57WlXHEaEV2Rrh7C9joA5STLEVP3QSNL2 GUsl798guiHbVWZGYq/++UaUoKhbT0glOYedDwd0jds7oOn8bhV2CMlRHENz8R15+FP6 qX0A== X-Gm-Message-State: AO0yUKWkHYXruaPrzVdd0PwPRucPmeK3MQaZq1EZwjw0e299XiB+RUK+ r45Zk6kgMVvWqFH+8PDGRckui+M8oTsDH/PTEiQ= X-Google-Smtp-Source: AK7set8FK5KcTxO4T50ih7nUt4Lvi0/LZ7agMeEoA69EbAxW73WGwT0wyN8uj82ieOH9LWmT3EubHA== X-Received: by 2002:a05:600c:3b0c:b0:3eb:2b88:999f with SMTP id m12-20020a05600c3b0c00b003eb2b88999fmr13796924wms.5.1678232845517; Tue, 07 Mar 2023 15:47:25 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Huacai Chen , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 02/20] target/mips: Replace [g_]assert(0) -> g_assert_not_reached() Date: Wed, 8 Mar 2023 00:46:53 +0100 Message-Id: <20230307234711.55375-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232913733100003 In order to avoid warnings such commit c0a6665c3c ("target/i386: Remove compilation errors when -Werror=3Dmaybe-uninitialized"), replace all assert(0) and g_assert(0) by g_assert_not_reached(). Remove any code following g_assert_not_reached(). See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20230221232520.14480-4-philmd@linaro.org> --- target/mips/sysemu/physaddr.c | 3 +- target/mips/tcg/msa_helper.c | 104 +++++++++++++++++----------------- 2 files changed, 53 insertions(+), 54 deletions(-) diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c index 2970df8a09..05990aa5bb 100644 --- a/target/mips/sysemu/physaddr.c +++ b/target/mips/sysemu/physaddr.c @@ -70,8 +70,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int= mmu_idx) /* is this AM mapped in current execution mode */ return ((adetlb_mask << am) < 0); default: - assert(0); - return TLBRET_BADADDR; + g_assert_not_reached(); }; } =20 diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 736283e2af..29b31d70fe 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -5333,7 +5333,7 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } msa_move_v(pwd, pwx); } @@ -5368,7 +5368,7 @@ void helper_msa_ ## helper ## _df(CPUMIPSState *env, = uint32_t df, \ } \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } =20 @@ -5413,7 +5413,7 @@ void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } } =20 @@ -5461,7 +5461,7 @@ void helper_msa_ ## helper ## _df(CPUMIPSState *env, = uint32_t df, uint32_t wd, \ } \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } =20 @@ -5511,7 +5511,7 @@ void helper_msa_ ## helper ## _df(CPUMIPSState *env, = uint32_t df, \ } \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } =20 @@ -5557,7 +5557,7 @@ static inline void msa_sld_df(uint32_t df, wr_t *pwd, } break; default: - assert(0); + g_assert_not_reached(); } } =20 @@ -5632,7 +5632,7 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, \ pwd->d[1] =3D msa_ ## func ## _df(df, pws->d[1], pwt->d[1]); \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ } =20 @@ -5771,7 +5771,7 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, uint32_t wd, \ pwd->d[1] =3D msa_ ## func ## _df(df, pwd->d[1], pws->d[1], pwt->d= [1]); \ break; = \ default: = \ - assert(0); = \ + g_assert_not_reached(); = \ } = \ } =20 @@ -5811,7 +5811,7 @@ static inline void msa_splat_df(uint32_t df, wr_t *pw= d, } break; default: - assert(0); + g_assert_not_reached(); } } =20 @@ -5869,7 +5869,7 @@ void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df= , uint32_t wd, \ MSA_LOOP_D; \ break; \ default: \ - assert(0); \ + g_assert_not_reached(); \ } \ msa_move_v(pwd, pwx); \ } @@ -6090,7 +6090,7 @@ void helper_msa_insve_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, pwd->d[n] =3D (int64_t)pws->d[0]; break; default: - assert(0); + g_assert_not_reached(); } } =20 @@ -6150,7 +6150,7 @@ void helper_msa_fill_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } } =20 @@ -6565,7 +6565,7 @@ static inline void compare_af(CPUMIPSState *env, wr_t= *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6596,7 +6596,7 @@ static inline void compare_un(CPUMIPSState *env, wr_t= *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6625,7 +6625,7 @@ static inline void compare_eq(CPUMIPSState *env, wr_t= *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6654,7 +6654,7 @@ static inline void compare_ueq(CPUMIPSState *env, wr_= t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6683,7 +6683,7 @@ static inline void compare_lt(CPUMIPSState *env, wr_t= *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6712,7 +6712,7 @@ static inline void compare_ult(CPUMIPSState *env, wr_= t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6741,7 +6741,7 @@ static inline void compare_le(CPUMIPSState *env, wr_t= *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6770,7 +6770,7 @@ static inline void compare_ule(CPUMIPSState *env, wr_= t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6799,7 +6799,7 @@ static inline void compare_or(CPUMIPSState *env, wr_t= *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6828,7 +6828,7 @@ static inline void compare_une(CPUMIPSState *env, wr_= t *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -6857,7 +6857,7 @@ static inline void compare_ne(CPUMIPSState *env, wr_t= *pwd, wr_t *pws, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, retaddr); @@ -7107,7 +7107,7 @@ void helper_msa_fadd_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7137,7 +7137,7 @@ void helper_msa_fsub_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7167,7 +7167,7 @@ void helper_msa_fmul_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7198,7 +7198,7 @@ void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7245,7 +7245,7 @@ void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7280,7 +7280,7 @@ void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7317,7 +7317,7 @@ void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7371,7 +7371,7 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7417,7 +7417,7 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df= , uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7526,7 +7526,7 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, =20 } else { =20 - assert(0); + g_assert_not_reached(); =20 } =20 @@ -7555,7 +7555,7 @@ void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t= df, uint32_t wd, FMAXMIN_A(min, max, pwx->d[0], pws->d[0], pwt->d[0], 64, status); FMAXMIN_A(min, max, pwx->d[1], pws->d[1], pwt->d[1], 64, status); } else { - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7628,7 +7628,7 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, =20 } else { =20 - assert(0); + g_assert_not_reached(); =20 } =20 @@ -7657,7 +7657,7 @@ void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t= df, uint32_t wd, FMAXMIN_A(max, min, pwx->d[0], pws->d[0], pwt->d[0], 64, status); FMAXMIN_A(max, min, pwx->d[1], pws->d[1], pwt->d[1], 64, status); } else { - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7681,7 +7681,7 @@ void helper_msa_fclass_df(CPUMIPSState *env, uint32_t= df, pwd->d[0] =3D float_class_d(pws->d[0], status); pwd->d[1] =3D float_class_d(pws->d[1], status); } else { - assert(0); + g_assert_not_reached(); } } =20 @@ -7723,7 +7723,7 @@ void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7753,7 +7753,7 @@ void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32= _t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7783,7 +7783,7 @@ void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7832,7 +7832,7 @@ void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t= df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7862,7 +7862,7 @@ void helper_msa_frcp_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7892,7 +7892,7 @@ void helper_msa_frint_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7946,7 +7946,7 @@ void helper_msa_flog2_df(CPUMIPSState *env, uint32_t = df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -7983,7 +7983,7 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t= df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -8019,7 +8019,7 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t= df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -8046,7 +8046,7 @@ void helper_msa_ffql_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 msa_move_v(pwd, pwx); @@ -8072,7 +8072,7 @@ void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 msa_move_v(pwd, pwx); @@ -8100,7 +8100,7 @@ void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, } break; default: - assert(0); + g_assert_not_reached(); } =20 check_msacsr_cause(env, GETPC()); @@ -8130,7 +8130,7 @@ void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_= t df, uint32_t wd, } break; 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id l10-20020a7bc44a000000b003e21dcccf9fsm17730941wmi.16.2023.03.07.15.47.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:47:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232851; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T8bm6uagQMSn5YcszvNvVG9S7Gfqzm98L/bweCMen+Q=; b=y0vPn78e2wbcn3wQ7XtOrvxVIH/AMVDK1mSjhG5mS4Ml+bmBQpXxv6lppKPYc0CPgq Re1YktpIUnXInvKAy6P/TnbX6uemkRbVU2heMW3cAvYvDVk7UUwuLrU7uuqNWTHSQFCW u5KxphpLXBluNn47Sq08qbcwvkGcg1CfUfHgZett7wEoew23k20l5onGSHSIFNQQJkf/ qwnpfrxfs5JKij5G4q6rQctYT1Qin3UcKuSeT8Tuxs9eVppd8DuB2q4FgYBMy/TolEqr Cbv56cdcvxuPGNKk/XVVPUHHqy6rC1cWYGOUd+qeYBP481OsBQ6hLSZsciPHXsZ693gR M9Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232851; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T8bm6uagQMSn5YcszvNvVG9S7Gfqzm98L/bweCMen+Q=; b=YkgLzoCz2UAQ3Q9aFtxh68MNkR4DYak3byuPYOXjngqLasdShswELgixbay8kwuxQP P2LqWn/533M2nwSQihNJRhO03QXlaMNtQyHLJzRKiX9I1PSmaT1+JZwaFQMbQTGptLy0 0BRgJeAr2MN2A+7bUBoyu2FSZMEOqVlfaTfT40gpZ/ZOQQdzSkyVoZzuKZsSvrZdqhXk mvb3vnqh/vx19WWE5XTTW80gFN0ZjGDy9Vp3Xcbk0RwcZlzVDTmR46OyfxRFUphXDTGk z8GW2k1Q63fQLCG9zEZ500KuKdDIjKM4GRgHqzQ8SernzJliZoM3PVRDW+DN5NCUNNiC n6Jw== X-Gm-Message-State: AO0yUKU5pKKasOgZ2C9y4ZdAV3x8TXzTe6TeeHwIYZmqgGEg5cIE72xh 2vxYgE2JCKaqgesZA7q62hFgzi1lKHn2Byg3nXc= X-Google-Smtp-Source: AK7set9DvrFZGz8AuDUAOTvhNzLg612uH/sZ7UJh3+bgQvByuoGgmEy6Ngx/NfhJJvdoAO9ROtBtRQ== X-Received: by 2002:a1c:750a:0:b0:3ea:e582:48dd with SMTP id o10-20020a1c750a000000b003eae58248ddmr13424919wmc.34.1678232851302; Tue, 07 Mar 2023 15:47:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Marcin Nowakowski , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 03/20] target/mips: Fix JALS32/J32 instruction handling for microMIPS Date: Wed, 8 Mar 2023 00:46:54 +0100 Message-Id: <20230307234711.55375-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232897923100004 From: Marcin Nowakowski microMIPS J & JAL instructions perform a jump in a 128MB region and 5 top bits of the address need to be preserved. This is different behavior compared to standard mips systems, where the jump is executed within a 256MB region. Note that microMIPS32 instruction set documentation appears to have inconsistent information regarding JALX32 instruction - it is written in the doc that: "To execute a procedure call within the current 256 MB-aligned region (...) The low 26 bits of the target address is the target field shifted left 2 bits." But the target address is already 26 bits. Moreover, the operation description indicates that 28 bits are copied, so the statement about use of 26 bits is _most likely_ incorrect and the corresponding code remains the same as for standard mips instruction set. Signed-off-by: Marcin Nowakowski Reviewed-by: Richard Henderson Message-Id: <20230216051717.3911212-2-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 8cad3d15a0..24993bc97d 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -4887,6 +4887,14 @@ static void gen_compute_branch(DisasContext *ctx, ui= nt32_t opc, break; case OPC_J: case OPC_JAL: + { + /* Jump to immediate */ + int jal_mask =3D ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000 + : 0xF0000000; + btgt =3D ((ctx->base.pc_next + insn_bytes) & jal_mask) + | (uint32_t)offset; + break; + } case OPC_JALX: /* Jump to immediate */ btgt =3D ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) | --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678233041; cv=none; d=zohomail.com; s=zohoarc; b=Mfz4+3VUXe+ka6OqAkI9KbPqYOQVjaIlNiwUF1C1cEHhkYdvwEukjT4rB+k0P8aBCgLXOuCfTA390pLXBQnm23WznmdGjhDV7QkUfcu8PqDzEmWC44eJ3yNrwCFVKador7BIgAqH7Oj/zgWu9Ot796dRkTX88lhlW6n9n1CrGtM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678233041; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OWLKTAiO22eOFIqE0r2ZKSlIhbJwHJ6ob/hpxtZPjvo=; b=V7uz9xPlHd2AciTXWl5pGhwY/vTPfUn61p1q14eglrsNSDMjSPr2fro3jO5jlOgW/Rdh8QsbnyPIlpZkTdYee9cTBSuJKjQuOlsiOHrsECZGw2FVE3W+PKejOGpVV9ugFImddfRATKvNTHZYxawrWahWhrM0AOc1BiG+lJBSTMc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 167823304109973.45738627209369; Tue, 7 Mar 2023 15:50:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh1y-0000Ly-G7; Tue, 07 Mar 2023 18:47:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh1w-0000E3-2Y for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:40 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh1u-0002go-Fi for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:39 -0500 Received: by mail-wr1-x432.google.com with SMTP id h11so13781051wrm.5 for ; Tue, 07 Mar 2023 15:47:38 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id n16-20020a5d67d0000000b002c758fe9689sm13634387wrw.52.2023.03.07.15.47.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:47:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OWLKTAiO22eOFIqE0r2ZKSlIhbJwHJ6ob/hpxtZPjvo=; b=B7M5uKYXYg1CUYNAgJgEcmrNPwzxV4Sh0R3tpe/+9j5HhW7o2FOb5FVWj4iyUE8pcc YKNUJzng8Og6kzvDYAG8nmBWoLRR/VGFGSbh0AfXp1VwwaMLXmeAhEkgPWMxNjWFvh9F tCcc6v5eOhAPmu50MfONL8j51Ip044hoOjWlII7qEs2KoGBqWbA4ZCBlUv899oU9hlvc ZcYi734tm2OUZmAsAHQFyDecalVee7LiUp7SEeE8oEp9axlzsrh7MxbdxymUn+xlEfsY r5GoD2MQtojxpQlmpIDQA32m3U0hcPtyzz8xswQpSqHH+lmIHGO0dyiGKpezJ/hSUyB5 CY+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232857; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OWLKTAiO22eOFIqE0r2ZKSlIhbJwHJ6ob/hpxtZPjvo=; b=ER1t8vg/WQkwgLZwDEJdERVYk4WEt007PdkvHvMMn5k+qw3ded1Ek9fSTuDXhp2A3E m0LbBIp09jhVaZDjR8O3FSpvJN2nkPMm8+jWMInFZA4Sb0NpYZsbQofQhkv1jbX/8Zp5 OixGTbjc5LJ4TEzKH7Aj/Q95buE/bmG3Vt8rSLEUgMhcorKeN6+M8vd6Re8vZrfAG4KO /LjydFgx/XorawfXDiGpMcA+YhPFVuWzCwYG4YJIp6JPygMFyTpft20FXkfIxAPi3ZrS 3nLiM/6i3nZSrRw+I3kqpkF3mAaLPuxUiza5loQT5VCMvpnNWWYj6YG7UDyhE41wW24C DU+g== X-Gm-Message-State: AO0yUKV9plEaUXWKdKc9KUapOX2yKqjFIyjjyaPkA/qCQTlk0mOyHLLK CoOzYUB3L09FW0r0RQRD8dXIMf2vN8OUttpZCBk= X-Google-Smtp-Source: AK7set+6BlgkUGiYDFbWRrw20oGWcF0wGMMvIxS8JnqoUffhSZpl4sv0hhyPCCqmaUVAjlW8gx+z6w== X-Received: by 2002:adf:dd4a:0:b0:2c8:14ba:459f with SMTP id u10-20020adfdd4a000000b002c814ba459fmr11256694wrm.20.1678232856935; Tue, 07 Mar 2023 15:47:36 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Marcin Nowakowski , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 04/20] target/mips: Fix SWM32 handling for microMIPS Date: Wed, 8 Mar 2023 00:46:55 +0100 Message-Id: <20230307234711.55375-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678233042428100003 From: Marcin Nowakowski SWM32 should store a sequence of 32-bit words from the GPRs, but it was incorrectly coded to store 16-bit words only. As a result, an LWM32 that usually follows would restore invalid register values. Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX") Signed-off-by: Marcin Nowakowski Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230216051717.3911212-3-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/ldst_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index d0bd0267b2..c1a8380e34 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -248,14 +248,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr,= target_ulong reglist, target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], + cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], mem_idx, GETPC()); addr +=3D 4; } } =20 if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); } } =20 --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232905; cv=none; d=zohomail.com; s=zohoarc; b=ZLFEGiO3pDemYbLXLc1d43ah//nOG2V7EV8pzcpBC5beQ7p92qIvZn1/TMfCrDic1ZIQySMixs5Bn/yEMYvpmQJSaR+BzAcsf4Wj1sivoUMNOd1P8/1Rb3BVhelCvYZyIHSWK/pN/VzmX+uukpvA9kHHgomgdGX/eyLWBws56vY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232905; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UexqQ8oqlDlV/fYFNmt7r3WxJQAbUfO1HiCV98NJrIs=; b=mb50yHYaX6r2pl5VbnWcDEFQCPwMCkytnHXXBmWxNzCNvZzyw2vUYF0/7ZaFQmnwl2gzw4p9LEnGLDmAXxuzVnnzALoJLjW6SUpXLvfy/2B+IKjEn8W5MmoFqm7xD1sp8i0WsmO+TgRVPJ0EpyKNFTjNcPk6cvDCc0Bh721nA7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678232905097578.4201037645703; Tue, 7 Mar 2023 15:48:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh23-0000q0-NR; Tue, 07 Mar 2023 18:47:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh22-0000lI-7M for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:46 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh20-0002h6-BS for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:45 -0500 Received: by mail-wr1-x435.google.com with SMTP id j2so13763271wrh.9 for ; Tue, 07 Mar 2023 15:47:43 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id w17-20020adfd4d1000000b002c6d0462163sm13738825wrk.100.2023.03.07.15.47.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:47:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UexqQ8oqlDlV/fYFNmt7r3WxJQAbUfO1HiCV98NJrIs=; b=xpHqSQjC6XxNvGRkFLSBULrlNVEwLrfAQR4at4tDWIiLtfpspvR5jbl3QyaUZnax1Z sM3l8T9ik/gJt/mAJH/Mva11HaqEw8sr2s+/infKaLe0L0A4ETxhdf4yclSEmlY1Sq7D /F3Dwlk04isG+Zh6SOFypAohSGzKB68n5Yov4jP+0b1iOnU9+Z9O2dRDJEM4sFp1tf+0 NRU/aVDe8JZy65iWLNUwWQTmEdc/eYr2BlvXWRmFqtUUGapHCruSe/4c/g7HU6Wn7gDQ 4bG/8kvIqdKnXMBxE5DtxpUrHIw2uiHOTrxV8MdIKz/dzZ2yRaJ9VkVQ0qzCH/L85YHs /3KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UexqQ8oqlDlV/fYFNmt7r3WxJQAbUfO1HiCV98NJrIs=; b=WgzAb3Y6gJEQE1+E75R2uoaTEEWlahcPKZf1Q3xucVz5rq1OSPogOyBNvGRnrbVtyS 3qBbFHVfQaOrXtef0xtC85QsmXBDiVPNvejFA9R5zyr9IxmV4CLoQMXqR1z5u1TP4Cox vw5ZoG1AeDeJ2VSNm34ScYya89BJVTw0ByKH/M52B4rLjLx6Lbjyuz7koxLuwTDlT8m4 Ap3LefEy54QCKUuJH6tzI9I+x//HAiTr/HBsHxgPVXTARujzTUg6uI6SwaDOvBxyKC45 3oyuVoJQqSXfdK8OM1bdGg6Te0p00Sc0YH6YOKbx0dwTUJUaal/B48x9If/PQcJK1fU1 xE0w== X-Gm-Message-State: AO0yUKU8ztFdnx/2KiFbDSX1Ftma3z5mEsEvBMS82ApCGx0p29U53jMa EGBBYeBbBu5xA5eayL70SvaOVhbEpLKPYxvxaPk= X-Google-Smtp-Source: AK7set8h9djBO4YR7FnvSTNruVytS5s4381JUCTLlLdU8ofPvXLMnm4F0ywUwwihVTaPcsuegaJHhg== X-Received: by 2002:adf:ea47:0:b0:2cb:4df5:932d with SMTP id j7-20020adfea47000000b002cb4df5932dmr9905010wrn.22.1678232862757; Tue, 07 Mar 2023 15:47:42 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Marcin Nowakowski , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 05/20] target/mips: Implement CP0.Config7.WII bit support Date: Wed, 8 Mar 2023 00:46:56 +0100 Message-Id: <20230307234711.55375-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232905936100009 From: Marcin Nowakowski Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14K(c) and P5600. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230216051717.3911212-4-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-defs.c.inc | 3 +++ target/mips/cpu.c | 4 +++- target/mips/cpu.h | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 480e60aeec..fdde04dfb9 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -333,6 +333,7 @@ const mips_def_t mips_defs[] =3D .CP0_Config1 =3D MIPS_CONFIG1, .CP0_Config2 =3D MIPS_CONFIG2, .CP0_Config3 =3D MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_V= Int), + .CP0_Config7 =3D 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask =3D 0, .CP0_LLAddr_shift =3D 4, .SYNCI_Step =3D 32, @@ -354,6 +355,7 @@ const mips_def_t mips_defs[] =3D (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 =3D MIPS_CONFIG2, .CP0_Config3 =3D MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_V= Int), + .CP0_Config7 =3D 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask =3D 0, .CP0_LLAddr_shift =3D 4, .SYNCI_Step =3D 32, @@ -392,6 +394,7 @@ const mips_def_t mips_defs[] =3D .CP0_Config5_rw_bitmask =3D (1 << CP0C5_K) | (1 << CP0C5_CV) | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | (1 << CP0C5_FRE) | (1 << CP0C5_UFR), + .CP0_Config7 =3D 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask =3D 0, .CP0_LLAddr_shift =3D 0, .SYNCI_Step =3D 32, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 05caf54999..543da911e3 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -143,11 +143,13 @@ static bool mips_cpu_has_work(CPUState *cs) /* * Prior to MIPS Release 6 it is implementation dependent if non-enabl= ed * interrupts wake-up the CPU, however most of the implementations only - * check for interrupts that can be taken. + * check for interrupts that can be taken. For pre-release 6 CPUs, + * check for CP0 Config7 'Wait IE ignore' bit. */ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || + (env->CP0_Config7 & (1 << CP0C7_WII)) || (env->insn_flags & ISA_MIPS_R6)) { has_work =3D true; } diff --git a/target/mips/cpu.h b/target/mips/cpu.h index caf2b06911..142c55af47 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -980,6 +980,7 @@ typedef struct CPUArchState { #define CP0C6_DATAPREF 0 int32_t CP0_Config7; int64_t CP0_Config7_rw_bitmask; +#define CP0C7_WII 31 #define CP0C7_NAPCGEN 2 #define CP0C7_UNIMUEN 1 #define CP0C7_VFPUCGEN 0 --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232991; cv=none; d=zohomail.com; s=zohoarc; b=ekb/QUPK1D/SnM1r65lR/N9rAlmWGPe0hmNXhyuxcBpE3r5NDAQyhon9O/+Rx0BaksHuhQG9bHSxuhbusE4rY2yZTRguIteE5axE2XWRhBcWjVLk20ZW8bGrM453tkelcUNl8cUfSSGgqClbHk+z3x2WDx9lTq9pNWQwmcUrTd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232991; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xzhjArs2G8Y1PX8+/j/k05IJYSC1IAa/Noqj1UMnTIQ=; b=ekxBKfq42EF5/Tb0eMTYiLQc0u9jKFHazpmBJq6c/Lv0rmt2+OKTRBilHLuk4SWRUIqcLLZ11xG4V2IKGqeTC+6cMBVSzLmbDS7Puzg+5JajeNprOHDbnsGf9shK7vBYrO1lT/rYf6fyEhhtHr9VUa+VY2WEgS6WJCmiPxnT8Fk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678232991558887.0017619102786; Tue, 7 Mar 2023 15:49:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh2D-0000vZ-6Y; Tue, 07 Mar 2023 18:47:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh2B-0000v8-Kp for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:55 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh26-0002ha-CF for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:47:55 -0500 Received: by mail-wm1-x32f.google.com with SMTP id j19-20020a05600c1c1300b003e9b564fae9so176630wms.2 for ; Tue, 07 Mar 2023 15:47:49 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232992216100001 From: Marcin Nowakowski Signed-off-by: Marcin Nowakowski Suggested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230216051717.3911212-5-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu-defs.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index fdde04dfb9..d45f245a67 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -332,7 +332,10 @@ const mips_def_t mips_defs[] =3D (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), .CP0_Config1 =3D MIPS_CONFIG1, .CP0_Config2 =3D MIPS_CONFIG2, - .CP0_Config3 =3D MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_V= Int), + .CP0_Config3 =3D MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_V= Int) | + (1 << CP0C3_M), + .CP0_Config4 =3D MIPS_CONFIG4 | (1 << CP0C4_M), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_NFExists), .CP0_Config7 =3D 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask =3D 0, .CP0_LLAddr_shift =3D 4, @@ -354,7 +357,10 @@ const mips_def_t mips_defs[] =3D (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA)= | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), .CP0_Config2 =3D MIPS_CONFIG2, - .CP0_Config3 =3D MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_V= Int), + .CP0_Config3 =3D MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_V= Int) | + (1 << CP0C3_M), + .CP0_Config4 =3D MIPS_CONFIG4 | (1 << CP0C4_M), + .CP0_Config5 =3D MIPS_CONFIG5 | (1 << CP0C5_NFExists), .CP0_Config7 =3D 1 << CP0C7_WII, .CP0_LLAddr_rw_bitmask =3D 0, .CP0_LLAddr_shift =3D 4, --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id j40-20020a05600c1c2800b003dd1bd0b915sm19754812wms.22.2023.03.07.15.47.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:47:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xzxFCJKLt3Na/5rQCwl0V5d3Jw1oq9RgUj/hKadUoGs=; b=PwoD67FDsHIV+nzpgsYFNh45Mz6rLBIQdqMntfoKEz3ZxVNBZ7Rs7Tc2zpRuDbSyPe yzToc9Gz8h8nQ/VpGSNUVq7OF8kGOJuOWXlJqMdQHsHK4nk3yD6VqVc2rPeImzDHZyi/ JhMugReFnyuBtIEPrnlfsxkS+kFv4kgeyMT3u0S3m+SxJx9Sxs3Egljk/xslP5QeTg/o +XGFlKXGyB0dwPIkkvH3M9zbRUvKBQ6dHXxkQRaQC5N3iLy86DOPlyDrqnaQIttf4TjO xTp/Q2htYKvYV4NmfRmdpFGtyzBIW65qi3viuuOsyuxdjxSmA++4ql7mdIFMdSrbDmIc hoaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xzxFCJKLt3Na/5rQCwl0V5d3Jw1oq9RgUj/hKadUoGs=; b=e8jW/71WimQJO3EEDY9D+4RZoIAL2htrtubHDNWPSN17y+zflz+QX+5B7GR2NzSsK7 Bc3FOJeRECyZdBz4uv7L8+BUy6ABWhF8FxxsI47BODzfLFWwoOnG3HrvgnbwvnT4U+0F 40k89jPkKV+3gSBrMeGnxLlrN5gk2M9aPikj5s7HvY+RXvF6za570pT8EZsYaBu8ZsOj XhVDq2o5rOvKRlgHFZlsCH8X+1MrUaCkfVauXAYVLOcr9gkY8+z1IBVEZmv24GlI9l10 kbIWTVXw7cbJhP++sVzxP7f6TbKVjA8GD5BzIIPQYBAtFJEyEbZloTMF8yS5UZojvmax tQEA== X-Gm-Message-State: AO0yUKVIFvIg3yD8b1G1WeCsg77OGfmhSHtmW5/0XGTyq0obgnyJ7xfE jopbDDFOkSr3Z2SQrnj5CsZ7LvuFoA/gCSWYKXI= X-Google-Smtp-Source: AK7set93tt7XpxzDagdNh8gfRszJm2C2ZB/HgE90bmxPlEZGU4M9xJh7Dc+sWFThqurioXhRkO9jzg== X-Received: by 2002:a05:600c:5107:b0:3eb:2de9:8af3 with SMTP id o7-20020a05600c510700b003eb2de98af3mr13691010wms.23.1678232874842; Tue, 07 Mar 2023 15:47:54 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paul Burton , Aleksandar Rikalo , Aurelien Jarno , Jiaxun Yang Subject: [PULL 07/20] hw/mips: Declare all length properties as unsigned Date: Wed, 8 Mar 2023 00:46:58 +0100 Message-Id: <20230307234711.55375-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232897854100003 Some length properties are signed, other unsigned: hw/mips/cps.c:183: DEFINE_PROP_UINT32("num-vp", MIPSCPSState, num_vp, = 1), hw/mips/cps.c:184: DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq= , 256), hw/misc/mips_cmgcr.c:215: DEFINE_PROP_INT32("num-vp", MIPSGCRState, nu= m_vps, 1), hw/misc/mips_cpc.c:167: DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num= _vp, 0x1), hw/misc/mips_itu.c:552: DEFINE_PROP_INT32("num-fifo", MIPSITUState, nu= m_fifo, hw/misc/mips_itu.c:554: DEFINE_PROP_INT32("num-semaphores", MIPSITUSta= te, Since negative values are not used (the minimum is '0'), unify by declaring all properties as unsigned. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230203113650.78146-9-philmd@linaro.org> --- hw/intc/mips_gic.c | 4 ++-- hw/mips/boston.c | 2 +- hw/mips/cps.c | 12 ++++++------ hw/mips/malta.c | 2 +- hw/misc/mips_cmgcr.c | 2 +- hw/misc/mips_itu.c | 4 ++-- include/hw/intc/mips_gic.h | 4 ++-- include/hw/misc/mips_cmgcr.h | 2 +- include/hw/misc/mips_itu.h | 4 ++-- 9 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index bda4549925..4bdc3b1bd1 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -439,8 +439,8 @@ static void mips_gic_realize(DeviceState *dev, Error **= errp) } =20 static Property mips_gic_properties[] =3D { - DEFINE_PROP_INT32("num-vp", MIPSGICState, num_vps, 1), - DEFINE_PROP_INT32("num-irq", MIPSGICState, num_irq, 256), + DEFINE_PROP_UINT32("num-vp", MIPSGICState, num_vps, 1), + DEFINE_PROP_UINT32("num-irq", MIPSGICState, num_irq, 256), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/mips/boston.c b/hw/mips/boston.c index a9d87f3437..21ad844519 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -702,7 +702,7 @@ static void boston_mach_init(MachineState *machine) object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS= ); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, &error_fatal); - object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, + object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", qdev_get_clock_out(dev, "cpu-refclk")); diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 2b436700ce..38acc57468 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -114,9 +114,9 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU= ); - object_property_set_int(OBJECT(&s->itu), "num-fifo", 16, + object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); - object_property_set_int(OBJECT(&s->itu), "num-semaphores", 16, + object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, &error_abort); object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_pre= sent, &error_abort); @@ -133,7 +133,7 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) =20 /* Cluster Power Controller */ object_initialize_child(OBJECT(dev), "cpc", &s->cpc, TYPE_MIPS_CPC); - object_property_set_int(OBJECT(&s->cpc), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp, &error_abort); object_property_set_int(OBJECT(&s->cpc), "vp-start-running", 1, &error_abort); @@ -146,9 +146,9 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) =20 /* Global Interrupt Controller */ object_initialize_child(OBJECT(dev), "gic", &s->gic, TYPE_MIPS_GIC); - object_property_set_int(OBJECT(&s->gic), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp, &error_abort); - object_property_set_int(OBJECT(&s->gic), "num-irq", 128, + object_property_set_uint(OBJECT(&s->gic), "num-irq", 128, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { return; @@ -161,7 +161,7 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) gcr_base =3D env->CP0_CMGCRBase << 4; =20 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); - object_property_set_int(OBJECT(&s->gcr), "num-vp", s->num_vp, + object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, &error_abort); object_property_set_int(OBJECT(&s->gcr), "gcr-rev", 0x800, &error_abort); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ec172b111a..af9021316d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1066,7 +1066,7 @@ static void create_cps(MachineState *ms, MaltaState *= s, object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type, &error_fatal); - object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, + object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index 3c8b37f700..66eb11662c 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -212,7 +212,7 @@ static const VMStateDescription vmstate_mips_gcr =3D { }; =20 static Property mips_gcr_properties[] =3D { - DEFINE_PROP_INT32("num-vp", MIPSGCRState, num_vps, 1), + DEFINE_PROP_UINT32("num-vp", MIPSGCRState, num_vps, 1), DEFINE_PROP_INT32("gcr-rev", MIPSGCRState, gcr_rev, 0x800), DEFINE_PROP_UINT64("gcr-base", MIPSGCRState, gcr_base, GCR_BASE_ADDR), DEFINE_PROP_LINK("gic", MIPSGCRState, gic_mr, TYPE_MEMORY_REGION, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index badef5c214..a06cdd10ea 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -549,9 +549,9 @@ static void mips_itu_reset(DeviceState *dev) } =20 static Property mips_itu_properties[] =3D { - DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo, + DEFINE_PROP_UINT32("num-fifo", MIPSITUState, num_fifo, ITC_FIFO_NUM_MAX), - DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores, + DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), DEFINE_PROP_END_OF_LIST(), diff --git a/include/hw/intc/mips_gic.h b/include/hw/intc/mips_gic.h index eeb136e261..5e4c71edd4 100644 --- a/include/hw/intc/mips_gic.h +++ b/include/hw/intc/mips_gic.h @@ -211,8 +211,8 @@ struct MIPSGICState { /* GIC VP Timer */ MIPSGICTimerState *gic_timer; =20 - int32_t num_vps; - int32_t num_irq; + uint32_t num_vps; + uint32_t num_irq; }; =20 #endif /* MIPS_GIC_H */ diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h index 9fa58942d7..db4bf5f449 100644 --- a/include/hw/misc/mips_cmgcr.h +++ b/include/hw/misc/mips_cmgcr.h @@ -75,7 +75,7 @@ struct MIPSGCRState { SysBusDevice parent_obj; =20 int32_t gcr_rev; - int32_t num_vps; + uint32_t num_vps; hwaddr gcr_base; MemoryRegion iomem; MemoryRegion *cpc_mr; diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index 50d961106d..ab6d286c38 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -57,8 +57,8 @@ struct MIPSITUState { SysBusDevice parent_obj; /*< public >*/ =20 - int32_t num_fifo; - int32_t num_semaphores; + uint32_t num_fifo; + uint32_t num_semaphores; =20 /* ITC Storage */ ITCStorageCell *cell; --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id l36-20020a05600c08a400b003eb39e60ec9sm13614767wmp.36.2023.03.07.15.47.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/rE0urdUg8ztCeuYXEZ0c5lKROu4bt0tiIslFCNA6KE=; b=GDhLHwXi3QjkymivHhG25sAsjjzHeLXUz9xNPuGTmEZLQSGjw2mqG8Ddkq+RiWZcbf 1Lxl3AZ0ESDNN66NgVdGec0O3jm8HnxHZg1L0F0vxh6Dc3cO48duqOcwSQlcvi95uug3 t1F6Rcw+maoXiPdELw/rnIRi9WlvWqg+26x/sgD/37lkBh1iE93yYWxmB/pHVNztV6pc EuxzODzUtKCGI++P2xKjQCHKN6R3wES9Z7CdyGr4DCTZILM3R8vpyKW6IeQo/2D6rtbD tzRY+MhIPE/uNdsQ2h4/DvSijR/8YfQ8EFTRwLoadJyGa6Yu/Ezm+DGLe/INiAfhtBBX 8n8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232880; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/rE0urdUg8ztCeuYXEZ0c5lKROu4bt0tiIslFCNA6KE=; b=BFzKYJnN+Pl4tBUmB0hCiybcW1sgcde3/+4hGodYB9PZUbQAUBESdSMCpwaL4tdAf5 5wumf9SZmiF+mhfqILVz4m5qC/BQT7v0/3uMWGeYu+yroeL2O27SZsbOl/WftzQVz6kL L4LDdvMPduus2QYigw9a8vd3xph9Y4tuAyB4+bNXIduJqnabDi+j/bq/3j6PldcTunqj BeJ7DYW+9J6yH1Fr33ceeRMhUWS78hxA45tolhs2KYHuU5xVgMWuuxi6D5xfpRl/PHje 31B08E8htY0i8MmfkwAV6McqCozRS1a8freM5cpc3pJhsBOUlBfMnAewsnpFmG5YJoqJ XjYw== X-Gm-Message-State: AO0yUKWJcm3IWBgp+HoP/2GVLEu7qHGCTh/6bfq+d5VvzZyYKIiF5iwP BnaaadjssjXH0TT7PSd1VoBIzpS+28QozY10+Is= X-Google-Smtp-Source: AK7set9QSK6uLtK87NsklnOsIKpAViWwu5PcIhKeN8GGqFeu15n/68mgQeyfLVgOmRHz3qAouxVLRw== X-Received: by 2002:a05:600c:3549:b0:3eb:55d2:9c4c with SMTP id i9-20020a05600c354900b003eb55d29c4cmr11470040wmq.16.1678232880551; Tue, 07 Mar 2023 15:48:00 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang Subject: [PULL 08/20] hw/mips/itu: Pass SAAR using QOM link property Date: Wed, 8 Mar 2023 00:46:59 +0100 Message-Id: <20230307234711.55375-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232974144100003 QOM objects shouldn't access each other internals fields except using the QOM API. mips_cps_realize() instantiates a TYPE_MIPS_ITU object, and directly sets the 'saar' pointer: if (saar_present) { s->itu.saar =3D &env->CP0_SAAR; } In order to avoid that, pass the MIPS_CPU object via a QOM link property, and set the 'saar' pointer in mips_itu_realize(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Jiaxun Yang Reviewed-by: Jiaxun Yang Message-Id: <20230203113650.78146-10-philmd@linaro.org> --- hw/mips/cps.c | 23 ++++++----------------- hw/misc/mips_itu.c | 26 ++++++++++++++++++-------- include/hw/misc/mips_itu.h | 5 ++--- 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 38acc57468..2b5269ebf1 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -66,20 +66,17 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env) static void mips_cps_realize(DeviceState *dev, Error **errp) { MIPSCPSState *s =3D MIPS_CPS(dev); - CPUMIPSState *env; - MIPSCPU *cpu; - int i; target_ulong gcr_base; bool itu_present =3D false; - bool saar_present =3D false; =20 if (!clock_get(s->clock)) { error_setg(errp, "CPS input clock is not connected to an output cl= ock"); return; } =20 - for (i =3D 0; i < s->num_vp; i++) { - cpu =3D MIPS_CPU(object_new(s->cpu_type)); + for (int i =3D 0; i < s->num_vp; i++) { + MIPSCPU *cpu =3D MIPS_CPU(object_new(s->cpu_type)); + CPUMIPSState *env =3D &cpu->env; =20 /* All VPs are halted on reset. Leave powering up to CPC. */ if (!object_property_set_bool(OBJECT(cpu), "start-powered-off", tr= ue, @@ -97,7 +94,6 @@ static void mips_cps_realize(DeviceState *dev, Error **er= rp) cpu_mips_irq_init_cpu(cpu); cpu_mips_clock_init(cpu); =20 - env =3D &cpu->env; if (cpu_mips_itu_supported(env)) { itu_present =3D true; /* Attach ITC Tag to the VP */ @@ -107,22 +103,15 @@ static void mips_cps_realize(DeviceState *dev, Error = **errp) qemu_register_reset(main_cpu_reset, cpu); } =20 - cpu =3D MIPS_CPU(first_cpu); - env =3D &cpu->env; - saar_present =3D (bool)env->saarp; - /* Inter-Thread Communication Unit */ if (itu_present) { object_initialize_child(OBJECT(dev), "itu", &s->itu, TYPE_MIPS_ITU= ); + object_property_set_link(OBJECT(&s->itu), "cpu[0]", + OBJECT(first_cpu), &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16, &error_abort); object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16, &error_abort); - object_property_set_bool(OBJECT(&s->itu), "saar-present", saar_pre= sent, - &error_abort); - if (saar_present) { - s->itu.saar =3D &env->CP0_SAAR; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->itu), errp)) { return; } @@ -158,7 +147,7 @@ static void mips_cps_realize(DeviceState *dev, Error **= errp) sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic)= , 0)); =20 /* Global Configuration Registers */ - gcr_base =3D env->CP0_CMGCRBase << 4; + gcr_base =3D MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4; =20 object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR); object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp, diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index a06cdd10ea..0eda302db4 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -93,10 +93,10 @@ void itc_reconfigure(MIPSITUState *tag) uint64_t size =3D (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); bool is_enabled =3D (am[0] & ITC_AM0_EN_MASK) !=3D 0; =20 - if (tag->saar_present) { - address =3D ((*(uint64_t *) tag->saar) & 0xFFFFFFFFE000ULL) << 4; - size =3D 1ULL << ((*(uint64_t *) tag->saar >> 1) & 0x1f); - is_enabled =3D *(uint64_t *) tag->saar & 1; + if (tag->saar) { + address =3D (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4; + size =3D 1ULL << ((tag->saar[0] >> 1) & 0x1f); + is_enabled =3D tag->saar[0] & 1; } =20 memory_region_transaction_begin(); @@ -157,7 +157,7 @@ static inline ITCView get_itc_view(hwaddr addr) static inline int get_cell_stride_shift(const MIPSITUState *s) { /* Minimum interval (for EntryGain =3D 0) is 128 B */ - if (s->saar_present) { + if (s->saar) { return 7 + ((s->icr0 >> ITC_ICR0_BLK_GRAIN) & ITC_ICR0_BLK_GRAIN_MASK); } else { @@ -515,6 +515,7 @@ static void mips_itu_init(Object *obj) static void mips_itu_realize(DeviceState *dev, Error **errp) { MIPSITUState *s =3D MIPS_ITU(dev); + CPUMIPSState *env; =20 if (s->num_fifo > ITC_FIFO_NUM_MAX) { error_setg(errp, "Exceed maximum number of FIFO cells: %d", @@ -526,6 +527,15 @@ static void mips_itu_realize(DeviceState *dev, Error *= *errp) s->num_semaphores); return; } + if (!s->cpu0) { + error_setg(errp, "Missing 'cpu[0]' property"); + return; + } + + env =3D &s->cpu0->env; + if (env->saarp) { + s->saar =3D env->CP0_SAAR; + } =20 s->cell =3D g_new(ITCStorageCell, get_num_cells(s)); } @@ -534,8 +544,8 @@ static void mips_itu_reset(DeviceState *dev) { MIPSITUState *s =3D MIPS_ITU(dev); =20 - if (s->saar_present) { - *(uint64_t *) s->saar =3D 0x11 << 1; + if (s->saar) { + s->saar[0] =3D 0x11 << 1; s->icr0 =3D get_num_cells(s) << ITC_ICR0_CELL_NUM; } else { s->ITCAddressMap[0] =3D 0; @@ -553,7 +563,7 @@ static Property mips_itu_properties[] =3D { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_BOOL("saar-present", MIPSITUState, saar_present, false), + DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU = *), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/misc/mips_itu.h b/include/hw/misc/mips_itu.h index ab6d286c38..35218b2d14 100644 --- a/include/hw/misc/mips_itu.h +++ b/include/hw/misc/mips_itu.h @@ -72,9 +72,8 @@ struct MIPSITUState { uint64_t icr0; =20 /* SAAR */ - bool saar_present; - void *saar; - + uint64_t *saar; + MIPSCPU *cpu0; }; =20 /* Get ITC Configuration Tag memory region. */ --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232900; cv=none; d=zohomail.com; s=zohoarc; b=RmQY7IARwhqyPgSQAmg114opoTio7yQu4AZBIoAfI5GAJlKWgKfGJf6XqamXj+l2L+MQ7T3WwNLoRy/lkYmUJGFfCb2uT6MJGc/iIy7YWFPOYvgtAEPkd7uSfPjYmnBcsr7Qa52DvxqF6oxPH0GZmmGiUEaddleVG6c+OZYlQMg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232900; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id l13-20020adfe58d000000b002c569acab1esm13729260wrm.73.2023.03.07.15.48.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wq29WJt1laPzE2bHEihgtyn5T2vm3Jo6XB+Kog9d3Iw=; b=w1Gy5vsUEfSqRnLfEPGbFFWtL86IBn3FwT3iBIF8AvZjsrofTQHbaJrHAsobCOZc5X K2NEt59of3uLkdmJhP+QUuk4phOovugZzHj7ygBhCbU7y6KFQR0zrONAB5MkmnvdRM27 CB3j17FdRcoXSwSZlWHTBUssb8pjyzFZZ/0KA+ucUpgN2cry3i39PSsYSKwU6UhmnA5W dlyl1r2Qk8x+d/PcbAiuNVMTDSesEnKfXmsMfOeUeZDxqicVgGlxlVbHi5EvgiTAFEgp eLS8TTG2o/uNk98vy99gZXVS1aQ3AriLV+dhNAqZCDQV02HenfzeddN0ZAzP8aYrRqgo mJTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wq29WJt1laPzE2bHEihgtyn5T2vm3Jo6XB+Kog9d3Iw=; b=N7smRDV0GWk9zcYl/GhgbC5xKess6QaDZtv0mrpFNV0vL5hTBJepgyyUntNhJ4zv6n Pb7gxyVUo591+hy85CzYncf5VdqVQAECmcM1UPuwS9o0J6SWTpgPWbtsIX4EGesd9DjK aoTgG/Mvp+IAWD36/Kpgi0WO5n2QsxbbSsoNcgmswfSd2Ze5fwkLZGBMDjxijy7l4tVI CmaQ/A4UgkG9s/prqA/VE5KFCtRxty1lKGrIU/NiQ3mn9Duj3vu5hDI7Q4T9NOU1PFpu wdCJheSlqDdo0zYEY5MUHossl8iRndof2OkxTa6C14XDm86LGpB4akMVMjM8x2igRR4D lDuQ== X-Gm-Message-State: AO0yUKXUaEBcmCF8NjtDSR+HdDQo0AQriv2pwjRrPY1vdLfnxBu0XWnA 6vQseEmnNQF6qY5dRSPx4cMQzm29l76roTQzxNs= X-Google-Smtp-Source: AK7set96lqYGxmJMa1ktJzF0cfxhkzACLk/7Qb/McBsMDNSoPmyA+xUwHqsSmWXjdiMk3hYhbrMu6A== X-Received: by 2002:a5d:664e:0:b0:2cd:defe:cfd3 with SMTP id f14-20020a5d664e000000b002cddefecfd3mr11249576wrw.30.1678232886458; Tue, 07 Mar 2023 15:48:06 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , Bernhard Beschow , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PULL 09/20] Revert "hw/isa/i82378: Remove intermediate IRQ forwarder" Date: Wed, 8 Mar 2023 00:47:00 +0100 Message-Id: <20230307234711.55375-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232901834100001 To be 'usable', QDev objects (which are QOM objects) must be 1/ initialized (at this point their properties can be modified), then 2/ realized (properties are consumed). Some devices (objects) might depend on other devices. When creating the 'QOM composition tree', parent objects can't be 'realized' until all their children are. We might also have circular dependencies. A common circular dependency occurs with IRQs. Device (A) has an output IRQ wired to device (B), and device (B) has one to device (A). When (A) is realized and connects its IRQ to an unrealized (B), the IRQ handler on (B) is not yet created. QEMU pass IRQ between objects as pointer. When (A) poll (B)'s IRQ, it is NULL. Later (B) is realized and its IRQ pointers are populated, but (A) keeps a reference to a NULL pointer. A common pattern to bypass this circular limitation is to use 'proxy' objects. Proxy (P) is created (and realized) before (A) and (B). Then (A) and (B) can be created in different order, it doesn't matter: (P) pointers are already populated. Commit cef2e7148e ("hw/isa/i82378: Remove intermediate IRQ forwarder") neglected the QOM/QDev circular dependency issue, and removed the 'proxy' between the southbridge, its PCI functions and the interrupt controller, resulting in PCI functions wiring output IRQs to 'NULL', leading to guest failures (IRQ never delivered) [1] [2]. Since we are entering feature freeze, it is safer to revert the offending patch until we figure a way to strengthen our APIs. [1] https://lore.kernel.org/qemu-devel/928a8552-ab62-9e6c-a492-d6453e338b9d= @redhat.com/ [2] https://lore.kernel.org/qemu-devel/cover.1677628524.git.balaton@eik.bme= .hu/ This reverts commit cef2e7148e32d61338de0220619d308bf42af770. Reported-by: Thomas Huth Inspired-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/i82378.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index 233059c6dc..5432ab5065 100644 --- a/hw/isa/i82378.c +++ b/hw/isa/i82378.c @@ -47,6 +47,12 @@ static const VMStateDescription vmstate_i82378 =3D { }, }; =20 +static void i82378_request_out0_irq(void *opaque, int irq, int level) +{ + I82378State *s =3D opaque; + qemu_set_irq(s->cpu_intr, level); +} + static void i82378_request_pic_irq(void *opaque, int irq, int level) { DeviceState *dev =3D opaque; @@ -88,7 +94,9 @@ static void i82378_realize(PCIDevice *pci, Error **errp) */ =20 /* 2 82C59 (irq) */ - s->isa_irqs_in =3D i8259_init(isabus, s->cpu_intr); + s->isa_irqs_in =3D i8259_init(isabus, + qemu_allocate_irq(i82378_request_out0_irq, + s, 0)); isa_bus_register_input_irqs(isabus, s->isa_irqs_in); =20 /* 1 82C54 (pit) */ --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232943; cv=none; d=zohomail.com; s=zohoarc; b=CcxN/n6mde4z8tIDCkLJl62gzQhAnQY4xm2sewjFn2dDVecplXO0ZLReAUxFv4YQbuglS6VL9upy3rk3XP8IxZUxYY+oJz4FPVcyle11LiEUU2o8ghPpGUgjuLrN19Fr4hIV/czy+/4VxCbAW331OOTitQepcK+/DI2O+cLxDPk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232943; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DnwfOaXOxJrTPxWxlZ50jz6yqfpogkCU7arLL1adNDo=; b=EnOBpJuSa/qgqGE1HLY7vfBbnDnT7CnLfzd9d42THIMXZw3ExJtLPZfocjuBI0SpV4lAvnBpsSvEmGGndZGDc7S68D+UbbYNfKmkg/wHu9ijIKw+Xv88xp9TOUzQFBrw7wjzLplfG75VEmI+VK4tX/ZAXKmBHuqOk6CNCZUOaSg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678232943938449.01613342978294; Tue, 7 Mar 2023 15:49:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh2Z-0001tx-ER; Tue, 07 Mar 2023 18:48:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh2V-0001hE-Tr for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:15 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh2T-0002fE-LF for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:15 -0500 Received: by mail-wm1-x32f.google.com with SMTP id l7-20020a05600c1d0700b003eb5e6d906bso150203wms.5 for ; Tue, 07 Mar 2023 15:48:13 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id f7-20020a05600c44c700b003e2232d0960sm14049592wmo.23.2023.03.07.15.48.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DnwfOaXOxJrTPxWxlZ50jz6yqfpogkCU7arLL1adNDo=; b=QopmL8k4bpj8/B6JHSR3giYXTdSGPrP04oHPfRkSGoyrIaDb8ByvmPRvNSEn7AQ7CB W5SVPF4xsaqE07BreKe1XFqpkhLiqoZwucv/j8+T3ltWw/yAY+XsNt9cTGu7jIpB9ljP PEgm5k2NRzaCWOtgjI//qzImZv5vnU+docY21DH8b+4Mtgg5a3RhukDeDR2CdMbe/DkZ YXKnGV/iaGDHhHO8s2Uy6KwKRZsdjodFrJvZsmX8ScwUpr36i1DV4/yDJfZ4RHfT6jta 2N/r1/r+YzqomKBsGc2PpW7SWNOLYNb0h1F18NO8/hCJVXAPJ2OjyJxUqHcXTeeoiBNn 4vgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DnwfOaXOxJrTPxWxlZ50jz6yqfpogkCU7arLL1adNDo=; b=iohPwWWKreUVc1Ej3yiBLTdZ845buQOEN8jCXmYHYwX6+92lPd74WNTCaySU/0sJgX PyNOMWlaANVHFi5DegU3aoGaPLpgpSjdaHHocWbTkeI34smQcl53M0dewcOuf2aT3M17 83dSvoF28Z7PP6y7jwII6YzXMaH4pUw0RTZGesG9PJQMhX+0/ojsBL7Rq0DG5zFGS5k2 2ds8b6H2LPQNFitX8flGK7AINBXni1sPDGTz75nkSfhq6vm79XMMP/+fUerEVa/ngytS qdlqfJuZh59Sc2l2o+fhScTK745VdWmiCOqSM62yrxldz9h6uNHb1Z9vatYshprMOjh7 f1Tg== X-Gm-Message-State: AO0yUKX60ShSl7wkXzq6VtHTIhUcOZKfV1eoj1ylOQ/fXcXHp7C/6z8U mckrUe/iHhfZMW0OT/2M0HoDRP/N+wW0Tmv9RNM= X-Google-Smtp-Source: AK7set8w0gA44wlYaKCU3/xjf/xeUnLEinWz9Dt6WTwZoSsy7dAnixReHwZcbx9MmYXt7f9EZzr4GQ== X-Received: by 2002:a05:600c:3506:b0:3dc:405b:99bf with SMTP id h6-20020a05600c350600b003dc405b99bfmr14894698wmq.15.1678232892608; Tue, 07 Mar 2023 15:48:12 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , Rene Engel , Daniel Henrique Barboza , Bernhard Beschow , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang Subject: [PULL 10/20] Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder" Date: Wed, 8 Mar 2023 00:47:01 +0100 Message-Id: <20230307234711.55375-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232946164100003 From: BALATON Zoltan To be 'usable', QDev objects (which are QOM objects) must be 1/ initialized (at this point their properties can be modified), then 2/ realized (properties are consumed). Some devices (objects) might depend on other devices. When creating the 'QOM composition tree', parent objects can't be 'realized' until all their children are. We might also have circular dependencies. A common circular dependency occurs with IRQs. Device (A) has an output IRQ wired to device (B), and device (B) has one to device (A). When (A) is realized and connects its IRQ to an unrealized (B), the IRQ handler on (B) is not yet created. QEMU pass IRQ between objects as pointer. When (A) poll (B)'s IRQ, it is NULL. Later (B) is realized and its IRQ pointers are populated, but (A) keeps a reference to a NULL pointer. A common pattern to bypass this circular limitation is to use 'proxy' objects. Proxy (P) is created (and realized) before (A) and (B). Then (A) and (B) can be created in different order, it doesn't matter: (P) pointers are already populated. Commit bb98e0f59cde ("hw/isa/vt82c686: Remove intermediate IRQ forwarder") neglected the QOM/QDev circular dependency issue, and removed the 'proxy' between the southbridge, its PCI functions and the interrupt controller, resulting in PCI functions wiring output IRQs to 'NULL', leading to guest failures (IRQ never delivered) [1] [2]. Since we are entering feature freeze, it is safer to revert the offending patch until we figure a way to strengthen our APIs. [1] https://lore.kernel.org/qemu-devel/928a8552-ab62-9e6c-a492-d6453e338b9d= @redhat.com/ [2] https://lore.kernel.org/qemu-devel/cover.1677628524.git.balaton@eik.bme= .hu/ Signed-off-by: BALATON Zoltan Tested-by: Rene Engel Reviewed-by: Daniel Henrique Barboza Message-Id: [PMD: Reworded description] Inspired-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index f4c40965cd..01e0148967 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -598,15 +598,23 @@ void via_isa_set_irq(PCIDevice *d, int n, int level) qemu_set_irq(s->isa_irqs_in[n], level); } =20 +static void via_isa_request_i8259_irq(void *opaque, int irq, int level) +{ + ViaISAState *s =3D opaque; + qemu_set_irq(s->cpu_intr, level); +} + static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s =3D VIA_ISA(d); DeviceState *dev =3D DEVICE(d); PCIBus *pci_bus =3D pci_get_bus(d); + qemu_irq *isa_irq; ISABus *isa_bus; int i; =20 qdev_init_gpio_out(dev, &s->cpu_intr, 1); + isa_irq =3D qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); isa_bus =3D isa_bus_new(dev, pci_address_space(d), pci_address_space_i= o(d), errp); =20 @@ -614,7 +622,7 @@ static void via_isa_realize(PCIDevice *d, Error **errp) return; } =20 - s->isa_irqs_in =3D i8259_init(isa_bus, s->cpu_intr); + s->isa_irqs_in =3D i8259_init(isa_bus, *isa_irq); isa_bus_register_input_irqs(isa_bus, s->isa_irqs_in); i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232952; cv=none; d=zohomail.com; s=zohoarc; b=KtR7+nF+fkR75gFVqTY28C75jOnTri8rErhBPb66RfbKmSUF34FppMTQgEtZ0S/2GvF7x/6Mfpa425rbhYic8LHxTr50+iu5bEFV4pXx867Qz4KvAjNJNoG67RtMc7KWkb0LyNtuWSdIY58IJx+HyOuTle+RnWDtrATsHKO5iBs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232952; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Xvj99jsqKpWqw2VGx7NNL/c4aCRXSRyUMEP0I5BD120=; b=LrZhUOyb4x61bHplfOvGJJIzY2Q4es0YDxZ0X239K+EQkWTNckxH8IYujRxFnsCN3tLnol/rmyiIoXgrx6kC1ZD8XLI/8f4gH7fjp+S0prepPMeAHpI+92dR3eqzZ0Paeda6UUxr04AfnB6/wZu74hp8h00gL/x8UqPxQ0cEE/A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16782329520331023.366501946016; Tue, 7 Mar 2023 15:49:12 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh2g-0002HL-C7; Tue, 07 Mar 2023 18:48:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh2c-00025L-RM for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:23 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh2a-0002lv-HJ for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:22 -0500 Received: by mail-wr1-x42c.google.com with SMTP id h11so13782060wrm.5 for ; Tue, 07 Mar 2023 15:48:19 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id j18-20020a5d6052000000b002c53f6c7599sm13407673wrt.29.2023.03.07.15.48.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xvj99jsqKpWqw2VGx7NNL/c4aCRXSRyUMEP0I5BD120=; b=tk5tpBGXCQOJEbWnjDZLm3IYxOrBV0aglKCQriBhh19w/RZSMBaRTQA93vUB7GG4f+ YJc9OIpmhDhRO0F6Nz7BxUZ096rqgz7Y4HM9BNjy+j3TbcNetgquNoNrk8rgj6NCGffI cczyHeFQgrIKqxhRy5F3PiKgwGv5fX7yMaA9l+qIby1TozuqM/TW8fNc/JP2aUO/mxzF St4pdTKW2zCzpxnsPtc2FEEMMXoWtGViEmd/PQpZhX/9Q27A+izXmf+mBssh2ENrgmxd EHc+JO94oqxZIKHIfOPumHBbyoB+9uYWY93ZXmxdeInbdvqoLD0n1tIQViF6tUkaSrki VVFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232898; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xvj99jsqKpWqw2VGx7NNL/c4aCRXSRyUMEP0I5BD120=; b=LsHVqTVVQSgGHZCJsZfLehekUhCH9V5Q8uQ4d7z+rhEIVrCEJEiM7F0FujoTLqZfKV xRf/WdyKvCvCcczPn2W6Y0R1x6V2Q9YtfE4UaFh14eb5IQ9hOwMNMjFtDag1LRUKs/xe J1rrsdqpsKhd0nq28EYSHhsNkMDD8e7fP8UzV8tVPQPf/Jq/x43nXCTnCfI5tN8qxpbL 4dlJtS4CD2GUKFaZ4HkYPpQoknha2gv0TrQz84+gg2e8Oep0ZkUpBG2p1eHnquXWoeDF hPxwjX1LO4ncY7BUq04jWeIOyGtGkSjQcAAfwfgWmAMpMGZK3vugD+Y1Ze//KBfKDfvc FT0A== X-Gm-Message-State: AO0yUKUeDTwzFrAbkoN0YLjsBRixRb/eQl3gXWPCwk+7pxoHSph2N7II rqYPRi2E4W3GjKcKTYmPvbMVxnqkbg+sOpkHyEA= X-Google-Smtp-Source: AK7set/2rPmjEDnm1Oqiu1p5hSqKSRltc3dqeWt5fRSlveFGOsRfqP4UsntKlxkJ5t+yX+GVB38Ibw== X-Received: by 2002:adf:ea47:0:b0:2cb:4df5:932d with SMTP id j7-20020adfea47000000b002cb4df5932dmr9905820wrn.22.1678232898702; Tue, 07 Mar 2023 15:48:18 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , Rene Engel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 11/20] hw/display/sm501: Add debug property to control pixman usage Date: Wed, 8 Mar 2023 00:47:02 +0100 Message-Id: <20230307234711.55375-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232954044100007 From: BALATON Zoltan Add a property to allow disabling pixman and always use the fallbacks for different operations which is useful for testing different drawing methods or debugging pixman related issues. Signed-off-by: BALATON Zoltan Tested-by: Rene Engel Message-Id: <61768ffaefa71b65a657d1365823bd43c7ee9354.1678188711.git.balato= n@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/display/sm501.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 17835159fc..dbabbc4339 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -465,6 +465,7 @@ typedef struct SM501State { uint32_t last_width; uint32_t last_height; bool do_full_update; /* perform a full update next time */ + uint8_t use_pixman; I2CBus *i2c_bus; =20 /* mmio registers */ @@ -827,7 +828,7 @@ static void sm501_2d_operation(SM501State *s) de =3D db + (width + (height - 1) * dst_pitch) * bypp; overlap =3D (db < se && sb < de); } - if (overlap) { + if (overlap && (s->use_pixman & BIT(2))) { /* pixman can't do reverse blit: copy via temporary */ int tmp_stride =3D DIV_ROUND_UP(width * bypp, sizeof(uint3= 2_t)); uint32_t *tmp =3D tmp_buf; @@ -852,13 +853,15 @@ static void sm501_2d_operation(SM501State *s) if (tmp !=3D tmp_buf) { g_free(tmp); } - } else { + } else if (!overlap && (s->use_pixman & BIT(1))) { fallback =3D !pixman_blt((uint32_t *)&s->local_mem[src_bas= e], (uint32_t *)&s->local_mem[dst_base], src_pitch * bypp / sizeof(uint32_t), dst_pitch * bypp / sizeof(uint32_t), 8 * bypp, 8 * bypp, src_x, src_y, dst_x, dst_y, width, height); + } else { + fallback =3D true; } if (fallback) { uint8_t *sp =3D s->local_mem + src_base; @@ -891,7 +894,7 @@ static void sm501_2d_operation(SM501State *s) color =3D cpu_to_le16(color); } =20 - if ((width =3D=3D 1 && height =3D=3D 1) || + if (!(s->use_pixman & BIT(0)) || (width =3D=3D 1 && height =3D=3D = 1) || !pixman_fill((uint32_t *)&s->local_mem[dst_base], dst_pitch * bypp / sizeof(uint32_t), 8 * bypp, dst_x, dst_y, width, height, color)) { @@ -2035,6 +2038,7 @@ static void sm501_realize_sysbus(DeviceState *dev, Er= ror **errp) =20 static Property sm501_sysbus_properties[] =3D { DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), + DEFINE_PROP_UINT8("x-pixman", SM501SysBusState, state.use_pixman, 7), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2122,6 +2126,7 @@ static void sm501_realize_pci(PCIDevice *dev, Error *= *errp) =20 static Property sm501_pci_properties[] =3D { DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), + DEFINE_PROP_UINT8("x-pixman", SM501PCIState, state.use_pixman, 7), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -2162,11 +2167,18 @@ static void sm501_pci_class_init(ObjectClass *klass= , void *data) dc->vmsd =3D &vmstate_sm501_pci; } =20 +static void sm501_pci_init(Object *o) +{ + object_property_set_description(o, "x-pixman", "Use pixman for: " + "1: fill, 2: blit, 4: overlap blit"); +} + static const TypeInfo sm501_pci_info =3D { .name =3D TYPE_PCI_SM501, .parent =3D TYPE_PCI_DEVICE, .instance_size =3D sizeof(SM501PCIState), .class_init =3D sm501_pci_class_init, + .instance_init =3D sm501_pci_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Paolo Bonzini Subject: [PULL 12/20] hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select Date: Wed, 8 Mar 2023 00:47:03 +0100 Message-Id: <20230307234711.55375-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232923940100001 From: David Woodhouse Back in the mists of time, before EISA came along and required per-pin level control in the ELCR register, the i8259 had a single chip-wide level-mode control in bit 3 of ICW1. Even in the PIIX3 datasheet from 1996 this is documented as 'This bit is disabled', but apparently MorphOS is using it in the version of the i8259 which is in the Pegasos2 board as part of the VT8231 chipset. It's easy enough to implement, and I think it's harmless enough to do so unconditionally. Signed-off-by: David Woodhouse [balaton: updated commit message as asked by author] Tested-by: BALATON Zoltan Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Message-Id: <3f09b2dd109d19851d786047ad5c2ff459c90cd7.1678188711.git.balato= n@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/i8259.c | 10 ++++------ hw/intc/i8259_common.c | 24 +++++++++++++++++++++++- include/hw/isa/i8259_internal.h | 1 + 3 files changed, 28 insertions(+), 7 deletions(-) diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 17910f3bcb..bbae2d87f4 100644 --- a/hw/intc/i8259.c +++ b/hw/intc/i8259.c @@ -133,7 +133,7 @@ static void pic_set_irq(void *opaque, int irq, int leve= l) } #endif =20 - if (s->elcr & mask) { + if (s->ltim || (s->elcr & mask)) { /* level triggered */ if (level) { s->irr |=3D mask; @@ -167,7 +167,7 @@ static void pic_intack(PICCommonState *s, int irq) s->isr |=3D (1 << irq); } /* We don't clear a level sensitive interrupt here */ - if (!(s->elcr & (1 << irq))) { + if (!s->ltim && !(s->elcr & (1 << irq))) { s->irr &=3D ~(1 << irq); } pic_update_irq(s); @@ -224,6 +224,7 @@ static void pic_reset(DeviceState *dev) PICCommonState *s =3D PIC_COMMON(dev); =20 s->elcr =3D 0; + s->ltim =3D 0; pic_init_reset(s); } =20 @@ -243,10 +244,7 @@ static void pic_ioport_write(void *opaque, hwaddr addr= 64, s->init_state =3D 1; s->init4 =3D val & 1; s->single_mode =3D val & 2; - if (val & 0x08) { - qemu_log_mask(LOG_UNIMP, - "i8259: level sensitive irq not supported\n"= ); - } + s->ltim =3D val & 8; } else if (val & 0x08) { if (val & 0x04) { s->poll =3D 1; diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index af2e4a2241..c931dc2d07 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -51,7 +51,7 @@ void pic_reset_common(PICCommonState *s) s->special_fully_nested_mode =3D 0; s->init4 =3D 0; s->single_mode =3D 0; - /* Note: ELCR is not reset */ + /* Note: ELCR and LTIM are not reset */ } =20 static int pic_dispatch_pre_save(void *opaque) @@ -144,6 +144,24 @@ static void pic_print_info(InterruptStatsProvider *obj= , Monitor *mon) s->special_fully_nested_mode); } =20 +static bool ltim_state_needed(void *opaque) +{ + PICCommonState *s =3D PIC_COMMON(opaque); + + return !!s->ltim; +} + +static const VMStateDescription vmstate_pic_ltim =3D { + .name =3D "i8259/ltim", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D ltim_state_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8(ltim, PICCommonState), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_pic_common =3D { .name =3D "i8259", .version_id =3D 1, @@ -168,6 +186,10 @@ static const VMStateDescription vmstate_pic_common =3D= { VMSTATE_UINT8(single_mode, PICCommonState), VMSTATE_UINT8(elcr, PICCommonState), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription*[]) { + &vmstate_pic_ltim, + NULL } }; =20 diff --git a/include/hw/isa/i8259_internal.h b/include/hw/isa/i8259_interna= l.h index 155b098452..f9dcc4163e 100644 --- a/include/hw/isa/i8259_internal.h +++ b/include/hw/isa/i8259_internal.h @@ -61,6 +61,7 @@ struct PICCommonState { uint8_t single_mode; /* true if slave pic is not initialized */ uint8_t elcr; /* PIIX edge/trigger selection*/ uint8_t elcr_mask; + uint8_t ltim; /* Edge/Level Bank Select (pre-PIIX, chip-wide) */ qemu_irq int_out[1]; uint32_t master; /* reflects /SP input pin */ uint32_t iobase; --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678233005; cv=none; d=zohomail.com; s=zohoarc; b=LHRFIxPNxBIf1RpcYnafgDd26Wai06Y2IvURrYz9gx/m0kJM5Q4vJJmNmc9rfplpCtgyuiquD2I0tFDdcpC/0iRAAaF+WDP7DSCgy/PP7Wf17klWSWJt75FUq1sf+F7TBvcbQ3kuV9B8lvPXej2liIJBTZykAZa0ZkskqWQYPrk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678233005; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id o13-20020a5d670d000000b002c8476dde7asm13706104wru.114.2023.03.07.15.48.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9irWQw02oFu2/D4ty32J7zQYkGSYrUOUK9Or1m5BKRM=; b=gwSjzS98wh68Fu2g62z1JKcKVOswblHKob2VT9JjOtYDq22LbtmKNaDA1fJtv2W1AT EV4PEnfHsvXV9fkZFHjfFey4bEm7elIRc/4o+ejCRKE9e7IICyYX2gxAIqVWa3nsR/6t jceI8fB1gGrP9Fot83WgeMN7M/DOrivjLLFqZ+87zq6cwjwgNW3E/X2hgLDIA3fluhRL 7rnXMz4v8wm1FMnhnQV2aMwxGVEcglLmU8y+nw1+eDeflXOJqADkJJV3KA1On/JMN0M/ vE9v2XBsHflvT4892HG+KM8JRDa5iTt/w1i7yYIAtrm5djlTqFbe2aCgvLVt6L2qDtJP 3HXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9irWQw02oFu2/D4ty32J7zQYkGSYrUOUK9Or1m5BKRM=; b=hn8AT+FRxbWjSXLQVW+ZZcpens+KvnOPo8QYWWdDDb4ZNrYUlHyDT2MyGDYoE74eU/ yAFNLX+80iDFjA2YAYbn5FItuEH0siMXetKfobDA7AgVJwofAKD98K+wDrDo2xnb/+7p LiZWuwqSeHBvvzRsvxtbTrdjb3XLxzvAqJU+7OYQiNgzvOG00DwhbvN4YQTKAK+FhDh+ cP/0iJF9MnsH4bVvPvp2MP8Ceb5jCzUUgpskMYjKOlCfP+vv5WuNVMs6wMYaup/bfjMx uv/mpXm/jtS4H+Ky7kyydPRrX/LUSlmmtGEjfVZwyx2KafnvY48IlvKNA5xy1ZNcQiaQ bW1w== X-Gm-Message-State: AO0yUKVWREodBLC/duBYcNN6RExy80hVz5RV4OZ++twrqJivuKCGWo5p cdLb+7v27Eid2lLubrJAF0VwXYShqGV8ANmhEPw= X-Google-Smtp-Source: AK7set9bUKjH516OYKwJDpYTcQvI7vZMOtaGlCpgvrDtdOORegST9Wycc1+PP+mlKDEPdmeA4OKwoA== X-Received: by 2002:a05:6000:1041:b0:2c6:e91d:1359 with SMTP id c1-20020a056000104100b002c6e91d1359mr9832855wrx.61.1678232910583; Tue, 07 Mar 2023 15:48:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , Bernhard Beschow , Rene Engel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang Subject: [PULL 13/20] hw/isa/vt82c686: Implement PCI IRQ routing Date: Wed, 8 Mar 2023 00:47:04 +0100 Message-Id: <20230307234711.55375-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678233006336100005 From: BALATON Zoltan The real VIA south bridges implement a PCI IRQ router which is configured by the BIOS or the OS. In order to respect these configurations, QEMU needs to implement it as well. The real chip may allow routing IRQs from internal functions independently of PCI interrupts but since guests usually configute it to a single shared interrupt we don't model that here for simplicity. Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4. Suggested-by: Bernhard Beschow Signed-off-by: BALATON Zoltan Reviewed-by: Bernhard Beschow Tested-by: Rene Engel Message-Id: Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 01e0148967..71da316052 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -604,6 +604,46 @@ static void via_isa_request_i8259_irq(void *opaque, in= t irq, int level) qemu_set_irq(s->cpu_intr, level); } =20 +static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) +{ + switch (irq_num) { + case 0: + return s->dev.config[0x55] >> 4; + case 1: + return s->dev.config[0x56] & 0xf; + case 2: + return s->dev.config[0x56] >> 4; + case 3: + return s->dev.config[0x57] >> 4; + } + return 0; +} + +static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) +{ + ViaISAState *s =3D opaque; + PCIBus *bus =3D pci_get_bus(&s->dev); + int i, pic_level, pic_irq =3D via_isa_get_pci_irq(s, irq_num); + + /* IRQ 0: disabled, IRQ 2,8,13: reserved */ + if (!pic_irq) { + return; + } + if (unlikely(pic_irq =3D=3D 2 || pic_irq =3D=3D 8 || pic_irq =3D=3D 13= )) { + qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing"); + } + + /* The pic level is the logical OR of all the PCI irqs mapped to it. */ + pic_level =3D 0; + for (i =3D 0; i < PCI_NUM_PINS; i++) { + if (pic_irq =3D=3D via_isa_get_pci_irq(s, i)) { + pic_level |=3D pci_bus_get_irq_level(bus, i); + } + } + /* Now we change the pic irq level according to the via irq mappings. = */ + qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level); +} + static void via_isa_realize(PCIDevice *d, Error **errp) { ViaISAState *s =3D VIA_ISA(d); @@ -627,6 +667,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp) i8254_pit_init(isa_bus, 0x40, 0, NULL); i8257_dma_init(isa_bus, 0); =20 + qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PINS= ); + /* RTC */ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000); if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) { --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232935; cv=none; d=zohomail.com; s=zohoarc; b=ILgXlrfFvizJglu88g4VBAH9L5EdkfV7XoF3UJQ04pJTb0Ga8ThTaVq30Ci+gD+R8K+ujjUUTeLujhg7rzYvoEdQMV6X3PxH+0HvJBDZLY3XLIps2bzoGUZzVVq2rs+txVa9sCvf1WPZ4nt9VgdJ7PbLRWwm+6JgWVjQ8d3L4+4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232935; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gpJPCmXwquoCWBgXDDE3NqTOd956WcpGbyNKVzShIlk=; b=Hdc/JD2gncu1qXTBzOOrg9a7UK/AGQBs0TX4F0C1MkKj40IoYI0nmogDUlSyt3okvNx/E1JlAksFYyq3SvJYjiG2v+mdlF2BW/ZXXF+hf07LGnZjfd5BinEEUjlugFwEqW+8HivI7vexRRAaCyrAngOYdxRqzCDkHSZMxAvnW4g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678232935849718.4321786614294; Tue, 7 Mar 2023 15:48:55 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh2v-0004CC-L2; Tue, 07 Mar 2023 18:48:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh2u-000466-B7 for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:40 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh2s-0002tK-8s for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:40 -0500 Received: by mail-wm1-x32d.google.com with SMTP id j19-20020a05600c191300b003eb3e1eb0caso179195wmq.1 for ; Tue, 07 Mar 2023 15:48:37 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id v12-20020a05600c12cc00b003de2fc8214esm13810478wmd.20.2023.03.07.15.48.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gpJPCmXwquoCWBgXDDE3NqTOd956WcpGbyNKVzShIlk=; b=IEw6CyOer/a0+9gM4WU+FY3dy/0K8DLtHAQHaqrrD4lTo/aNpwCYPfFo9OBZgkU6Zy n2u9DENkELJhO2khxWMUpUb/nn427floF08/vaDEDSwtLHwTMJ06/ysWYPIJbvMSlool T0hBZU3yZV9qbYj2FwcvWnVWJrqVVX/qtibau3tdIy3RyKmkwwANTbTQ/7rDJyq8xqaP i98CtuFcXo4LkwpGP4VsU+czxoLCiibUtYN7VPEtqqA6aGrkvh0uOXunZz8Tdhk95Ytt FMDKsvXoI5qOdNXAsa2u9SF8bSfLDbAh98X+GNSCaLcploNG4BvYp5dhZWfAbPRV7AuW HeuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232916; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gpJPCmXwquoCWBgXDDE3NqTOd956WcpGbyNKVzShIlk=; b=4hEpudjEX0VK/hvRC96mqImHKyBXJmmG4gkaoyZb3xNNZ82D2/tmH9FDiWSj6ElPDP IK53taUTb/3pu3OdNN9RSdXP70pJZsp12XmOSOZ0G8pOCsYGIXN9latgLR28lGGbIYVf 3MUHEzj5bkLpwU+ZNbL2gjQuAyVJRErYiDbH+e6GwUXnwHSFwZR3chKvd1RBNfVJ0Nk7 cE5TplgDXzJ+sImoojRv8p7lFczWiduvMzlqXto+FLsa2MJlfxiAU4Anssq4RBCXUe3l 68dvNxcOpzgFb9NYxXnFNKwhLC14M8RTdzP6SiVVIZ2pdqd4rG0bBsqeHAxPg3NKGAIM jymw== X-Gm-Message-State: AO0yUKXm479V+ZvYpWh327dY8gzLWX8Dfh9tD6sEX1voWJD1TjKRlZtu 58ElCuHho3hcPNeokE5K37xCXi/zroNuN1oxUrE= X-Google-Smtp-Source: AK7set8LM5/qxpwQjBUUR+G6Miz25iRI9cqbKg1MX3T+c0nHug202Qbl3P3/5yX1ar09h6sC4dc4zQ== X-Received: by 2002:a05:600c:5127:b0:3ea:dbdd:66df with SMTP id o39-20020a05600c512700b003eadbdd66dfmr13985794wms.2.1678232916367; Tue, 07 Mar 2023 15:48:36 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , Daniel Henrique Barboza , Rene Engel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 14/20] hw/ppc/pegasos2: Fix PCI interrupt routing Date: Wed, 8 Mar 2023 00:47:05 +0100 Message-Id: <20230307234711.55375-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232938177100003 From: BALATON Zoltan According to the PegasosII schematics the PCI interrupt lines are connected to both the gpp pins of the Mv64361 north bridge and the PINT pins of the VT8231 south bridge so guests can get interrupts from either of these. So far we only had the MV64361 connections which worked for on board devices but for additional PCI devices (such as network or sound card added with -device) guest OSes expect interrupt from the ISA IRQ 9 where the firmware routes these PCI interrupts in VT8231 ISA bridge. After the previous patches we can now model this and also remove the board specific connection from mv64361. Also configure routing of these lines when using Virtual Open Firmware to match board firmware for guests that expect this. This fixes PCI interrupts on pegasos2 under Linux, MorphOS and AmigaOS. Signed-off-by: BALATON Zoltan Reviewed-by: Daniel Henrique Barboza Tested-by: Rene Engel Message-Id: <520ff9e6eeef600ee14a4116c0c7b11940cc499c.1678188711.git.balato= n@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/pci-host/mv64361.c | 4 ---- hw/ppc/pegasos2.c | 26 +++++++++++++++++++++++++- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c index 298564f1f5..19e8031a3f 100644 --- a/hw/pci-host/mv64361.c +++ b/hw/pci-host/mv64361.c @@ -873,10 +873,6 @@ static void mv64361_realize(DeviceState *dev, Error **= errp) } sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cpu_irq); qdev_init_gpio_in_named(dev, mv64361_gpp_irq, "gpp", 32); - /* FIXME: PCI IRQ connections may be board specific */ - for (i =3D 0; i < PCI_NUM_PINS; i++) { - s->pci[1].irq[i] =3D qdev_get_gpio_in_named(dev, "gpp", 12 + i); - } } =20 static void mv64361_reset(DeviceState *dev) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 7cc375df05..f1650be5ee 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -73,6 +73,8 @@ struct Pegasos2MachineState { MachineState parent_obj; PowerPCCPU *cpu; DeviceState *mv; + qemu_irq mv_pirq[PCI_NUM_PINS]; + qemu_irq via_pirq[PCI_NUM_PINS]; Vof *vof; void *fdt_blob; uint64_t kernel_addr; @@ -95,6 +97,15 @@ static void pegasos2_cpu_reset(void *opaque) } } =20 +static void pegasos2_pci_irq(void *opaque, int n, int level) +{ + Pegasos2MachineState *pm =3D opaque; + + /* PCI interrupt lines are connected to both MV64361 and VT8231 */ + qemu_set_irq(pm->mv_pirq[n], level); + qemu_set_irq(pm->via_pirq[n], level); +} + static void pegasos2_init(MachineState *machine) { Pegasos2MachineState *pm =3D PEGASOS2_MACHINE(machine); @@ -106,7 +117,7 @@ static void pegasos2_init(MachineState *machine) I2CBus *i2c_bus; const char *fwname =3D machine->firmware ?: PROM_FILENAME; char *filename; - int sz; + int i, sz; uint8_t *spd_data; =20 /* init CPU */ @@ -156,11 +167,18 @@ static void pegasos2_init(MachineState *machine) /* Marvell Discovery II system controller */ pm->mv =3D DEVICE(sysbus_create_simple(TYPE_MV64361, -1, qdev_get_gpio_in(DEVICE(pm->cpu), PPC6xx_INPUT_I= NT))); + for (i =3D 0; i < PCI_NUM_PINS; i++) { + pm->mv_pirq[i] =3D qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i); + } pci_bus =3D mv64361_get_pci_bus(pm->mv, 1); + pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS); =20 /* VIA VT8231 South Bridge (multifunction PCI device) */ via =3D OBJECT(pci_create_simple_multifunction(pci_bus, PCI_DEVFN(12, = 0), true, TYPE_VT8231_ISA)); + for (i =3D 0; i < PCI_NUM_PINS; i++) { + pm->via_pirq[i] =3D qdev_get_gpio_in_named(DEVICE(via), "pirq", i); + } object_property_add_alias(OBJECT(machine), "rtc-time", object_resolve_path_component(via, "rtc"), "date"); @@ -267,6 +285,12 @@ static void pegasos2_machine_reset(MachineState *machi= ne, ShutdownCause reason) PCI_INTERRUPT_LINE, 2, 0x9); pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | 0x50, 1, 0x2); + pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | + 0x55, 1, 0x90); + pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | + 0x56, 1, 0x99); + pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) | + 0x57, 1, 0x90); =20 pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 1) << 8) | PCI_INTERRUPT_LINE, 2, 0x109); --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678232951; cv=none; d=zohomail.com; s=zohoarc; b=Lxroy0cmFpoFVNjesJ7BWC27nHiHnlmc3lKm/jag0ebhRqh5RKyD/OkqYXH9UXJblPrmsh9R7iG1nU1/xCy/qk2Ylnakm8/R8ex6hdKOX2l9pXA44rMKx26c+qu1UuJPNS5ICkv2xQubixwWiQcSccOflqD5UNbNB8R52SJoOn8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678232951; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kvZA9kHv9vC3q4gyCksHVwK7luWn5sDCN4JTXjtF+kU=; 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id q30-20020a05600c331e00b003dc5b59ed7asm13912209wmp.11.2023.03.07.15.48.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kvZA9kHv9vC3q4gyCksHVwK7luWn5sDCN4JTXjtF+kU=; b=A5kVc/GeqbJTFVVopw3C2R0ZYUj3G633doRkKCInHYAkoIADBunNYWarVQqnxWFzwW XMy4OZfHn+3sBcSRksMrREdEDbFwknEH5rZc9HpznNbqNSRMtkt+xPGkMgKBMVCHPvmB aVIyzpUF/XBdVJbvxQAUYgXS8ZEjGh1xd8vy9ECVUjBGITZF4V9q9EAur0BMQrd69WqE GCoCao50MbfeMDOBU0L3OFbCNla+TSsFQo5Yxgz2yk7oy8eVHpAn92zlMbvluBOsiCHw /Kn5Bk6dzU4UH8gnXrwP1yGTujNqjszfD39xb/KnwATOyVetyQIaA3p/Wr8wTSVt0azo kHtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232922; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kvZA9kHv9vC3q4gyCksHVwK7luWn5sDCN4JTXjtF+kU=; b=VlkhfZ8EOG+RaCPoYg30uGSptDf+PV1SASvFyCk2wwrwVH2969TkItTui9zbd4zkmT LP1lw6POhG/7/OCW/HwsvkvcCJeJj6UQfasZPulKfZ+G8hBiLceQd+umuRIB2YghFCw2 rXL7zhf7ymhl+CESOMbFBfnhYRFdT4IPuJv4BwwJ8LnxbcWmL+tVX15H9vh+jc1dIP6b GpLNHZlRsnawQhl3knAwRJyfIXuGLxCOAREx5tlM1TKTTm12qYc+yZZjFbmlktUWRipy 3EMN5sEjJ/PQ0u+9mcpfe0IXau5J/cRZmJCaJPQqbQwQgZsuJJcruBWfdid2zwm20kEN TfCw== X-Gm-Message-State: AO0yUKX7GlkkHT5+4aT+nN8p0zinn+G7bNlPQf67cMQRu7MoE/ezUCQO JGNpAiGUEPBRQWotp3IxkuwhqJBr4nHIlPVNem0= X-Google-Smtp-Source: AK7set9m3apu0wbnTk+EhTO+Tqmj6YIBHEmTYwtqiU8Ualh2Ek6949PeycYq6kq4AApu4kOxvub8Mw== X-Received: by 2002:a05:600c:450b:b0:3ea:ea8a:a94a with SMTP id t11-20020a05600c450b00b003eaea8aa94amr14921165wmo.27.1678232922525; Tue, 07 Mar 2023 15:48:42 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Bernhard Beschow , Mark Cave-Ayland , Rene Engel , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Jiaxun Yang , Gerd Hoffmann Subject: [PULL 15/20] hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing Date: Wed, 8 Mar 2023 00:47:06 +0100 Message-Id: <20230307234711.55375-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678232952048100001 From: Bernhard Beschow According to the PCI specification, PCI_INTERRUPT_LINE shall have no effect on hardware operations. Now that the VIA south bridges implement the internal PCI interrupt router let's be more conformant to the PCI specification. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland Tested-by: Rene Engel Signed-off-by: BALATON Zoltan Message-Id: <9fb86a74d16db65e3aafbb154238d55e123053eb.1678188711.git.balato= n@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/vt82c686-uhci-pci.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/hw/usb/vt82c686-uhci-pci.c b/hw/usb/vt82c686-uhci-pci.c index 46a901f56f..b4884c9011 100644 --- a/hw/usb/vt82c686-uhci-pci.c +++ b/hw/usb/vt82c686-uhci-pci.c @@ -1,17 +1,7 @@ #include "qemu/osdep.h" -#include "hw/irq.h" #include "hw/isa/vt82c686.h" #include "hcd-uhci.h" =20 -static void uhci_isa_set_irq(void *opaque, int irq_num, int level) -{ - UHCIState *s =3D opaque; - uint8_t irq =3D pci_get_byte(s->dev.config + PCI_INTERRUPT_LINE); - if (irq > 0 && irq < 15) { - via_isa_set_irq(pci_get_function_0(&s->dev), irq, level); - } -} - static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Error **errp) { UHCIState *s =3D UHCI(dev); @@ -25,8 +15,6 @@ static void usb_uhci_vt82c686b_realize(PCIDevice *dev, Er= ror **errp) pci_set_long(pci_conf + 0xc0, 0x00002000); =20 usb_uhci_common_realize(dev, errp); - object_unref(s->irq); - s->irq =3D qemu_allocate_irq(uhci_isa_set_irq, s, 0); } =20 static UHCIInfo uhci_info[] =3D { --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678233003; cv=none; d=zohomail.com; s=zohoarc; b=j49i9X+vY9rQZ3CU4YVRXbBgJEjy1zb5PHxaT/l32D0Nt5RL3cpUisb7sK4r+Q2z0zfImKizS3JCwmDKeh2X5PoE/B5SCPvoZWk5+TDb7YSXwf0OX0AndzCQ+bUOr4qd/NFymHhkYBHc+KCLgHdAWjo42QELRyNhB4UeiMAI6mw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678233003; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=On55k3PnTVKUXNRwlYNTFY0ojQbTf7BC/rL43z5BXv4=; b=UUZuzDnCGbs2dU45xrJS9LQoQA+qcdi4MY6FL5epoT/7QVPKYyXC4FGopkO5s10pNZdfrWD0+1EIV4QR1c1uF0c8mfvWVnbttmvRJ35p6YEJPYvptx8x0zRSZhJP02qlXu/He20mMWftocWxLY/sgm9D8zXqk4F5f9jS+Q/wvZQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678233003928409.69546467984026; Tue, 7 Mar 2023 15:50:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh3Q-0005NI-C1; Tue, 07 Mar 2023 18:49:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh37-000566-5d for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:54 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh34-0002ml-E0 for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:48:52 -0500 Received: by mail-wr1-x432.google.com with SMTP id l1so13739373wry.12 for ; Tue, 07 Mar 2023 15:48:49 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id x8-20020adff648000000b002c3dc4131f5sm13805670wrp.18.2023.03.07.15.48.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=On55k3PnTVKUXNRwlYNTFY0ojQbTf7BC/rL43z5BXv4=; b=eBOrcOUQEAxOdrxfGeKa8VvJOk65Vv+wM57LxI0QdaQNvc6g3xCyE5vvdfiQlDmQWb eAj4DpUbhroi1LnRoKapVXA3UBLN1ajPhd3I3/bNnszAiuVsAlFAiH+W+3dQkSsY14i8 vbUXP/7znwU5RG/oJX6dOudZFw7E+kHmWqYD4Tb2aII6OV4geSsVrpvJgnwF+DLR0wey yVtqTVWtiOYa77/vDtI8IPsOKeI8CPOg9mLQu3SDkyApShaLDDoTOTyJ3/lJ8fu9bbgS 5BjbjXmtPt8MPvUF8xOe/jqdu27bR3zbn7YUaHIR8FVAbdG2NWECbysy4hivhn4HS3YZ QpfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232929; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=On55k3PnTVKUXNRwlYNTFY0ojQbTf7BC/rL43z5BXv4=; b=Lzcu0hP1/eCiYU1PsoS5NDPPQIhmK6sCu3fuiUvOO/ETu18JftnUBva8iH14ZXmkJA n9F80c/jTzK6YJOc6g4tdOezjYoJhbG2V4UOo9omwqt5azm0eC1DW9yCNyN1+CfZV5cD FyTR6A8TiM1V/pLBxW5HdmP0Ybsi3XtUvvWjEGTgbXkt3owPQr1sHVPLDZilyVgobbPQ c2jZftolVGgcsDFh0LPzMeX3T/m9RHFcyXqJS7nSyNcE27XZBzmcPXNz/jWWphztDlcp HzQFuMBdA4KhIAAliTQKAFBeLLZFIUgrVmjK6YzlNex89B1MDbIqJWXNTKgWFq58Ozd+ 6TxQ== X-Gm-Message-State: AO0yUKVLwf7jiUF93i/idsQ0zAINj6dXXmzxw3E/Z7GG5SbWqXP14SwP Vr3NLL0D5lRyu/yZz8dTodJB7SzA+xknxGYPpkY= X-Google-Smtp-Source: AK7set/ntTVXLO63U1j1t7QtdQfOjC80WiKPCM6SmgS+SPiLAraGAHi2evYFhLQSjmfQWLgcV/tmKA== X-Received: by 2002:adf:ec09:0:b0:2c3:e5e6:f0d8 with SMTP id x9-20020adfec09000000b002c3e5e6f0d8mr10706750wrn.11.1678232929096; Tue, 07 Mar 2023 15:48:49 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , =?UTF-8?q?Volker=20R=C3=BCmelin?= , Rene Engel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Gerd Hoffmann , Huacai Chen , Jiaxun Yang Subject: [PULL 16/20] hw/audio/via-ac97: Basic implementation of audio playback Date: Wed, 8 Mar 2023 00:47:07 +0100 Message-Id: <20230307234711.55375-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678233004454100001 From: BALATON Zoltan Add basic implementation of the AC'97 sound part used in VIA south bridge chips. Not all features of the device is emulated, only one playback channel is supported for now but this is enough to get sound output from some guests using this device on pegasos2. Signed-off-by: BALATON Zoltan Reviewed-by: Volker R=C3=BCmelin Tested-by: Rene Engel Message-Id: <63b99410895312f40e7be479f581da0805e605a1.1678188711.git.balato= n@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/audio/trace-events | 6 + hw/audio/via-ac97.c | 455 +++++++++++++++++++++++++++++++++++++- hw/isa/trace-events | 1 + hw/isa/vt82c686.c | 2 +- include/hw/isa/vt82c686.h | 25 +++ 5 files changed, 482 insertions(+), 7 deletions(-) diff --git a/hw/audio/trace-events b/hw/audio/trace-events index e0e71cd9b1..4dec48a4fd 100644 --- a/hw/audio/trace-events +++ b/hw/audio/trace-events @@ -11,3 +11,9 @@ hda_audio_running(const char *stream, int nr, bool runnin= g) "st %s, nr %d, run % hda_audio_format(const char *stream, int chan, const char *fmt, int freq) = "st %s, %d x %s @ %d Hz" hda_audio_adjust(const char *stream, int pos) "st %s, pos %d" hda_audio_overrun(const char *stream) "st %s" + +#via-ac97.c +via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x" +via_ac97_sgd_fetch(uint32_t curr, uint32_t addr, char stop, char eol, char= flag, uint32_t len) "curr=3D0x%x addr=3D0x%x %c%c%c len=3D%d" +via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64"= %d -> 0x%"PRIx64 +via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64= " %d <- 0x%"PRIx64 diff --git a/hw/audio/via-ac97.c b/hw/audio/via-ac97.c index d1a856f63d..676254b7a4 100644 --- a/hw/audio/via-ac97.c +++ b/hw/audio/via-ac97.c @@ -1,39 +1,482 @@ /* * VIA south bridges sound support * + * Copyright (c) 2022-2023 BALATON Zoltan + * * This work is licensed under the GNU GPL license version 2 or later. */ =20 /* - * TODO: This is entirely boiler plate just registering empty PCI devices - * with the right ID guests expect, functionality should be added here. + * TODO: This is only a basic implementation of one audio playback channel + * more functionality should be added here. */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "hw/isa/vt82c686.h" -#include "hw/pci/pci_device.h" +#include "ac97.h" +#include "trace.h" + +#define CLEN_IS_EOL(x) ((x)->clen & BIT(31)) +#define CLEN_IS_FLAG(x) ((x)->clen & BIT(30)) +#define CLEN_IS_STOP(x) ((x)->clen & BIT(29)) +#define CLEN_LEN(x) ((x)->clen & 0xffffff) + +#define STAT_ACTIVE BIT(7) +#define STAT_PAUSED BIT(6) +#define STAT_TRIG BIT(3) +#define STAT_STOP BIT(2) +#define STAT_EOL BIT(1) +#define STAT_FLAG BIT(0) + +#define CNTL_START BIT(7) +#define CNTL_TERM BIT(6) +#define CNTL_PAUSE BIT(3) + +static void open_voice_out(ViaAC97State *s); + +static uint16_t codec_rates[] =3D { 8000, 11025, 16000, 22050, 32000, 4410= 0, + 48000 }; + +#define CODEC_REG(s, o) ((s)->codec_regs[(o) / 2]) +#define CODEC_VOL(vol, mask) ((255 * ((vol) & mask)) / mask) + +static void codec_volume_set_out(ViaAC97State *s) +{ + int lvol, rvol, mute; + + lvol =3D 255 - CODEC_VOL(CODEC_REG(s, AC97_Master_Volume_Mute) >> 8, 0= x1f); + lvol *=3D 255 - CODEC_VOL(CODEC_REG(s, AC97_PCM_Out_Volume_Mute) >> 8,= 0x1f); + lvol /=3D 255; + rvol =3D 255 - CODEC_VOL(CODEC_REG(s, AC97_Master_Volume_Mute), 0x1f); + rvol *=3D 255 - CODEC_VOL(CODEC_REG(s, AC97_PCM_Out_Volume_Mute), 0x1f= ); + rvol /=3D 255; + mute =3D CODEC_REG(s, AC97_Master_Volume_Mute) >> MUTE_SHIFT; + mute |=3D CODEC_REG(s, AC97_PCM_Out_Volume_Mute) >> MUTE_SHIFT; + AUD_set_volume_out(s->vo, mute, lvol, rvol); +} + +static void codec_reset(ViaAC97State *s) +{ + memset(s->codec_regs, 0, sizeof(s->codec_regs)); + CODEC_REG(s, AC97_Reset) =3D 0x6a90; + CODEC_REG(s, AC97_Master_Volume_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Headphone_Volume_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Master_Volume_Mono_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Phone_Volume_Mute) =3D 0x8008; + CODEC_REG(s, AC97_Mic_Volume_Mute) =3D 0x8008; + CODEC_REG(s, AC97_Line_In_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_CD_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_Video_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_Aux_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_PCM_Out_Volume_Mute) =3D 0x8808; + CODEC_REG(s, AC97_Record_Gain_Mute) =3D 0x8000; + CODEC_REG(s, AC97_Powerdown_Ctrl_Stat) =3D 0x000f; + CODEC_REG(s, AC97_Extended_Audio_ID) =3D 0x0a05; + CODEC_REG(s, AC97_Extended_Audio_Ctrl_Stat) =3D 0x0400; + CODEC_REG(s, AC97_PCM_Front_DAC_Rate) =3D 48000; + CODEC_REG(s, AC97_PCM_LR_ADC_Rate) =3D 48000; + /* Sigmatel 9766 (STAC9766) */ + CODEC_REG(s, AC97_Vendor_ID1) =3D 0x8384; + CODEC_REG(s, AC97_Vendor_ID2) =3D 0x7666; +} + +static uint16_t codec_read(ViaAC97State *s, uint8_t addr) +{ + return CODEC_REG(s, addr); +} + +static void codec_write(ViaAC97State *s, uint8_t addr, uint16_t val) +{ + trace_via_ac97_codec_write(addr, val); + switch (addr) { + case AC97_Reset: + codec_reset(s); + return; + case AC97_Master_Volume_Mute: + case AC97_PCM_Out_Volume_Mute: + if (addr =3D=3D AC97_Master_Volume_Mute) { + if (val & BIT(13)) { + val |=3D 0x1f00; + } + if (val & BIT(5)) { + val |=3D 0x1f; + } + } + CODEC_REG(s, addr) =3D val & 0x9f1f; + codec_volume_set_out(s); + return; + case AC97_Extended_Audio_Ctrl_Stat: + CODEC_REG(s, addr) &=3D ~EACS_VRA; + CODEC_REG(s, addr) |=3D val & EACS_VRA; + if (!(val & EACS_VRA)) { + CODEC_REG(s, AC97_PCM_Front_DAC_Rate) =3D 48000; + CODEC_REG(s, AC97_PCM_LR_ADC_Rate) =3D 48000; + open_voice_out(s); + } + return; + case AC97_PCM_Front_DAC_Rate: + case AC97_PCM_LR_ADC_Rate: + if (CODEC_REG(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) { + int i; + uint16_t rate =3D val; + + for (i =3D 0; i < ARRAY_SIZE(codec_rates) - 1; i++) { + if (rate < codec_rates[i] + + (codec_rates[i + 1] - codec_rates[i]) / 2) { + rate =3D codec_rates[i]; + break; + } + } + if (rate > 48000) { + rate =3D 48000; + } + CODEC_REG(s, addr) =3D rate; + open_voice_out(s); + } + return; + case AC97_Powerdown_Ctrl_Stat: + CODEC_REG(s, addr) =3D (val & 0xff00) | (CODEC_REG(s, addr) & 0xff= ); + return; + case AC97_Extended_Audio_ID: + case AC97_Vendor_ID1: + case AC97_Vendor_ID2: + /* Read only registers */ + return; + default: + qemu_log_mask(LOG_UNIMP, + "via-ac97: Unimplemented codec register 0x%x\n", add= r); + CODEC_REG(s, addr) =3D val; + } +} + +static void fetch_sgd(ViaAC97SGDChannel *c, PCIDevice *d) +{ + uint32_t b[2]; + + if (c->curr < c->base) { + c->curr =3D c->base; + } + if (unlikely(pci_dma_read(d, c->curr, b, sizeof(b)) !=3D MEMTX_OK)) { + qemu_log_mask(LOG_GUEST_ERROR, + "via-ac97: DMA error reading SGD table\n"); + return; + } + c->addr =3D le32_to_cpu(b[0]); + c->clen =3D le32_to_cpu(b[1]); + trace_via_ac97_sgd_fetch(c->curr, c->addr, CLEN_IS_STOP(c) ? 'S' : '-', + CLEN_IS_EOL(c) ? 'E' : '-', + CLEN_IS_FLAG(c) ? 'F' : '-', CLEN_LEN(c)); +} + +static void out_cb(void *opaque, int avail) +{ + ViaAC97State *s =3D opaque; + ViaAC97SGDChannel *c =3D &s->aur; + int temp, to_copy, copied; + bool stop =3D false; + uint8_t tmpbuf[4096]; + + if (c->stat & STAT_PAUSED) { + return; + } + c->stat |=3D STAT_ACTIVE; + while (avail && !stop) { + if (!c->clen) { + fetch_sgd(c, &s->dev); + } + temp =3D MIN(CLEN_LEN(c), avail); + while (temp) { + to_copy =3D MIN(temp, sizeof(tmpbuf)); + pci_dma_read(&s->dev, c->addr, tmpbuf, to_copy); + copied =3D AUD_write(s->vo, tmpbuf, to_copy); + if (!copied) { + stop =3D true; + break; + } + temp -=3D copied; + avail -=3D copied; + c->addr +=3D copied; + c->clen -=3D copied; + } + if (CLEN_LEN(c) =3D=3D 0) { + c->curr +=3D 8; + if (CLEN_IS_EOL(c)) { + c->stat |=3D STAT_EOL; + if (c->type & CNTL_START) { + c->curr =3D c->base; + c->stat |=3D STAT_PAUSED; + } else { + c->stat &=3D ~STAT_ACTIVE; + AUD_set_active_out(s->vo, 0); + } + if (c->type & STAT_EOL) { + pci_set_irq(&s->dev, 1); + } + } + if (CLEN_IS_FLAG(c)) { + c->stat |=3D STAT_FLAG; + c->stat |=3D STAT_PAUSED; + if (c->type & STAT_FLAG) { + pci_set_irq(&s->dev, 1); + } + } + if (CLEN_IS_STOP(c)) { + c->stat |=3D STAT_STOP; + c->stat |=3D STAT_PAUSED; + } + c->clen =3D 0; + stop =3D true; + } + } +} + +static void open_voice_out(ViaAC97State *s) +{ + struct audsettings as =3D { + .freq =3D CODEC_REG(s, AC97_PCM_Front_DAC_Rate), + .nchannels =3D s->aur.type & BIT(4) ? 2 : 1, + .fmt =3D s->aur.type & BIT(5) ? AUDIO_FORMAT_S16 : AUDIO_FORMAT_S8, + .endianness =3D 0, + }; + s->vo =3D AUD_open_out(&s->card, s->vo, "via-ac97.out", s, out_cb, &as= ); +} + +static uint64_t sgd_read(void *opaque, hwaddr addr, unsigned size) +{ + ViaAC97State *s =3D opaque; + uint64_t val =3D 0; + + switch (addr) { + case 0: + val =3D s->aur.stat; + if (s->aur.type & CNTL_START) { + val |=3D STAT_TRIG; + } + break; + case 1: + val =3D s->aur.stat & STAT_PAUSED ? BIT(3) : 0; + break; + case 2: + val =3D s->aur.type; + break; + case 4: + val =3D s->aur.curr; + break; + case 0xc: + val =3D CLEN_LEN(&s->aur); + break; + case 0x10: + /* silence unimplemented log message that happens at every IRQ */ + break; + case 0x80: + val =3D s->ac97_cmd; + break; + case 0x84: + val =3D s->aur.stat & STAT_FLAG; + if (s->aur.stat & STAT_EOL) { + val |=3D BIT(4); + } + if (s->aur.stat & STAT_STOP) { + val |=3D BIT(8); + } + if (s->aur.stat & STAT_ACTIVE) { + val |=3D BIT(12); + } + break; + default: + qemu_log_mask(LOG_UNIMP, "via-ac97: Unimplemented register read 0x= %" + HWADDR_PRIx"\n", addr); + } + trace_via_ac97_sgd_read(addr, size, val); + return val; +} + +static void sgd_write(void *opaque, hwaddr addr, uint64_t val, unsigned si= ze) +{ + ViaAC97State *s =3D opaque; + + trace_via_ac97_sgd_write(addr, size, val); + switch (addr) { + case 0: + if (val & STAT_STOP) { + s->aur.stat &=3D ~STAT_PAUSED; + } + if (val & STAT_EOL) { + s->aur.stat &=3D ~(STAT_EOL | STAT_PAUSED); + if (s->aur.type & STAT_EOL) { + pci_set_irq(&s->dev, 0); + } + } + if (val & STAT_FLAG) { + s->aur.stat &=3D ~(STAT_FLAG | STAT_PAUSED); + if (s->aur.type & STAT_FLAG) { + pci_set_irq(&s->dev, 0); + } + } + break; + case 1: + if (val & CNTL_START) { + AUD_set_active_out(s->vo, 1); + s->aur.stat =3D STAT_ACTIVE; + } + if (val & CNTL_TERM) { + AUD_set_active_out(s->vo, 0); + s->aur.stat &=3D ~(STAT_ACTIVE | STAT_PAUSED); + s->aur.clen =3D 0; + } + if (val & CNTL_PAUSE) { + AUD_set_active_out(s->vo, 0); + s->aur.stat &=3D ~STAT_ACTIVE; + s->aur.stat |=3D STAT_PAUSED; + } else if (!(val & CNTL_PAUSE) && (s->aur.stat & STAT_PAUSED)) { + AUD_set_active_out(s->vo, 1); + s->aur.stat |=3D STAT_ACTIVE; + s->aur.stat &=3D ~STAT_PAUSED; + } + break; + case 2: + { + uint32_t oldval =3D s->aur.type; + s->aur.type =3D val; + if ((oldval & 0x30) !=3D (val & 0x30)) { + open_voice_out(s); + } + break; + } + case 4: + s->aur.base =3D val & ~1ULL; + s->aur.curr =3D s->aur.base; + break; + case 0x80: + if (val >> 30) { + /* we only have primary codec */ + break; + } + if (val & BIT(23)) { /* read reg */ + s->ac97_cmd =3D val & 0xc0ff0000ULL; + s->ac97_cmd |=3D codec_read(s, (val >> 16) & 0x7f); + s->ac97_cmd |=3D BIT(25); /* data valid */ + } else { + s->ac97_cmd =3D val & 0xc0ffffffULL; + codec_write(s, (val >> 16) & 0x7f, val); + } + break; + case 0xc: + case 0x84: + /* Read only */ + break; + default: + qemu_log_mask(LOG_UNIMP, "via-ac97: Unimplemented register write 0= x%" + HWADDR_PRIx"\n", addr); + } +} + +static const MemoryRegionOps sgd_ops =3D { + .read =3D sgd_read, + .write =3D sgd_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t fm_read(void *opaque, hwaddr addr, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d\n", __func__, addr, = size); + return 0; +} + +static void fm_write(void *opaque, hwaddr addr, uint64_t val, unsigned siz= e) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d <=3D 0x%"PRIX64"\n", + __func__, addr, size, val); +} + +static const MemoryRegionOps fm_ops =3D { + .read =3D fm_read, + .write =3D fm_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t midi_read(void *opaque, hwaddr addr, unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d\n", __func__, addr, = size); + return 0; +} + +static void midi_write(void *opaque, hwaddr addr, uint64_t val, unsigned s= ize) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d <=3D 0x%"PRIX64"\n", + __func__, addr, size, val); +} + +static const MemoryRegionOps midi_ops =3D { + .read =3D midi_read, + .write =3D midi_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void via_ac97_reset(DeviceState *dev) +{ + ViaAC97State *s =3D VIA_AC97(dev); + + codec_reset(s); +} =20 static void via_ac97_realize(PCIDevice *pci_dev, Error **errp) { - pci_set_word(pci_dev->config + PCI_COMMAND, - PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY); + ViaAC97State *s =3D VIA_AC97(pci_dev); + Object *o =3D OBJECT(s); + + /* + * Command register Bus Master bit is documented to be fixed at 0 but = it's + * needed for PCI DMA to work in QEMU. The pegasos2 firmware writes 0 = here + * and the AmigaOS driver writes 1 only enabling IO bit which works on + * real hardware. So set it here and fix it to 1 to allow DMA. + */ + pci_set_word(pci_dev->config + PCI_COMMAND, PCI_COMMAND_MASTER); + pci_set_word(pci_dev->wmask + PCI_COMMAND, PCI_COMMAND_IO); pci_set_word(pci_dev->config + PCI_STATUS, PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_MEDIUM); pci_set_long(pci_dev->config + PCI_INTERRUPT_PIN, 0x03); + pci_set_byte(pci_dev->config + 0x40, 1); /* codec ready */ + + memory_region_init_io(&s->sgd, o, &sgd_ops, s, "via-ac97.sgd", 256); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->sgd); + memory_region_init_io(&s->fm, o, &fm_ops, s, "via-ac97.fm", 4); + pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->fm); + memory_region_init_io(&s->midi, o, &midi_ops, s, "via-ac97.midi", 4); + pci_register_bar(pci_dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->midi); + + AUD_register_card ("via-ac97", &s->card); } =20 +static void via_ac97_exit(PCIDevice *dev) +{ + ViaAC97State *s =3D VIA_AC97(dev); + + AUD_close_out(&s->card, s->vo); + AUD_remove_card(&s->card); +} + +static Property via_ac97_properties[] =3D { + DEFINE_AUDIO_PROPERTIES(ViaAC97State, card), + DEFINE_PROP_END_OF_LIST(), +}; + static void via_ac97_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->realize =3D via_ac97_realize; + k->exit =3D via_ac97_exit; k->vendor_id =3D PCI_VENDOR_ID_VIA; k->device_id =3D PCI_DEVICE_ID_VIA_AC97; k->revision =3D 0x50; k->class_id =3D PCI_CLASS_MULTIMEDIA_AUDIO; + device_class_set_props(dc, via_ac97_properties); set_bit(DEVICE_CATEGORY_SOUND, dc->categories); dc->desc =3D "VIA AC97"; + dc->reset =3D via_ac97_reset; /* Reason: Part of a south bridge chip */ dc->user_creatable =3D false; } @@ -41,7 +484,7 @@ static void via_ac97_class_init(ObjectClass *klass, void= *data) static const TypeInfo via_ac97_info =3D { .name =3D TYPE_VIA_AC97, .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIDevice), + .instance_size =3D sizeof(ViaAC97State), .class_init =3D via_ac97_class_init, .interfaces =3D (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/isa/trace-events b/hw/isa/trace-events index c4567a9b47..1816e8307a 100644 --- a/hw/isa/trace-events +++ b/hw/isa/trace-events @@ -16,6 +16,7 @@ apm_io_write(uint8_t addr, uint8_t val) "write addr=3D0x%= x val=3D0x%02x" =20 # vt82c686.c via_isa_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x le= n 0x%x" +via_pm_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len = 0x%x" via_pm_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len= 0x%x" via_pm_io_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x l= en 0x%x" via_pm_io_write(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x = len 0x%x" diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 71da316052..ca89119ce0 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -554,7 +554,7 @@ struct ViaISAState { PCIIDEState ide; UHCIState uhci[2]; ViaPMState pm; - PCIDevice ac97; + ViaAC97State ac97; PCIDevice mc97; }; =20 diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index e273cd38dc..da1722daf2 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -1,6 +1,8 @@ #ifndef HW_VT82C686_H #define HW_VT82C686_H =20 +#include "hw/pci/pci_device.h" +#include "audio/audio.h" =20 #define TYPE_VT82C686B_ISA "vt82c686b-isa" #define TYPE_VT82C686B_USB_UHCI "vt82c686b-usb-uhci" @@ -9,6 +11,29 @@ #define TYPE_VIA_IDE "via-ide" #define TYPE_VIA_MC97 "via-mc97" =20 +typedef struct { + uint8_t stat; + uint8_t type; + uint32_t base; + uint32_t curr; + uint32_t addr; + uint32_t clen; +} ViaAC97SGDChannel; + +OBJECT_DECLARE_SIMPLE_TYPE(ViaAC97State, VIA_AC97); + +struct ViaAC97State { + PCIDevice dev; + QEMUSoundCard card; + MemoryRegion sgd; + MemoryRegion fm; + MemoryRegion midi; + SWVoiceOut *vo; + ViaAC97SGDChannel aur; + uint16_t codec_regs[128]; + uint32_t ac97_cmd; +}; + void via_isa_set_irq(PCIDevice *d, int n, int level); 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id z9-20020adfec89000000b002425be3c9e2sm13720376wrn.60.2023.03.07.15.48.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:48:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232935; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G/7TZdWIWI2bPNX8WYjN36RNDgq59bbWj+qZFqKNCyM=; b=s4imKU1pSGCI846VbPzI+gH3Zvldo+Pu1mqmXJhhbHsfZYtSTokO+Ixo0RHMYbv++8 AX3rM3XgejjEl9QSIb1+Os5bPqfdP33KYUCUcp4i0RXdPbWCPIe8rbImkB0sWnT5RNG0 Yqw0ZUee9FfJOPqthq/AFgxxxQnm4i6DHWtV9ww7AzTIsJoARv0j890yCq4sdeBUtQMm 3ARWxfZSmLiCTHtt7rpEs5G4nwljHsswPx1ogveNdad1FtLBacW53niKDU/v2dJmVBac P28RBRd7bLhfQhH6W4w1KExD03wTS/namSaFaauTQZmcQAV8ikP7EHsxDbCiGBGsMS9v zlOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232935; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G/7TZdWIWI2bPNX8WYjN36RNDgq59bbWj+qZFqKNCyM=; b=dlb+6OKNk3IWrLC56oP/lfavG70iGX+nh2y7gRvQ3LjwNU23h/5UYo7e+VIDdN0Vh1 gzxVBV13QvCJcYgUepEsG2aytNaLCsXnxFGmYBt05SHxpzqgR7TXDfNGyQnW1VgpRhTy BgsNlyrnG9R4GQW1PBl4meuhuARxrAo6Be2wEVMhT8gxAnDs5YuwjS3XLSxvnL8965WF dEc3WOeHXEwvFDTekvfSdrAEvjcwHtZr28sUrkJ6XsOTXZV2HBEBuU7tY9n0S/OimTTs Mo8QyP6mfEg6AIPF4aXWT8kiSTrB0IafG++jLVX/WUP8zJyjlF7/AzJTvxGomm49ZRJc GHYg== X-Gm-Message-State: AO0yUKXk7Fe2nEpXHjLNEDTFYoHzr3i23w2zki+zBtwkKI4biPUAgVV2 iml8TkwPY9OW/elI5OH/PLNhllm2bm8wlhvK4e8= X-Google-Smtp-Source: AK7set9h8D9mBI07UH1QTrRaK1hXGJ0zQst7fkdZNtBRiXCPVcvKRQilSECdG1sizvvKkToG7d3yFA== X-Received: by 2002:a1c:7c16:0:b0:3df:9858:c02e with SMTP id x22-20020a1c7c16000000b003df9858c02emr14118530wmc.3.1678232934902; Tue, 07 Mar 2023 15:48:54 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 17/20] hw/usb/ohci: Implement resume on connection status change Date: Wed, 8 Mar 2023 00:47:08 +0100 Message-Id: <20230307234711.55375-18-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678233028375100003 From: BALATON Zoltan If certain bit is set remote wake up should change state from suspended to resume and generate interrupt. There was a todo comment for this, implement that by moving existing resume logic to a function and call that. Signed-off-by: BALATON Zoltan Acked-by: Gerd Hoffmann Message-Id: <35c4d4ccf2f73e6a87cdbd28fb6a1b33de72ed74.1676916640.git.balato= n@eik.bme.hu> [PMD: Have ohci_resume() return a boolean] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/usb/hcd-ohci.c | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 6f8b543243..88d2b4b13c 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -1410,6 +1410,18 @@ static void ohci_set_hub_status(OHCIState *ohci, uin= t32_t val) } } =20 +/* This is the one state transition the controller can do by itself */ +static bool ohci_resume(OHCIState *s) +{ + if ((s->ctl & OHCI_CTL_HCFS) =3D=3D OHCI_USB_SUSPEND) { + trace_usb_ohci_remote_wakeup(s->name); + s->ctl &=3D ~OHCI_CTL_HCFS; + s->ctl |=3D OHCI_USB_RESUME; + return true; + } + return false; +} + /* * Sets a flag in a port status reg but only set it if the port is connect= ed. * If not set ConnectStatusChange flag. If flag is enabled return 1. @@ -1426,7 +1438,10 @@ static int ohci_port_set_if_connected(OHCIState *ohc= i, int i, uint32_t val) if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { ohci->rhport[i].ctrl |=3D OHCI_PORT_CSC; if (ohci->rhstatus & OHCI_RHS_DRWE) { - /* TODO: CSC is a wakeup event */ + /* CSC is a wakeup event */ + if (ohci_resume(ohci)) { + ohci_set_interrupt(ohci, OHCI_INTR_RD); + } } return 0; } @@ -1828,11 +1843,7 @@ static void ohci_wakeup(USBPort *port1) intr =3D OHCI_INTR_RHSC; } /* Note that the controller can be suspended even if this port is not = */ - if ((s->ctl & OHCI_CTL_HCFS) =3D=3D OHCI_USB_SUSPEND) { - trace_usb_ohci_remote_wakeup(s->name); - /* This is the one state transition the controller can do by itsel= f */ - s->ctl &=3D ~OHCI_CTL_HCFS; - s->ctl |=3D OHCI_USB_RESUME; + if (ohci_resume(s)) { /* * In suspend mode only ResumeDetected is possible, not RHSC: * see the OHCI spec 5.1.2.3. --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678233035; cv=none; d=zohomail.com; s=zohoarc; b=cf0hgbJuLe8ADs1niS+LsbIns1ar0a6nTFYv2mA+cdzeJm0Eat7JH6sOmFth8tPeXH314KWyb7uob85dtIWbkkBtGC7PuEcum37Jbodq4tiOOfoTlC6twK6j5DCLSU4Q50RQC1hrv23Q+CjKTW4jXiY/FV/7TRcGKFe4RF8CkTA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678233035; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NiawUsU8t9iSDPAS2ynsYcKvAPuboz/5nBfIXoe6khg=; b=UWBRzXcgQBqhR7Pc/LnI1X67BZkGssH8P5D1Fws7lPjaJULByuKUq0cWh4wejAoxM7T9PZkH4DlYTu2v/w2XzQWAQjhNM2fj6yNvm6m6NCUsuucsma9fRyPlf8KBpA7zERAgagy4t365vGsQ4+PbRECjatttC2rnnsYi+BcDw7I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678233035326547.9222378505902; Tue, 7 Mar 2023 15:50:35 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh3a-0005pI-1d; Tue, 07 Mar 2023 18:49:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh3H-0005TE-NY for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:49:09 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh3F-0002tI-Uk for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:49:03 -0500 Received: by mail-wm1-x335.google.com with SMTP id j19-20020a05600c1c1300b003e9b564fae9so177721wms.2 for ; Tue, 07 Mar 2023 15:49:01 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id m13-20020a056000008d00b002c54c92e125sm13988751wrx.46.2023.03.07.15.48.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232940; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NiawUsU8t9iSDPAS2ynsYcKvAPuboz/5nBfIXoe6khg=; b=ngJ7LoAniqn69ZUzCIh7UJjhEzokAG3f6buBP17pRCv/xvcOtkHpRRonnrIWbg92c8 KTMBNjlcBlkxtB717aLR+CMmEOXg0id1s1FAWY4VpTOPFkafo+D8wABZBsSVXSxF/pcG gvYBX9KJZZqxUOfVl/uNrsBfAjo+YKunHqWIC80uHXfLlsegp7FjKy6+y6/CD5AfHePt 0BUoO74+LoBn4fdk1jPxvZrKnWDlvD7phN5ROV8eLxFVfe3bUgoHNwbOq0fYQeUMrv+m Rp5uv1CF7XuIT+LVcx5TzmDTXg5t6xbuVFQV4MGPZfQh1H+qj6gz4mKdJJgYV+bH9OhM PDwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232940; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NiawUsU8t9iSDPAS2ynsYcKvAPuboz/5nBfIXoe6khg=; b=m0hBi6236xH+MMTPYnxoIM8j2NgEmgzQI6iSaj0EPiKBopHNSA5lCtKp2ipmMUhvMH TWL6KxhINjvyTAuP4nlD1RHCPwaFWOZokWD4Fh/B9G5pcWXBAhiXfBGSE607boMvNSJd q55G4njA1W4yzEJO24onx0wpA8ZTXldV8UYdY7NDY/CPI4nNmsqWMT9wZ938wFogvT7y NmwztaWBYw7CrpAaj2O0LbSg7AqncTjGwlI+qKgff2ehgycRiYJyGtVjJB3iq+zpGmSB ovpaXJQJjug+EXHEA+hecJ8pYAifnisn9CJkGuuzXlx/9e3byz3Pw023JMjy4pempuIK WV6w== X-Gm-Message-State: AO0yUKXB95a3CRYCBf4PSXcatNXLyomRzqaQv1SjbQC4PvCeEDmN/7+F u0VR40Hrv5M8g4xXJzImkNH/nJuOWJ/5rAh5Xq0= X-Google-Smtp-Source: AK7set+THg9Dny7OwwXkrer7f6SEhh7Z0Y/Mpfj1rPdzhxXZMSBxkFflGvH7+C3+f5l5tbsyPczzTg== X-Received: by 2002:a05:600c:474f:b0:3df:deb5:6ff5 with SMTP id w15-20020a05600c474f00b003dfdeb56ff5mr14674737wmo.24.1678232940806; Tue, 07 Mar 2023 15:49:00 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Akihiko Odaki , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Akihiko Odaki , Gerd Hoffmann , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= Subject: [PULL 18/20] ui/cocoa: Override windowDidResignKey Date: Wed, 8 Mar 2023 00:47:09 +0100 Message-Id: <20230307234711.55375-19-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678233036408100001 From: Akihiko Odaki This fixes pressed keys being stuck when the deck is clicked and the window loses focus. In the past, Gustavo Noronha Silva also had a patch to fix this issue though it only ungrabs mouse and does not release keys, and depends on another out-of-tree patch: https://github.com/akihikodaki/qemu/pull/3/commits/e906a80147b1dc6d4f31b6a0= 8064ef9871a2b76c Signed-off-by: Akihiko Odaki Message-Id: <20230228070946.12370-1-akihiko.odaki@daynix.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- ui/cocoa.m | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index 289a2b193e..985a0f5069 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -1330,10 +1330,15 @@ - (BOOL)windowShouldClose:(id)sender return NO; } =20 -/* Called when QEMU goes into the background */ -- (void) applicationWillResignActive: (NSNotification *)aNotification +/* + * Called when QEMU goes into the background. Note that + * [-NSWindowDelegate windowDidResignKey:] is used here instead of + * [-NSApplicationDelegate applicationWillResignActive:] because it cannot + * detect that the window loses focus when the deck is clicked on macOS 13= .2.1. + */ +- (void) windowDidResignKey: (NSNotification *)aNotification { - COCOA_DEBUG("QemuCocoaAppController: applicationWillResignActive\n"); + COCOA_DEBUG("%s\n", __func__); [cocoaView ungrabMouse]; [cocoaView raiseAllKeys]; } --=20 2.38.1 From nobody Mon May 6 15:28:42 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1678233038; cv=none; d=zohomail.com; s=zohoarc; b=U2pPlcAyvBnT1klSpb9CJ/a25eYsFG5QARUsFMktiHmV7ZS2hGb+ywX6FJ3B33A+81ga85PikfsmklpUlLUBc7lyJeP0Fu1Y/JFBCMbYWlvMivnJhJtejHykTotmQNv6TtGw4nA+vYyRwtKWLdeNHIELymXB8PpZwz0dqUIOwdQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678233038; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d/943dM73+CscRWT5p4HgkQ0Mpf3ps69VM4jkjUa4hA=; b=Ylkp68/3s6nLBvdokIEo6El2E3KH0tAQsN9r82VcPe7r58vQ5+nXsBfk90VEsOhs7ioxfmJzPTT5S0oD/bnGvmb/MH7MeeCsAzJ8JnXABtoga/GtiiObFwBIsig9nEfyFgTgno1hTnljHnRiTd898PuGS7dlpjlfSYaPh2qtIJE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678233038931752.6615289919597; Tue, 7 Mar 2023 15:50:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZh3e-0005yM-JG; Tue, 07 Mar 2023 18:49:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZh3N-0005ZS-RI for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:49:11 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pZh3M-0002z2-7F for qemu-devel@nongnu.org; Tue, 07 Mar 2023 18:49:09 -0500 Received: by mail-wm1-x32e.google.com with SMTP id l7-20020a05600c4f0700b003e79fa98ce1so156929wmq.2 for ; Tue, 07 Mar 2023 15:49:07 -0800 (PST) Received: from localhost.localdomain (57.red-88-29-179.dynamicip.rima-tde.net. [88.29.179.57]) by smtp.gmail.com with ESMTPSA id f18-20020a05600c43d200b003dec22de1b1sm13849131wmn.10.2023.03.07.15.49.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:49:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d/943dM73+CscRWT5p4HgkQ0Mpf3ps69VM4jkjUa4hA=; b=UEXGQP5JYl6F8NyKaqcNMtpuhKxE7o/SMahDyFKf90VUG91tOEdGgGPLyZHqDZIyMQ IRxKqNvOV60fKkn8iUeghS+hLnIwgv6XZZACF5x0ljQVKwwioYEyVWvmImxPS7EFcedb yZll+xuHtyClQqb9VTOixAVK/DvxaggQqzeWns1cTh/sqSRJCaCa4turo63AG0JM8Yzt lBU6XcWK8KR343+Z9wYcEjDdaZcjUATF5Jjviguwvf4hBd0KLvIaQo6LtMk8mzERSnPF pZcvRi3/qH7Guh/CpQshxNr+zoEoJv+YWkwXL5mFIIfSwuPk7LpZBDoHjEjgs9uQ+kdz zFsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d/943dM73+CscRWT5p4HgkQ0Mpf3ps69VM4jkjUa4hA=; b=PMVx47jomeJY4gupCQEoKkPMAgi4ytG9mT3WSoaLEej1yBKfNnElQi8zFFMj5AeJ/x SL2LEf4cFHOCjFQkJHkNWFUtG5qmkVWG375UMUiYbTUE91OiBKnhb1IRhIkDC7piyKrh xGuEVJxYU5GVy/wZx38WoQD7GSNqw1WCRtdOB+GrY5Ps10cTdNwe+yMwMnE3MmEygYXv cIiKgCNJNiTjELLvHDrhAkkBC0O0IkWed1nun6kdpgG6sjPVeE54Y0wXC2Kw9jkxseYP dvlzh5FbbTkImw7AbbxImMrPsHcFBNRIoc83fI9pWp0WA/qdGfGVISpkXfFfBLUd6bkX dedw== X-Gm-Message-State: AO0yUKU7qmgu8CdIDheE8/mOLuRJFrLxM8D2ZGeF7YZ5DLmV1MhkIZRS pP17JInKSXN2IOmJlkh5a+XATpoYOXJ/sxJDDeE= X-Google-Smtp-Source: AK7set8LzC9p2bAZI6/vk8TB4eMRvMaWijG12eEQ/Sas63UDrdAllqP58bhJ4l/lXNoEb3OcBFxarA== X-Received: by 2002:a05:600c:4f13:b0:3eb:3998:8bca with SMTP id l19-20020a05600c4f1300b003eb39988bcamr14698884wmq.17.1678232946724; Tue, 07 Mar 2023 15:49:06 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, Ted Chen , Peter Xu , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini Subject: [PULL 19/20] memory: Dump HPA and access type of ramblocks Date: Wed, 8 Mar 2023 00:47:10 +0100 Message-Id: <20230307234711.55375-20-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678233040491100001 From: Ted Chen It's convenient to dump HVA and RW/RO status of a ramblock in "info rambloc= k" for debug purpose. Before: Offset Used Total 0x0000000000000000 0x0000000400000000 0x0000000400000000 After: Offset Used Total HVA= RO 0x0000000000000000 0x0000000400000000 0x0000000400000000 0x00007f12ebe00000= rw Signed-off-by: Ted Chen Reviewed-by: Peter Xu Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20221205120712.269013-1-znscnchen@gmail.com> [PMD: Add uintptr_t cast for 32-bit hosts] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- softmmu/physmem.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 47143edb4f..085b3ca6d2 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -1126,15 +1126,21 @@ GString *ram_block_format(void) GString *buf =3D g_string_new(""); =20 RCU_READ_LOCK_GUARD(); - g_string_append_printf(buf, "%24s %8s %18s %18s %18s\n", - "Block Name", "PSize", "Offset", "Used", "Total= "); + g_string_append_printf(buf, "%24s %8s %18s %18s %18s %18s %3s\n", + "Block Name", "PSize", "Offset", "Used", "Total= ", + "HVA", "RO"); + RAMBLOCK_FOREACH(block) { psize =3D size_to_str(block->page_size); g_string_append_printf(buf, "%24s %8s 0x%016" PRIx64 " 0x%016" PR= Ix64 - " 0x%016" PRIx64 "\n", block->idstr, psize, + " 0x%016" PRIx64 " 0x%016" PRIx64 " %3s\n", + block->idstr, psize, (uint64_t)block->offset, (uint64_t)block->used_length, - (uint64_t)block->max_length); + (uint64_t)block->max_length, + (uint64_t)(uintptr_t)block->host, + block->mr->readonly ? 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[88.29.179.57]) by smtp.gmail.com with ESMTPSA id bg17-20020a05600c3c9100b003eb5a531232sm2986669wmb.38.2023.03.07.15.49.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 07 Mar 2023 15:49:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678232952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q0Gy8m0zmWanKLNg2VIR8nQ763VWzHqeUnDf/g3Wq6E=; b=vuJNZ/X+9ojDW1SIMtn46t1c6WH2DNyBAUD9PRXM7JxBq3m0+BwP0X5l0wQUWxzWiM CqxtYJsNUyLzmi8N3UFPIARnsBLclzAydq+9RsIx7Abv98FXKlXeQj4SR2siSErVI0iI bJfKJKjpH8xqaV56wmEEK+pk7H9iQ+j0BJ3ozXaXTiSOh/u69XIKoJTA2T/RR8L5ObZU dEcNkjU1Fj0mdJkqeFQQPxtW4wB6qamNXCa5vUo8tNeoiWYcbE1TMXLIUgoUAwt8Lvrh mp57DT2ekTmqxAkJH+8+5nbKzyfNjQmwenrlE+p7Q2bW7+9UFpb8aplzT5TlXqVxciWP biYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678232952; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q0Gy8m0zmWanKLNg2VIR8nQ763VWzHqeUnDf/g3Wq6E=; b=KuxJFfnWxKQ773NWzQcaR2kJHtg4CxvFpFZ5/HjuQIiYTLrfOaLTnbJfmNa8OCRiM/ GAfs35F+za48rPAerxQzptW4yN1mtjpsgHFRF/KqGef7MQOIGNjP/esjSNNxpHqRAy0y OSifBJusGTIR06WrjkU/DY1681wQ3cCoPv/5EuYvPpN/I2HQmhRxo+YcfO/moHvGXTZJ ToYKnJttVqtwHFp2Bxjr2n0cE+pQjw9PEQ/Fhge7022hCLQF+LXkoEejF+cOwd911UF2 6P/CZpWO/h+O6agBcZc4Q6s57pr79qP4gC6Q1UKdGLac+xZTKRGR/9sWvpMkAnJMPWiT tXZg== X-Gm-Message-State: AO0yUKXm0lsO+k6UPOp+YqX3j2lltJrDO0TBhAsVjabTBgOdM5JPD7Yd TwPIqidQ3+Rkc69HGKXkD2V81TUvWAtzprYzh3k= X-Google-Smtp-Source: AK7set+QspUI4ObReOZirHw1ZLkfU/EqeEZRwbncv13zWZUj523L1Iopd8RG6TJ7ZA1slXJoTNUz2g== X-Received: by 2002:a05:600c:3502:b0:3e1:e149:b67b with SMTP id h2-20020a05600c350200b003e1e149b67bmr14360113wmq.18.1678232952221; Tue, 07 Mar 2023 15:49:12 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 20/20] log: Remove unneeded new line Date: Wed, 8 Mar 2023 00:47:11 +0100 Message-Id: <20230307234711.55375-21-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230307234711.55375-1-philmd@linaro.org> References: <20230307234711.55375-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1678233028394100004 From: BALATON Zoltan The help text of the -d plugin option has a new line at the end which is not needed as one is added automatically. Fixing it removes the unexpected empty line in -d help output. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20230119214033.600FB74645F@zero.eik.bme.hu> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- util/log.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/log.c b/util/log.c index 7837ff9917..53b4f6c58e 100644 --- a/util/log.c +++ b/util/log.c @@ -489,7 +489,7 @@ const QEMULogItem qemu_log_items[] =3D { "do not chain compiled TBs so that \"exec\" and \"cpu\" show\n" "complete traces" }, #ifdef CONFIG_PLUGIN - { CPU_LOG_PLUGIN, "plugin", "output from TCG plugins\n"}, + { CPU_LOG_PLUGIN, "plugin", "output from TCG plugins"}, #endif { LOG_STRACE, "strace", "log every user-mode syscall, its input, and its result" }, --=20 2.38.1