From nobody Sat Jul 5 01:15:02 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678295279764817.8374128529798; Wed, 8 Mar 2023 09:07:59 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pZxDp-0003dS-Qa; Wed, 08 Mar 2023 12:05:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZxDa-0003H9-HF; Wed, 08 Mar 2023 12:04:46 -0500 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pZxDY-0005ZE-Ox; Wed, 08 Mar 2023 12:04:46 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 42573400C3; Wed, 8 Mar 2023 19:58:19 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id D02AC13A; Wed, 8 Mar 2023 19:58:17 +0300 (MSK) Received: (nullmailer pid 2098270 invoked by uid 1000); Wed, 08 Mar 2023 16:58:15 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Klaus Jensen , Guenter Roeck , Keith Busch , Michael Tokarev Subject: [PATCH 09/47] hw/nvme: fix missing endian conversions for doorbell buffers Date: Wed, 8 Mar 2023 19:57:12 +0300 Message-Id: <20230308165815.2098148-9-mjt@msgid.tls.msk.ru> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230308165035.2097594-1-mjt@msgid.tls.msk.ru> References: <20230308165035.2097594-1-mjt@msgid.tls.msk.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678295281348100001 Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The eventidx and doorbell value are not handling endianness correctly. Fix this. Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support") Cc: qemu-stable@nongnu.org Reported-by: Guenter Roeck Reviewed-by: Keith Busch Signed-off-by: Klaus Jensen (cherry picked from commit 2fda0726e5149e032acfa5fe442db56cd6433c4c) Signed-off-by: Michael Tokarev Conflicts: hw/nvme/ctrl.c --- hw/nvme/ctrl.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index ac3885ce50..83f5e58e8d 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1333,8 +1333,12 @@ static inline void nvme_blk_write(BlockBackend *blk,= int64_t offset, =20 static void nvme_update_cq_head(NvmeCQueue *cq) { - pci_dma_read(&cq->ctrl->parent_obj, cq->db_addr, &cq->head, - sizeof(cq->head)); + uint32_t v; + + pci_dma_read(&cq->ctrl->parent_obj, cq->db_addr, &v, sizeof(v)); + + cq->head =3D le32_to_cpu(v); + trace_pci_nvme_shadow_doorbell_cq(cq->cqid, cq->head); } =20 @@ -6221,15 +6225,21 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeReq= uest *req) =20 static void nvme_update_sq_eventidx(const NvmeSQueue *sq) { - pci_dma_write(&sq->ctrl->parent_obj, sq->ei_addr, &sq->tail, - sizeof(sq->tail)); + uint32_t v =3D cpu_to_le32(sq->tail); + + pci_dma_write(&sq->ctrl->parent_obj, sq->ei_addr, &v, sizeof(v)); + trace_pci_nvme_eventidx_sq(sq->sqid, sq->tail); } =20 static void nvme_update_sq_tail(NvmeSQueue *sq) { - pci_dma_read(&sq->ctrl->parent_obj, sq->db_addr, &sq->tail, - sizeof(sq->tail)); + uint32_t v; + + pci_dma_read(&sq->ctrl->parent_obj, sq->db_addr, &v, sizeof(v)); + + sq->tail =3D le32_to_cpu(v); + trace_pci_nvme_shadow_doorbell_sq(sq->sqid, sq->tail); } =20 --=20 2.30.2