From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306828; cv=none; d=zohomail.com; s=zohoarc; b=lLHPZEnUwPVqagMwizsyk0ydwsCnU1qqO6jZEwIgVJdwHtto+wA/qaMJ8JTWd7IYU+iRedGo3NmYVs6wGUQ3YMpNG8AmqmMHAgDp49PbZh0G2g0ghJUU2TSGhqu9pN+qExNZJWCQG6vgK7P5HtX2lrYw4I5iBBxtWHXWN9bj69U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306828; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h0P1UnDjGy/z/U1aQi6eJShdM9aLBbZfiZBKn3C8EKc=; b=d21SlNSwR7yg8hNXHWJBcrTtYmEZjTRSuuWMZfOwyJ9Kkh/t7ue15CxjplCGflhp+6ZbOpaT/y81PuVxuhSSnGV/69VpMhgnFkZ82AI7Qz+r06JG+hGtZFMrJomzsXZtveGkuaPRh3F86z4ZG+AG42BlTWurgHBcOEB7tmeltLs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306828760925.1131977616074; Wed, 8 Mar 2023 12:20:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0GC-00082m-5p; Wed, 08 Mar 2023 15:19:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0GA-000829-E0 for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:19:38 -0500 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0G8-0002SF-Qx for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:19:38 -0500 Received: by mail-oi1-x230.google.com with SMTP id bj30so13126727oib.6 for ; Wed, 08 Mar 2023 12:19:36 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h0P1UnDjGy/z/U1aQi6eJShdM9aLBbZfiZBKn3C8EKc=; b=S5UztB6HOpAE75hStorc8hS8RBX+AyVbDp8ygLc3fHWFEnaG4R7KvtYWetr9KyARFn K0bgz4zvJimiC9bRwtTJYtUYrqajA87HJNWF0QxrqSg20U7qm7/yHe+Tj2on7zYiZv4N xtSE8JVUUG6fQXdu7siEQb5YL2UHldz1sVPO6KEEw0lU71RyzZbSyPT5WDs7GVkLYw2y bq8SZAxE9LaWbk4SYrUeNHUmqFvsm5myqXBj3O0Q3C1suFkeuZOQe5f6WSs573rSaBLI vHjcvSqHACX8eObX7bsgJ8g9o7o31itPQ668jX8wr5APlY/zKe42c//x/foywukZf5W4 lMPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h0P1UnDjGy/z/U1aQi6eJShdM9aLBbZfiZBKn3C8EKc=; b=y9l/nanSYQ9GPoMmz7sexg6a7JFApvRNvU3faAMQkf7sTCAeentWG/UbQGuBRNZpZw mHOF7OY2cwa4QTJGU5GFTeYK3O1UAb/nOU6eIsurh4S+98m6/oJ0ZClU/260r3VsNEd3 J18wyGFGijID4WXYWpnu6yEMpIjMMBTzT4A6dMwTHrwLdATZkXdFK6IEgretWLTBMYEQ LPkOsqhygZuijmUpnJ5SahqwuJfGQoKX6OhuHys85R4h3B+m3nfu8XAHUGQSJsBXx8/l NzGaPoD1nbHHDJjtQZpmf71ax4Tcg+m1ZELFGz7bgmvy4frt2+RBQATWfX7UI5NkqWGA gd8A== X-Gm-Message-State: AO0yUKV5OccwoCaBI9r0Ij4INOnDtknl2iDCmdUiEddR5l9VwgTxOeZE H7BA6cO4p0XLsaDhdwiZaED17zOJw37wM2epxP8= X-Google-Smtp-Source: AK7set8pZ5HYEkcxDHCTqvxnTmKWOK3KOP/vhuBGikudeCR/iWUWL4qIdUbMTNxsPITTXWuZTOywBA== X-Received: by 2002:a05:6808:344:b0:384:6ae4:afe8 with SMTP id j4-20020a056808034400b003846ae4afe8mr9004426oie.47.1678306775420; Wed, 08 Mar 2023 12:19:35 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 01/17] target/riscv/cpu.c: add riscv_cpu_validate_v() Date: Wed, 8 Mar 2023 17:19:09 -0300 Message-Id: <20230308201925.258223-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306830854100002 Content-Type: text/plain; charset="utf-8" The code that validates ext_v in riscv_cpu_validate_set_extensions() is not properly indented - we're missing an extra indent level right after the first check that uses cfg->elen. In the end the 'v' verification is a bit too large in comparison with the others, and can be put in a separated function to enhance the readability of riscv_cpu_validate_set_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 83 ++++++++++++++++++++++++++-------------------- 1 file changed, 47 insertions(+), 36 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..5060a98b6d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -802,6 +802,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disa= ssemble_info *info) } } =20 +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + int vext_version =3D VEXT_VERSION_1_00_0; + + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + vext_version =3D VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -993,44 +1033,15 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) ext |=3D RVH; } if (cpu->cfg.ext_v) { - int vext_version =3D VEXT_VERSION_1_00_0; - ext |=3D RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN= " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN= " - "in the range [8, 64]"); + Error *local_err =3D NULL; + + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); return; } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version =3D VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); + + ext |=3D RVV; } if (cpu->cfg.ext_j) { ext |=3D RVJ; --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; 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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Urkftsk9UwUaTCcoEU1Jq3jTCffHbJotteipZdlPPs=; b=Jcl8xVD8tSrTsOe90piusPEXOhv6bxt8wCA9i3GplK1HNWghsCe8RIVFA3jXMk16rx Hecd2EZHc1/1NSkExJ4EYsDlyB84MpFk7N5g2uCTuPCDuzxBHCku15kAxhFDOeOmpQd0 vfNKiarO0GBvMKZ1y/Y2A868m7veII7J9PnbYchyAjd28v/MHeHYw/dmYTgdVoQ92sVe iinQHzT4jkKUWEyCmQWEQH7R5erImSY48w/tsJDElyLri5w7AynSxJT9Nj3X7CLX03sN L3Xt5nC1g4TXxM/JIHDwYYdYYYISDkTWk3mYeUfwQhJVWq7mt5/roE5u1zd/SZnb45PA oPYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Urkftsk9UwUaTCcoEU1Jq3jTCffHbJotteipZdlPPs=; b=bsqxxYBCD7WhV3QLV1VwrkqxxzUT/boSB2LNKG20hML9h8mcEe2YQ+bHEp1Xq893LR 8tfR14V7wCz65I+N4zkmo8ambx54E6XTb+EnWs9iedKi3ByD1xH1WRfJN8L7LihPOKyt gqtW0ypul8W7OUuDMgY1xfTbeObo/Jh5SD4RLdIgxS0vdnybZM/ZpCRLogwXmYdr5VFj uA6LGpzhwV5LoD3Kk5+mcu8FtQwFnQg2+WKLT/juYZAWtZ9wt1VoWt1BjJzwpM9oz+Ah xsupaxVWtU5GHbyJHjV0VfCuzvo/tX7zzFuKe3wrHl+/jlQPWYhF1n51QRfzwVsSPd9P k+iA== X-Gm-Message-State: AO0yUKUqj/AfJD1VtrEUy+d+LFz2j2F+4XCBbP0xSwT5jPht00Qp2l95 sl99JeDFz7Y8i8UlRyUYegyEX13cAxUbWXiG3dw= X-Google-Smtp-Source: AK7set8ecL23ia4i1AMbOJHEPbxyo9grsACP+W51rUZ3sLJbGEwYxP16zdL3Lw9HRc8Xk/6RVJGAgg== X-Received: by 2002:aca:1204:0:b0:383:eec0:7564 with SMTP id 4-20020aca1204000000b00383eec07564mr8568146ois.38.1678306778234; Wed, 08 Mar 2023 12:19:38 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 02/17] target/riscv/cpu.c: remove set_vext_version() Date: Wed, 8 Mar 2023 17:19:10 -0300 Message-Id: <20230308201925.258223-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306886632100003 Content-Type: text/plain; charset="utf-8" This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5060a98b6d..0baed79ec2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -245,11 +245,6 @@ static void set_priv_version(CPURISCVState *env, int p= riv_ver) env->priv_ver =3D priv_ver; } =20 -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver =3D vext_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -839,7 +834,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RI= SCVCPUConfig *cfg, qemu_log("vector version is not specified, " "use the default value v1.0\n"); } - set_vext_version(env, vext_version); + env->vext_ver =3D vext_version; } =20 /* --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306893; cv=none; d=zohomail.com; s=zohoarc; b=g9WWUHROdCguU53mrvh68DnITGv5UMsRmzzDtfgtW3annypTws/20dgV5afwMedZymR1ZKAmpws5G5bA0t9ih9m6yoYScSrNvcYBO9vyjM4Pcf9Bu1etJIkbGfNBcsCD6pE79Zt52ipyAUSKQx3yZ3UgxKKRzl0km22BpiC0CvE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306893; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tpRZhkJlHC/x0Vht0jAUjaGoR/S+k4KvktgH+tlcXTc=; b=d/YTNg8kmf0fNg47b5ogh0Zh8jO8M4INmU7q8460DMSWbyCGzXzovOwj5L7ejtbdMxTJhnLV3qxCy583imEggmHmcHELnMVIwb8nvqmQnVJiprcYN5pbLYoxiDOZeGLAXcBxKxztfFLJ+ENc7NfmV63f7DW0W41vj2AQ9A8B7RE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306893848559.220146269778; Wed, 8 Mar 2023 12:21:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0GH-00084k-Ql; Wed, 08 Mar 2023 15:19:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0GG-00084K-9O for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:19:44 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0GE-0002TN-Je for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:19:44 -0500 Received: by mail-oi1-x22f.google.com with SMTP id s41so13089760oiw.13 for ; Wed, 08 Mar 2023 12:19:42 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tpRZhkJlHC/x0Vht0jAUjaGoR/S+k4KvktgH+tlcXTc=; b=TKX+HPAtYs1swPsWXAWunjPLJHORtCbYWWi78FB07s97BB5zzaJD2l66ZOQj7XKqAs u+l5e95IkwPUrxUiNRehgXoQv4TtfnvIDQ6Mi0Y3hfTRr6CjibxN2AmjMlju0G3u3Ros vlxpyNrY/oycUUbQc75Emba/EJSu5IuO67arV0kCqDF69+dnDk1qFd6dReqkGTkWe0AC QbsJI+l4ezMHZnGmjn/FkLSN2/G0DlNtTkShTvIZRI65RLBjdch8ILfiGR9hbx6bqb8E f/Tmcb5c1gNgSpropPiRcxof2jWKolDuhuzriz2KY8EtuP2QM8Kvy6vNombVoUJwEY5d GZgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306781; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tpRZhkJlHC/x0Vht0jAUjaGoR/S+k4KvktgH+tlcXTc=; b=LwgI1zs+D+4PdEHGgFZRHnUdGLOvNuIel26ZbxM8IaJDEXnSsG4JF2Cmz+MKYRGgLn aHKAI5W18vJXExeyej1gDTzO7/kwipKYHrI7/SuTZHA8pf70fuk3SMWx/CeqL4zg3nUz N24lWEEAgA5fNyhVFnYrz8XwoFuni0xvECETmH0GBXyxJv3MAwIn+2G5irkRxQ7vyBuV q/UKriZVCWLK8MtVgyRdq3HSsofDDWi0EJsgCnYrv3qcpuy8HdH8sGxWAF+O9UUlPRpO kiclGWWsETTGfAiNDhK2Rd6ZtGIu6C8k8R3x2+QZMboAGA4VU2UY3V/PT1y3XD0J5F91 5gBw== X-Gm-Message-State: AO0yUKWRN7kwcRptePj0A5OnOmNR4D3rUpBiahyVQGyzJKkK3RobaULK A96Lc7lbXDXqm9MmceuNzWpnmiE+qDzcknoTMcs= X-Google-Smtp-Source: AK7set/DFtZuIZ1jFQyEcwrtfbuhz7ItkPSZCi+5x6Rk+rnQ28zcs84hxZmOHixlnpLvrXibaFe9hw== X-Received: by 2002:aca:f0f:0:b0:37b:385b:c965 with SMTP id 15-20020aca0f0f000000b0037b385bc965mr7716782oip.2.1678306781211; Wed, 08 Mar 2023 12:19:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 03/17] target/riscv/cpu.c: remove set_priv_version() Date: Wed, 8 Mar 2023 17:19:11 -0300 Message-Id: <20230308201925.258223-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306894596100001 Content-Type: text/plain; charset="utf-8" The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0baed79ec2..964817b9d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,11 +240,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,= uint32_t ext) env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver =3D priv_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -343,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; register_cpu_props(obj); } =20 @@ -355,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -366,7 +361,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif @@ -379,7 +374,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -392,7 +387,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; =20 cpu->cfg.ext_g =3D true; cpu->cfg.ext_c =3D true; @@ -431,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -444,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver =3D PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -454,8 +449,9 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -468,7 +464,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -482,7 +478,7 @@ static void rv32_ibex_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver =3D PRIV_VERSION_1_11_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -497,7 +493,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver =3D PRIV_VERSION_1_10_0; cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1159,7 +1155,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) } =20 if (priv_version >=3D PRIV_VERSION_1_10_0) { - set_priv_version(env, priv_version); + env->priv_ver =3D priv_version; } =20 /* Force disable extensions if priv spec version does not match */ --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306951; cv=none; d=zohomail.com; s=zohoarc; b=YVr68JGUVcDsPqpgpQneBPAYkySopv2xLmloZtL/CVn3tPxED1ZcLmbG6//kQk/cGKQft8lDzWtgX+zbr1E1SFVIJc/DKCLiCbC5cmMlzNZj1ppQEyQeYlJ4fx7VGzRRRnyeL6UaaRv1gmLP82k5zM9c7lwo0YJ+5UiK/3zrfwo= ARC-Message-Signature: i=1; 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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MllaajdX1fwdPjFAr0zO+Y5CuLxZh/hvmr+W4o52MIA=; b=oKwH+a/uYB1Zm/1so0aVursroSJUsRdiguLnmxGOovItJX/SZ8KFrCbT20DY7P84fk P9pYNwTNYMfHEd3aiQs02PWlLc/7sI2AQdNCMZHQ95YEDGJ/FKinjMyknK/NfY5+JUM7 q8zIy0c5BnFxDlVNpgwptzpxLlQ+Q4S2sTlNT9A8xWEZDWra45BI7HeYiYyoicJ0ueWV NAItbmvtFsF5O4rOaezlE2JVn5iYvo1Z9aKQzdscfa/x/3/aWRgkXeJ0WTeYn7/mi+1s vSqPHXNrKy7p1pd0aZN4j3eYNRVJfW4HYaJe0W2UCea8bmxlSmVYIUsR7wRkYMcaaBWz TO/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306784; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MllaajdX1fwdPjFAr0zO+Y5CuLxZh/hvmr+W4o52MIA=; b=wZfPxMnzm9ZjqXMbuTrnV/QCpjKBBud9iEWKeTqjX6HRn9tfM/oGiivn7LLi7DDW8C w8PxYJvmcFzNlgA7bY+VI8P8I99Ywe+g0Sj92wxH4ahmvvP1AYxcCE6nyuthuWbUf3iZ /JRSwNLjkUPKH2SpTxa8e6ZkcvqQRGwRVaM0+ozUi+hbO+1U+7+eFSmMIz/fLJVu9iXX XUv+8AxguWf0dB/hab1VB4xao9UhkFQSP4AbLlLYDzf7tIwMRWjeHnDIjo9tgUeTyJKP 1TGrxvHY2RrMsd6u4KG3pyJO/LDquvPz2RN/BW4lM8GjvCBfqJ7E/nzW5ffQYvCnzu/k cOUg== X-Gm-Message-State: AO0yUKX3bOzTXH/vOk9xRL3w6k/ckbVyZgOqhK7Po5npxSXa/F2iC8Kr C18akvrZzBkUSlZjsoQ2X5znd4iwyacuTaGHkys= X-Google-Smtp-Source: AK7set8hhSuHJlaeRmUQQSh5A7lmaRJ2v8lh+R8+f79TGi4TEDwCB7EBG+NaDeYNIGRryPoggHamIw== X-Received: by 2002:aca:f0d:0:b0:384:416:19e3 with SMTP id 13-20020aca0f0d000000b00384041619e3mr8941567oip.52.1678306784133; Wed, 08 Mar 2023 12:19:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro Date: Wed, 8 Mar 2023 17:19:12 -0300 Message-Id: <20230308201925.258223-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306952973100003 Content-Type: text/plain; charset="utf-8" PRIV_VERSION_LATEST, at this moment assigned to PRIV_VERSION_1_12_0, is used in all generic CPUs: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() When a new PRIV version is made available we can just update the LATEST macro. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 964817b9d2..62ef11180f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -338,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif =20 - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; register_cpu_props(obj); } =20 @@ -350,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -426,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -439,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - env->priv_ver =3D PRIV_VERSION_1_12_0; + env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..af2e4b7695 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -89,6 +89,7 @@ enum { PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, }; +#define PRIV_VERSION_LATEST PRIV_VERSION_1_12_0 =20 #define VEXT_VERSION_1_00_0 0x00010000 =20 --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306938; cv=none; d=zohomail.com; s=zohoarc; b=EQLYTkHWH7ugsAGq+O5nv4gYiK6grvweCClxy5c+F3riUqXLK70weLgXGTXIIMb7/n3R3FHT8Sne87vTX5QGsp4//pM4kq5Xsx4bBC4PAxw3OQefm7cLdib4EkyD/BoRI2lIj1zkAKi+yfuKo2dwvCHeIZGS7KeOCDqd2QSx+po= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306938; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ULwmOEdWnWF+cKmfjxbMQCB8XtgNhk0EBmqOCSnzuZM=; b=OtBymd+pJDYrVwlK2qULEJEZB0Y1Cfzds2zvpsphPgR7xSNJboTsfJclst2rFxVBXuaWAJbRUI1dM64i/AgpDJwOiNRg/5Ca0IYYPI94Y1LsdOAcNETvJo3wsIntyW2b/cO395/WrUDG/VpDabKkaCKYLsg4gCKUHlqor/IFx7A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306938120764.4033009143362; Wed, 8 Mar 2023 12:22:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0GO-00086u-1v; Wed, 08 Mar 2023 15:19:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0GM-00086M-Id for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:19:50 -0500 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0GK-0002So-Aa for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:19:50 -0500 Received: by mail-oi1-x232.google.com with SMTP id bm20so13110043oib.7 for ; Wed, 08 Mar 2023 12:19:47 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ULwmOEdWnWF+cKmfjxbMQCB8XtgNhk0EBmqOCSnzuZM=; b=Je8SCk1PfRvjJJUVlU4mehUf19+KInBGtK1B43fHHuh7dWaEKIhWPrYn2h4ILh6qyW przofU+xjOuXMU3PkPoto9HUuwOnMCP2k4BRSyT4YsM3yFh58iPI+LLMUlIbhA0wq9Ik jgQA0+FyodkD8L+Id52BR2dC0pnXYuUlkSYUQKme7zqn8T2tHPmzZ4dWmIMg02cUWJaw bFHIglTlbHhduLy7v7Aqj52JtVpW2iw0ZVBaXYF9b0KxQIQuGGs+V3BST+i7j30+1OX2 eYGMPMTU5FbKDxCAsd/FDKYv3CRlMNWAqH8n1yTrjWsnjKqzkyE9vF3mJe0DVXpfgozf ygIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306787; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ULwmOEdWnWF+cKmfjxbMQCB8XtgNhk0EBmqOCSnzuZM=; b=Mal8pe3geSmnCYaCBvmq76uQDvuSVTB9FbWsS5/XVdXMIMFvZDcAXZybA6WbHM0CQp Crhm1bPptrYAch+iujUu1XbXtBWI2Q6pe5F7k5/ceEz5B7KFFO9WciOO3VqvHvrYduhj XjoEBq4sLA0cGLnPTK/h+RcPlzzMkskXFI4LUDtfLqaKg8K5A1oDohKxDk/j7oIt/EWn TavKf6nNLU6hErLn3qinQPCYhHbm0/VE/vt3Tpr2QpHhEvuQnCdK9bAXjsq9j1cf7bAr FUqISb2DTMNTJg7jvtdz04732bOFbafC78mrkXu3fFyfwlyILhH3rGF1dIyCgD7RtX0g YCbA== X-Gm-Message-State: AO0yUKXVECEThfqGGyIN4fqaICsfi/TNRle7TYUN2FbL9m4wetiXD0Jo m28xR1Fvf2ap4KDSgPTImyFNFAMI4WE6lLzSu6s= X-Google-Smtp-Source: AK7set/FwRACjr5Qhkqjmrt0fuqClPdR0IowRC7Uz6NkYIBAIb3SRnDb/LEPshayWbIBwGyr9pcOfw== X-Received: by 2002:aca:2311:0:b0:383:f4fb:be63 with SMTP id e17-20020aca2311000000b00383f4fbbe63mr7817519oie.37.1678306787206; Wed, 08 Mar 2023 12:19:47 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 05/17] target/riscv/cpu.c: add riscv_cpu_validate_priv_spec() Date: Wed, 8 Mar 2023 17:19:13 -0300 Message-Id: <20230308201925.258223-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306938891100005 Content-Type: text/plain; charset="utf-8" Put all the env->priv_spec related validation into a helper to unclog riscv_cpu_realize a bit. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 81 ++++++++++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 62ef11180f..e15f829edc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -833,6 +833,48 @@ static void riscv_cpu_validate_v(CPURISCVState *env, R= ISCVCPUConfig *cfg, env->vext_ver =3D vext_version; } =20 +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + int i, priv_version =3D -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version =3D PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version =3D PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + } + + if (priv_version >=3D PRIV_VERSION_1_10_0) { + env->priv_ver =3D priv_version; + } + + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -1130,7 +1172,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int i, priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1139,40 +1180,10 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) return; } =20 - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version =3D PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version =3D PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version =3D PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - } - - if (priv_version >=3D PRIV_VERSION_1_10_0) { - env->priv_ver =3D priv_version; - } - - /* Force disable extensions if priv spec version does not match */ - for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - isa_edata_arr[i].name); -#endif - } + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; } =20 if (cpu->cfg.epmp && !cpu->cfg.pmp) { --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306885; cv=none; d=zohomail.com; s=zohoarc; b=izMWILKrIVhuPsdtyRqU1x7f369iZS5H/yDky1PRkt/MGXLYiIH4G9wrZM/9BQb59ZPKzRvUfqfLh+03LVue0QjumPyDIgFn7vhkIA0mHjhTbVoTmJbtfXICNYmP3l98ff7XRaN+KeRMU2V2m1d5h7Y0e/cMSlw6b4xLbyMBrSY= ARC-Message-Signature: i=1; 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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xsh1iCWD9Y32A+LimVSP5RAfzDBl9hWshDY0NEwDdpg=; b=FEBS5Tasc60jkmXQiMAQy9bLProHRH247hGmBfPlWHKJwggg5vo6RuCiBr0g+kIiie EHskP60EZJdH0OKYCOa3h+URwoS4rlUx/4s8f1KWjk4uYobleYAuTooqG73p+mgTqAMa D7+ZjEBK7MyyypHIMeYAOsAoiRkLIJzWS8EqKq62o692ElhFPLSa/eqADbkITFL6Bruj OJ9JqowaTvNZd+OjUJjqR36/Gcje1favXLZBZS/iACyicNuVANgJmPFMqr2NBTECJZdb b9rBnoZ8clB7TVjbaKtOg6URPzaLpXUhUN10bTxJ/0EFPC22jbuhRR/BpTqd5I/nvuRW /qfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xsh1iCWD9Y32A+LimVSP5RAfzDBl9hWshDY0NEwDdpg=; b=MgFQ7JLxKBdmNLe7OMvCq7Vd0mAEWLjEW9Nwup911HpYwmoaJicHwohXhI04oIbYxi eacEUW2mTIfxyNGESgN6bbWAZK7E89kMzJNltE+P7JCdtj/UGEM6WBByIKO4gcMYiUT2 n+iyKobUj3UGErWwAMlwKWkzRjETY/pC4qoyzK76kckxOw2E3KsjGdRb3Nn6/e8RR2ky 3y8UJm62K+aHSXAAVE9mW50jlWi324cHtn2mduU8rmmVJAxF1WMIQd+roGr4o6+7tqyy HDwlR641BZDngbK19cxIi/JWKY7QiFsii6MXosaVMsaDEB7hcTg67jf1bMhHZLxQcXOt XZUg== X-Gm-Message-State: AO0yUKX2AEFljF0l0rm0w3MnmzyVH/4olZyIsJytAGKi9ymqzGjy5FDO r5j7Y+fxtWN75he64rQJ0x+gj785c9UflQkVwTE= X-Google-Smtp-Source: AK7set9e+dNxmmH4B5KQSsvNwte59vXOlgmk0GU4i1/M6cZGujvR4HyQCwoHSw20jiBf/8xA/wVXvQ== X-Received: by 2002:aca:1912:0:b0:383:de45:6d87 with SMTP id l18-20020aca1912000000b00383de456d87mr9778254oii.28.1678306790081; Wed, 08 Mar 2023 12:19:50 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 06/17] target/riscv: move realize() validations to riscv_cpu_validate_set_extensions() Date: Wed, 8 Mar 2023 17:19:14 -0300 Message-Id: <20230308201925.258223-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306886647100004 Content-Type: text/plain; charset="utf-8" Center all validations that are scattered in riscv_cpu_realize() in the same function. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 74 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 39 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e15f829edc..e2cd55320c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -881,9 +881,43 @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu= , Error **errp) */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); CPURISCVState *env =3D &cpu->env; + Error *local_err =3D NULL; uint32_t ext =3D 0; =20 + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); + return; + } + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + assert(env->misa_mxl_max =3D=3D env->misa_mxl); + /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && cpu->cfg.ext_a && cpu->cfg.ext_f && @@ -1066,8 +1100,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) ext |=3D RVH; } if (cpu->cfg.ext_v) { - Error *local_err =3D NULL; - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -1169,9 +1201,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); - CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); - CPUClass *cc =3D CPU_CLASS(mcc); Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1180,51 +1210,17 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) return; } =20 - riscv_cpu_validate_priv_spec(cpu, &local_err); + riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; } =20 - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support= "); - return; - } - - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); } -#endif /* CONFIG_USER_ONLY */ - - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - assert(env->misa_mxl_max =3D=3D env->misa_mxl); =20 - riscv_cpu_validate_set_extensions(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - -#ifndef CONFIG_USER_ONLY if (cpu->cfg.pmu_num) { if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpm= f) { cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306946; cv=none; d=zohomail.com; s=zohoarc; b=ANEC/Ck8uFHQkL0OXWQealEOfHJpfgcKnIdteEWx5hM5JE8iujbkLGfvthf2J9cKC4BgK8FZg+nsUzQnfOwLhtPE7LLx7QZtCasSia/6GWR3u8sVSYlAdk3ZeonbGaKY6TpTIHktL776qQ+URo/V9EK0ISluEIJrwTz4bxQRk0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306946; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bQEp3uxgQUjVhkMRfKKD7zfqhzNbCepUcFSG6WZW69g=; b=hoFT0jcsvjYZGrb/8q0gJpgX7p1THMyQdVdCOBAHXWKgiDMz8HygLzCf3LQTw2wdHr W0m3c4b/iK5RRwZ2vk4x4QB4LXfXm/U1/RRgcBSa3hUVyOwV8l1CE66IsFBndVFtohOo 9J2zkVXGSoIkV0yuRdkTT2FJtvOvIAPcf+550fQ7qwzQrftTrpNG9QRpLH5v0X/PrfHk 0gfley302IySTnGClqzd9GKVY0v63AqrALCI0lSrh0OVutJ2dnAwmmyGeVSOAdo4FHaO JQ21qivdRLehtD5Zv2wxq9syReC4OEsCd8ZdjrQLZNUrZepwUG+axBqMLF9YzfrRcPQ/ vJ4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306793; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bQEp3uxgQUjVhkMRfKKD7zfqhzNbCepUcFSG6WZW69g=; b=kfYuhC+zStqrSHlapDHr76kmO1pSZyfJRXwHQNSrvQDct7d9AVC2T/2xwCjq/it4Wq O/MSZ0CzEOvzcar+Gsd2nNP9FrZMXppxnUBUwSLptxPxxzyGj35wnyUlFjgzZfFc8J9c RxJ1Ug1DFiWXYw0FnTj76HZkSpV1bs3rqccdmDyCKFtSp4KW6C12FJz1MbKpELfmdVti W0GW2aWAdvRD6ud4wpWn0J81P2ElK3hD9D7Z2pPUQycXWrK3VSdCaWZeuJm/+AZJ+2Yh fbRpEdonMUD+ls8kolGlf7IF8YTm2dxw+4GfzX/3dPD1NzGY33ODdnFEYSxNLOSGtNAn AeMw== X-Gm-Message-State: AO0yUKXB0P7gBIii82xLX2lG3bNnyp1apYLB0608jg0fkhIR49WOj5sz uNfunkAkY7GaYVp5QV+SFesTxvVdV8qkoSO+Qwg= X-Google-Smtp-Source: AK7set8EXWbpfykLGF6ctYqEuKejbP7+RJXT6uzBIC+3/2Ak8l5LDext1qgmEEE2nmmIV1AioBYfPg== X-Received: by 2002:a05:6808:41:b0:383:f380:868e with SMTP id v1-20020a056808004100b00383f380868emr718164oic.34.1678306792976; Wed, 08 Mar 2023 12:19:52 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Date: Wed, 8 Mar 2023 17:19:15 -0300 Message-Id: <20230308201925.258223-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306948956100003 Content-Type: text/plain; charset="utf-8" We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should always account for them. CPUs such as sifive_e need to disable settings that aren't enabled simply because the parent class happens to be enabling it. Moving all configurations from the parent class to each CPU will centralize the config of each CPU into its own init(), which is clearer than having to account to whatever happens to be set in the parent device. These settings are also being set in register_cpu_props() when no 'misa_ext' is set, so for these CPUs we don't need changes. Named CPUs will receive all cfgs that the parent were setting into their init(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 48 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e2cd55320c..499738d2dd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -325,7 +325,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) =20 static void riscv_any_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) @@ -340,6 +341,12 @@ static void riscv_any_cpu_init(Object *obj) =20 env->priv_ver =3D PRIV_VERSION_LATEST; register_cpu_props(obj); + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 #if defined(TARGET_RISCV64) @@ -358,13 +365,20 @@ static void rv64_base_cpu_init(Object *obj) =20 static void rv64_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_sifive_e_cpu_init(Object *obj) @@ -375,10 +389,14 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv64_thead_c906_cpu_init(Object *obj) @@ -411,6 +429,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv128_base_cpu_init(Object *obj) @@ -447,7 +469,8 @@ static void rv32_base_cpu_init(Object *obj) =20 static void rv32_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env =3D &RISCV_CPU(obj)->env; + RISCVCPU *cpu =3D RISCV_CPU(obj); + CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); =20 register_cpu_props(obj); @@ -455,6 +478,12 @@ static void rv32_sifive_u_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.mmu =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_sifive_e_cpu_init(Object *obj) @@ -465,10 +494,14 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_ibex_cpu_init(Object *obj) @@ -479,11 +512,15 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_11_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif cpu->cfg.epmp =3D true; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } =20 static void rv32_imafcu_nommu_cpu_init(Object *obj) @@ -494,10 +531,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; - cpu->cfg.mmu =3D false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei =3D true; + cpu->cfg.ext_icsr =3D true; + cpu->cfg.pmp =3D true; } #endif =20 @@ -1357,11 +1398,6 @@ static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu =3D RISCV_CPU(obj); =20 - cpu->cfg.ext_ifencei =3D true; - cpu->cfg.ext_icsr =3D true; - cpu->cfg.mmu =3D true; - cpu->cfg.pmp =3D true; - cpu_set_cpustate_pointers(cpu); =20 #ifndef CONFIG_USER_ONLY --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306935; cv=none; d=zohomail.com; s=zohoarc; b=K4CuuZ8Z7+r6EkSwgXZBXfPux4HuS2Lpij95Knlk45S4N9HbWt+9gU0JyIvvvQHKfcw6JQiU7XbFSnKvYysDMury0LsZCs9+GOJWrfk1npYTMRAEvjS/4fBsBAoiCz6sTA2RJD4qtWwk2Puksx6MkcyCtiSQnvCsed3XfTvwMto= ARC-Message-Signature: i=1; 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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7EOXcDW6p8G+IFiiDat3ZFWdJNRQpAX4f1N5sF8hvvc=; b=IuC0kCJ24+ac4L5/SUOeAwRGablw1XckDfK3j2SSr50eY1tQiCpcC+0OeldEL8gY4M RV6XpcMJb0G7b/0WiVNmBvaL6wX0fXRGeuYmgqBYl2cM8L+pUcwHTP1Whc+WwRczp2AT fKvi+3eLNkAJmueCUquIITxgjYwNYt5U2Asv5WFa8kyrTQxrnzBWPtb+dxdsZkD/1Ud2 /+a8A9KjTuS4keBjVF+jBj9B00t2FNEYY23gcQEFhli881GbPOYSSlG12nUTGq1CZU83 mQBamcecXvC1+dxIFoCXEgLhc+mBGwKIWwkOieeU/mncSsqmI7xwARC80nujdzVrgrw9 tOrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7EOXcDW6p8G+IFiiDat3ZFWdJNRQpAX4f1N5sF8hvvc=; b=thOowCa0wy4a8vgbp25mMGoM5U806YEnLaCX1iVvF4lmrsspmg2+qZx+CucErV/KgW aC/+avhHOb/U3bi71NqtxVqRXlOrW7VpNCzBxjaenFjLIin65DkBAKeVp1HLXr5fythp nXeWiAjNYJ5m+X6SwIWCOP60XfD25+HXNObLSLnKsZvBfS32VrnI22A58Uc7fYD81IFH gqxuiZbQeC+O53Wr8P7+fXCGiGRcAgpUHY7cph/fdMptIERW1KD1NMIxu3kMT2UCrZPZ VuIHkQKXNIgsnpun8/jKQH0FyAwkOF97n3NQSQQltKJwkY3Pjk7jxVuIa27g9G9zhvAc egEg== X-Gm-Message-State: AO0yUKVPwVxchEoQJlmM6trFKrqrZa6JHrI1oFu5VuBpzGLOFe6c+1w4 Z8QKD25KxctU58yDZLPtkZwTe7q7XMNREeeB/Ec= X-Google-Smtp-Source: AK7set+D60PNp69ssW60Ouq5ifbn+94wPGlFFmDCE9OmX/l2pXMEKYJXvzHheYedmsaC7iby0RE5AA== X-Received: by 2002:a05:6808:2382:b0:37a:2bf0:501b with SMTP id bp2-20020a056808238200b0037a2bf0501bmr12961775oib.9.1678306795931; Wed, 08 Mar 2023 12:19:55 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Date: Wed, 8 Mar 2023 17:19:16 -0300 Message-Id: <20230308201925.258223-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306936940100003 Content-Type: text/plain; charset="utf-8" set_misa() will be tuned up to do more than it's already doing and it will be redundant to what riscv_cpu_validate_set_extensions() does. Note that we don't ever change env->misa_mlx in this function, so set_misa() can be replaced by just assigning env->misa_ext and env->misa_ext_mask to 'ext'. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 499738d2dd..dc6e444219 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1153,7 +1153,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCP= U *cpu, Error **errp) ext |=3D RVJ; } =20 - set_misa(env, env->misa_mxl, ext); + env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 #ifndef CONFIG_USER_ONLY --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306910; cv=none; d=zohomail.com; s=zohoarc; b=SSC+eYTJ284WXrfMNsAo/msWxQ/v36enNfhBgU05EuE6hN5ysIma9lyfEsU+m71W3xg/DzTZfLswVFgDR4tfJNGuwAwafnWhASXZHT13TWKhjPdiDC7n0qlqgvtYpK+0sMGcutR7umEMPgDwixc/6s6jHpJGX8r9opUEP2h/rEs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306910; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CwNWHsFbNT1Xg+X7KE2JYFVcnaWt4G8P4YU3bP/dFoY=; b=HHvpjdjCo5KPYzfKZIRlNWofOD5jLaZMz2cLmNAGIrtzmnWRl0r5rspCRoQUpzFJ6C5dq0ppUejvqd5i1mRfJN/eANcKKRPx2G2pX1/SyH9qohqZdh72C1PaNXiwYkrb55V0+NF/kE6J9y9Wj46AlPDM1OlIhPZXEXX+Xq2uTVY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306910687849.1656359156909; Wed, 8 Mar 2023 12:21:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0GZ-0008DX-GR; Wed, 08 Mar 2023 15:20:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0GX-0008Ch-Jf for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:01 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0GV-0002TF-Rl for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:01 -0500 Received: by mail-oi1-x236.google.com with SMTP id bh20so13110683oib.9 for ; Wed, 08 Mar 2023 12:19:59 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:19:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CwNWHsFbNT1Xg+X7KE2JYFVcnaWt4G8P4YU3bP/dFoY=; b=mkPkr3W10LDd5TooDjO+kNMCFA+X0kXlB9o5ApCA8G4KOsbZjlbxzPIsnf5s0i4IY8 QNYMuF25AiS02Jn3EOnXYr0R8b4vvlncGNpmxds6YXU3knyaYO/Gak2j+8JyFe0+fY+6 KxLhmAH89WgruaGzUWVJzdx4dkRd8pHW8yyzau5P9w+MWlZ49HS510UOF0T2KI23iVMS UWahU8l4ZtddoJRRlCvtD71b4UVaNPEPhKe8w854f1Ox1FO3GVcfp6eo+vVvuNfUHKAX R0yzx/9bFYo9AkE/rG7dWczLY4cc7LGkdmczlp5DENTc48kW3Pb5II2pGmTxLElPFK2p l7Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306799; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CwNWHsFbNT1Xg+X7KE2JYFVcnaWt4G8P4YU3bP/dFoY=; b=EIgYfqTO1Q8QxMluAqm67Kacc5wUgipGVoRHkoZ1inTu2Z1uB13qf+NbnMNA9UxFe/ TrJQ4r/8BurfGUrW8J1pTMgEKfXg9Rs8kPEbgKnJONu2vE9riFw1qxIE2M2NbNBL73KG pBw43NQsj6PNtJPQPmvZKgACV28h16xtjLFVpEgxkCmX5uvLHB0OH1imWO5Hl4Q4BIpe 9V8Lrpy6cGo00SPYMGg4bOpsBoGV4GrKaxHgRBDsqCODyajUo0WhCiv4JSlfZF2DY9zC 8lyatIk68u+ylkups7VxPdTFoLKpkSBdTgJNf7IUDkEmDVyowFO8KSh16pL2U7wNaGr7 IyjA== X-Gm-Message-State: AO0yUKWj9+sVSfrEsTSmmoX4pM+9827+c1SxWR6Z7guDyYxbpywTvbda WVqklvFxucTxdZTaBgfw6ztQ3dT+AU3z31syH3Q= X-Google-Smtp-Source: AK7set9KFEpNOy83PMXQl03JmaI2NL4gJpfQzZMsHX7ea2n/5piTLgPrGp2dviscQo9KcOnpeQIVAg== X-Received: by 2002:aca:6504:0:b0:37f:ac0a:f4d5 with SMTP id m4-20020aca6504000000b0037fac0af4d5mr9405291oim.3.1678306798765; Wed, 08 Mar 2023 12:19:58 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa() Date: Wed, 8 Mar 2023 17:19:17 -0300 Message-Id: <20230308201925.258223-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306912692100003 Content-Type: text/plain; charset="utf-8" set_misa() is setting all 'misa' related env states and nothing else. But other functions, namely riscv_cpu_validate_set_extensions(), uses the config object to do its job. This creates a need to set the single letter extensions in the cfg object to keep both in sync. At this moment this is being done by register_cpu_props(), forcing every CPU to do a call to this function. Let's beef up set_misa() and make the function do the sync for us. This will relieve named CPUs to having to call register_cpu_props(), which will then be redesigned to a more specialized role next. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++-------- target/riscv/cpu.h | 4 ++-- 2 files changed, 34 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dc6e444219..08bdf861db 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -236,8 +236,40 @@ const char *riscv_cpu_get_trap_name(target_ulong cause= , bool async) =20 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { + RISCVCPU *cpu; + env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; + + /* + * ext =3D 0 will only be a thing during cpu_init() functions + * as a way of setting an extension-agnostic CPU. We do + * not support clearing misa_ext* and the ext_N flags in + * RISCVCPUConfig in regular circunstances. + */ + if (ext =3D=3D 0) { + return; + } + + /* + * We can't use riscv_cpu_cfg() in this case because it is + * a read-only inline and we're going to change the values + * of cpu->cfg. + */ + cpu =3D env_archcpu(env); + + cpu->cfg.ext_i =3D ext & RVI; + cpu->cfg.ext_e =3D ext & RVE; + cpu->cfg.ext_m =3D ext & RVM; + cpu->cfg.ext_a =3D ext & RVA; + cpu->cfg.ext_f =3D ext & RVF; + cpu->cfg.ext_d =3D ext & RVD; + cpu->cfg.ext_v =3D ext & RVV; + cpu->cfg.ext_c =3D ext & RVC; + cpu->cfg.ext_s =3D ext & RVS; + cpu->cfg.ext_u =3D ext & RVU; + cpu->cfg.ext_h =3D ext & RVH; + cpu->cfg.ext_j =3D ext & RVJ; } =20 #ifndef CONFIG_USER_ONLY @@ -340,7 +372,6 @@ static void riscv_any_cpu_init(Object *obj) #endif =20 env->priv_ver =3D PRIV_VERSION_LATEST; - register_cpu_props(obj); =20 /* inherited from parent obj via riscv_cpu_init() */ cpu->cfg.ext_ifencei =3D true; @@ -368,7 +399,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -387,7 +417,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -472,8 +501,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); CPURISCVState *env =3D &cpu->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - - register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -492,7 +519,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -510,7 +536,6 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_11_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -529,7 +554,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu =3D RISCV_CPU(obj); =20 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(obj); env->priv_ver =3D PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index af2e4b7695..f8baedd9c7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,8 +66,8 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* - * Consider updating register_cpu_props() when adding - * new MISA bits here. + * Consider updating set_misa() when adding new + * MISA bits here. */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.19.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6JSPHWrMYs6J2tCCNojYxAAj60kq9bvBLnyhd2Lgi6c=; b=hq7rUsM03sf6PV8R0bxHV4XJjPmggZ6B0eFQ7q8CexiGon6sftseKRzz0l5tBucYYm 9yCPmD+JHJ1CSy7BaDHgc6JssfK6wXP7V5G9BvWntvLe8j2jlPdoutAlkLv7xMrnuAPk fK/JXxNdroLa7qPXC+EnLzbOXeKcsrmxjLhONBkp8JppfWL6HaQEUd+h6eujhdkXJY1D Jkjr3DBjHgvrGHXe27pH8ljg5aoejZDi0ASLON40bLVfFIh1ULzQIzdMVCG/ZbJFS8lx mbDie+UoyczMEo+JGGbRMPnbtP+YaU3zCrvr933OS2JTOCqCt3ndvRawD2xjNzyViyIJ Kxfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6JSPHWrMYs6J2tCCNojYxAAj60kq9bvBLnyhd2Lgi6c=; b=cwAcdj+IY5onejuNzQH9tqGQl+dlWMDGzn3ahLj5nhSQFKs6hBE2ZJuU1b/s9KEiwK ir5X44llisbPg2uLLIVMDJlzzoXpheQKA1e6xsZcsiEyTA5OaNs5Qb53eXekwpNFKRvH +AFYnUbkCCzVgCY7HUPc+Gxj4JdeXcyTQMZniye/Kj5dSNDlCMEpDvPmWgOqp9uHp5J1 BA1cO6HHy/G5lMDYwT8YCQvCEt7QdtDc1C9LZ86e0Fnn8nMAg9jQOJWJ6l8sAy/CVMi8 q13zln4kMh9ofP9nIIRBrOcbOPjQZQdKETtT6fc3abTDREkIgHuIwZYTZu7U6Og3zaUK jv5w== X-Gm-Message-State: AO0yUKXK3Pz8fCD1oeshwxMk3cguH5vmmtPxwJM5qXblKug+1e64QOs5 dKqpJiJQFnHItw7XkZVqVLnMZKDxoDZDTUkIbhQ= X-Google-Smtp-Source: AK7set+XwHelUmWTtOzWxRRjXDHkr2vJXwDp4mhUu1bIsXaa27wciFVcCLdqYJkAyNqVS0r1J3qvMw== X-Received: by 2002:a54:450d:0:b0:384:1a4b:c609 with SMTP id l13-20020a54450d000000b003841a4bc609mr7853946oil.57.1678306801689; Wed, 08 Mar 2023 12:20:01 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props() Date: Wed, 8 Mar 2023 17:19:18 -0300 Message-Id: <20230308201925.258223-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306894600100002 Content-Type: text/plain; charset="utf-8" Now that the function is a no-op if 'env.misa_ext !=3D 0', and no one that are setting misa_ext !=3D 0 is calling it because set_misa() is setting the cpu cfg accordingly, remove the now deprecated code and rename the function to register_generic_cpu_props(). This function is now doing exactly what the name says: it is creating user-facing properties to allow changes in the CPU cfg via the QEMU command line, setting default values if no user input is provided. Note that there's the possibility of a CPU to set a certain misa value and, at the same, also want user-facing flags and defaults from this function. This is not the case since commit 26b2bc58599c ("target/riscv: Don't expose the CPU properties on names CPUs"), but given that this is also a possibility, clarify in the function that using this function will overwrite existing values in cpu->cfg. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 48 ++++++++++------------------------------------ 1 file changed, 10 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 08bdf861db..4988fd4d4b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -221,7 +221,7 @@ static const char * const riscv_intr_names[] =3D { "reserved" }; =20 -static void register_cpu_props(Object *obj); +static void register_generic_cpu_props(Object *obj); =20 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -386,7 +386,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(obj); + register_generic_cpu_props(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -475,7 +475,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(obj); + register_generic_cpu_props(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -488,7 +488,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(obj); + register_generic_cpu_props(obj); /* Set latest version of privileged specification */ env->priv_ver =3D PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -575,7 +575,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(obj); + register_generic_cpu_props(obj); } #endif =20 @@ -1529,44 +1529,16 @@ static Property riscv_cpu_extensions[] =3D { }; =20 /* - * Register CPU props based on env.misa_ext. If a non-zero - * value was set, register only the required cpu->cfg.ext_* - * properties and leave. env.misa_ext =3D 0 means that we want - * all the default properties to be registered. + * Register generic CPU props with user-facing flags declared + * in riscv_cpu_extensions[]. + * + * Note that this will overwrite existing values in cpu->cfg. */ -static void register_cpu_props(Object *obj) +static void register_generic_cpu_props(Object *obj) { - RISCVCPU *cpu =3D RISCV_CPU(obj); - uint32_t misa_ext =3D cpu->env.misa_ext; Property *prop; DeviceState *dev =3D DEVICE(obj); =20 - /* - * If misa_ext is not zero, set cfg properties now to - * allow them to be read during riscv_cpu_realize() - * later on. - */ - if (cpu->env.misa_ext !=3D 0) { - cpu->cfg.ext_i =3D misa_ext & RVI; - cpu->cfg.ext_e =3D misa_ext & RVE; - cpu->cfg.ext_m =3D misa_ext & RVM; - cpu->cfg.ext_a =3D misa_ext & RVA; - cpu->cfg.ext_f =3D misa_ext & RVF; - cpu->cfg.ext_d =3D misa_ext & RVD; - cpu->cfg.ext_v =3D misa_ext & RVV; - cpu->cfg.ext_c =3D misa_ext & RVC; - cpu->cfg.ext_s =3D misa_ext & RVS; - cpu->cfg.ext_u =3D misa_ext & RVU; - cpu->cfg.ext_h =3D misa_ext & RVH; - cpu->cfg.ext_j =3D misa_ext & RVJ; - - /* - * We don't want to set the default riscv_cpu_extensions - * in this case. - */ - return; - } - for (prop =3D riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306885; cv=none; d=zohomail.com; s=zohoarc; b=UuUx/bahvYQE35fZLjQkWipn5i4rxo8Szng3KUJEqOkeGARuOTOiPxMZu5jexQWZEvsjMeiE35hx70Agarb5s7+yF9Sq2+m1R+aaWCUc9WNG+WMbHHTeWEVcBb5yhM7Av38syen6k9NoS9rTqEBO+WCl4T063YCkT9obgdrSSf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306885; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ujomQRHGgwjDrFsnpBRurC6xFEUn7Ynnev0wZ4SoaIY=; b=lxMTpoWYq9WkmG3naCSZ6tufE9y6GGWx5E9d0yC+nS0+xN8QRImf0cqYbmuBx/vMcDZxv8UftESqLnfWjDoft9enBJkd9TlUzXLFcMmGpUJfCuXrHv3ScnTWFwzwymcwB9UPdO8PUHH4pbDYMjTyaYVL3xIJ9EDCEZK6dNUp94M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306885237736.4350741437033; Wed, 8 Mar 2023 12:21:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0Gg-0008GS-3R; Wed, 08 Mar 2023 15:20:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0Ge-0008Fe-7B for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:08 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0Gb-0002Vs-Ke for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:07 -0500 Received: by mail-oi1-x236.google.com with SMTP id q15so13097850oiw.11 for ; Wed, 08 Mar 2023 12:20:05 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ujomQRHGgwjDrFsnpBRurC6xFEUn7Ynnev0wZ4SoaIY=; b=MDUI6Bicf4vbL3rz/6F0vbCO0Dprf7NSlXklIo6ewHOmHgHdo1hHGiexXqw7HQEilG Sh6Cy+XpWyVvD3PQwME0ChOvqaSBRKN9fek0lUxJ10azp5m1Czmy8lIr70pdfQ73ds9U ++mHAxG42eY2M/YB/48QREhstARQPFLvRRDa2Wr4hZo2W8HA7B+jeGZf8bjCym6Cgyky mAODhXEDhm5F0+1EQmLWa9SUjGYmP9Gvi6sXv+pSSRU7F6+d/ktz00Vx+OTWZomSLdAT nFQGDU1HCvPpU2wjkn7ilTy8DSSNefVRkF86VgROW6o4BVJ0857TEUiOgcOjoGdDVCaT c7Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306804; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ujomQRHGgwjDrFsnpBRurC6xFEUn7Ynnev0wZ4SoaIY=; b=i533Hr+N11gz2OqHr/IvZ31BA3Z4M2aaevrknUSjrws96fts6z7lgbMo9ko2q5kOIq h3zefpWUtpRgZwEwRNyZwGE3QkFqC177K9NtdXS3kKZ46zNrvk8r+s+k8B1k0yK2hizg Ckv3IsglZmRDYsf/DKvjd2zEAxD/TBUNNK1rWXJ5MQbHB6x+lEo/8ULNVFSXTvetJpz+ mBx65hQxvuJjxXHGvDr9+tmCI+ngd8pJsouLMzXUvjTPSIrSr4Jv4wKd5fS0Cuw8LIFa YubiAtK3YEpWtLtP2x/W4I5o/EDrGK+hFLDPlE7o8atP5Ahj9uf65+vkY+bL37cz/3w6 pZbQ== X-Gm-Message-State: AO0yUKUkMRTxxn9NkeQaLOdP1IC4uHVcReyOWJdb9fe/otDZ4imA+499 JruzLMWB3QI+bCo1/g6TQGU8AdAvzM0Xgp1/rKs= X-Google-Smtp-Source: AK7set9WVRRqcOUAcUScOCqvLmZ3/r9vw5ZI50hGM0lMOk88Thd53TBwu+rra8gK5FjcMmwugB72Pw== X-Received: by 2002:aca:281a:0:b0:37f:8ad8:48b4 with SMTP id 26-20020aca281a000000b0037f8ad848b4mr8134847oix.17.1678306804597; Wed, 08 Mar 2023 12:20:04 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 11/17] target/riscv/cpu.c: move riscv_cpu_validate_v() up Date: Wed, 8 Mar 2023 17:19:19 -0300 Message-Id: <20230308201925.258223-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306886672100006 Content-Type: text/plain; charset="utf-8" riscv_cpu_validate_set_extensions() will play a future role in write_misa(). First we need to ensure that this function is validating first and setting cfg values later. At this moment this is not the case of the RVV validation. Move RVV validation up. Leave the 'ext |=3D RVV' where it is - next patch has plans for it. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4988fd4d4b..48838471b8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1111,6 +1111,14 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) } } =20 + if (cpu->cfg.ext_v) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; @@ -1165,12 +1173,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) ext |=3D RVH; } if (cpu->cfg.ext_v) { - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - ext |=3D RVV; } if (cpu->cfg.ext_j) { --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306884; cv=none; d=zohomail.com; s=zohoarc; b=DVRem9WdEcrGZKPbet+S7hRdG4MN9d5gownkKH74+fd3LaLsZZZitqQ5kP6NjM1CsdVBVYF14AayvvUe7JuRlKp4+3arnpM+h2iizohl2mPCFM4T58xYAkEfj9XygGkIkMNJpAHI274XRRu82LDh9S+J+6L+hNnaPwowFPnSTpk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306884; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0QTR0ZBEeetCDibdFu13o9OoCHPUbiVB3yz0NXvEhrk=; b=F/RHva/tKBO4u/KNvXJGmNeAkbeaOxQvlWvE/wzxOXzZsatDFqGTWT5eWitNYiYpf6FE6PfCzry+aBqBo619pmbgXUrp/J4jeghf8QSDjkJDgaQN2236t5hFq/qdGXgGiEvfN6lRcOGd+hVAxEqggDPrQ4GIzIoakHVHBpWS9Dk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306884480239.5830454104298; Wed, 8 Mar 2023 12:21:24 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0Gh-0008Gm-Vj; Wed, 08 Mar 2023 15:20:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0Gg-0008GV-Jd for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:10 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0Ge-0002Sm-NJ for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:10 -0500 Received: by mail-oi1-x236.google.com with SMTP id c11so16484oiw.2 for ; Wed, 08 Mar 2023 12:20:08 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0QTR0ZBEeetCDibdFu13o9OoCHPUbiVB3yz0NXvEhrk=; b=lR03a5vcekKH4a1JRJu3JnQCVU7mb90S/YtjgWZMCIh9UqtB8Aa3rAIxtX1bsGZBpn W64kqGD2Av43ohh16zCisgG2Xgj5NzB6IKrBvzbt/f8eHXxqv0lta5cP+OfRDyM2QVcu iomRZE2Nb21i7Fpl8CzV87B72+iHxlBbH//unROjOI6mBQVChISjtljLZOBWh7Z0k2q1 0azUwChszUWgEZ96x+eUjGLtedcEJKfNCCVI8ZljJF4b2yPBCawB8tuTJw3TJ72m/QDP 2BC5x17ZPYhlKQviofkWJy3v679p1voJRdGUgLDirHWDa3rAvt0wWWn88QIFxSTaWLzk rmJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0QTR0ZBEeetCDibdFu13o9OoCHPUbiVB3yz0NXvEhrk=; b=Dm9297o67/zmj+vx6j5DuQX2mIrYpO1k69ZwApLq3Z1+5azqxcVBhEl6bpcPHAVw96 FgKrAOZBAE4LB4Qhzo6MEkw54ZwsZ2V2tPi26kb5wNRhXUCDc9fX98zYPA2S7b6gUXJW btuqlYFUfnG6TxHLecSUktV40ZVpCN2cEfoXGEr6eLAmaRJeem9m4UooLnGApWOa32jp csxxkaxXhJmg0WocR/P27KNJqvKSPgpmEfw8xF0LwWVkMVmPnYUdw+htJSB29/soXw7V 3bucioDTD/sCt51OwobYR6OoKGR+CDj23AuG6al0ESv/bo2KgwnxDrVNyZLkZqsPqdpa hPxg== X-Gm-Message-State: AO0yUKXfUnr86T5CNmtEt73DA8NZGAytZjnBojez0f8ItkX9cWft7yS5 3BDgoZ4wwoZtjXwnwRS1x/E9RC8XYMjWBOq8WDw= X-Google-Smtp-Source: AK7set8e354WLnBXR+pzo3vswXBnqChg7S0unEQ3dw7sTm8weBO0TiezbKPAFML5fUsRqnAO7GGcxw== X-Received: by 2002:a05:6808:7c3:b0:367:7633:30dc with SMTP id f3-20020a05680807c300b00367763330dcmr7772087oij.40.1678306807684; Wed, 08 Mar 2023 12:20:07 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 12/17] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers Date: Wed, 8 Mar 2023 17:19:20 -0300 Message-Id: <20230308201925.258223-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306886668100005 Content-Type: text/plain; charset="utf-8" The extremely tedious code that sets cpu->cfg based on misa_ext, and vice-versa, is scattered around riscv_cpu_validate_set_extensions() and set_misa(). Introduce helpers to do this work, cleaning up the logic of both functions a bit. While we're at it, add a note in cpu.h informing that any future change in MISA RV* bits should also be reflected in the helpers as well. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 120 ++++++++++++++++++++++++--------------------- target/riscv/cpu.h | 3 +- 2 files changed, 65 insertions(+), 58 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 48838471b8..a564de01df 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -234,10 +234,69 @@ const char *riscv_cpu_get_trap_name(target_ulong caus= e, bool async) } } =20 -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) { - RISCVCPU *cpu; + uint32_t ext =3D 0; =20 + if (cfg->ext_i) { + ext |=3D RVI; + } + if (cfg->ext_e) { + ext |=3D RVE; + } + if (cfg->ext_m) { + ext |=3D RVM; + } + if (cfg->ext_a) { + ext |=3D RVA; + } + if (cfg->ext_f) { + ext |=3D RVF; + } + if (cfg->ext_d) { + ext |=3D RVD; + } + if (cfg->ext_c) { + ext |=3D RVC; + } + if (cfg->ext_s) { + ext |=3D RVS; + } + if (cfg->ext_u) { + ext |=3D RVU; + } + if (cfg->ext_h) { + ext |=3D RVH; + } + if (cfg->ext_v) { + ext |=3D RVV; + } + if (cfg->ext_j) { + ext |=3D RVJ; + } + + return ext; +} + +static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, + uint32_t misa_ext) +{ + cfg->ext_i =3D misa_ext & RVI; + cfg->ext_e =3D misa_ext & RVE; + cfg->ext_m =3D misa_ext & RVM; + cfg->ext_a =3D misa_ext & RVA; + cfg->ext_f =3D misa_ext & RVF; + cfg->ext_d =3D misa_ext & RVD; + cfg->ext_v =3D misa_ext & RVV; + cfg->ext_c =3D misa_ext & RVC; + cfg->ext_s =3D misa_ext & RVS; + cfg->ext_u =3D misa_ext & RVU; + cfg->ext_h =3D misa_ext & RVH; + cfg->ext_j =3D misa_ext & RVJ; +} + +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +{ env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; =20 @@ -251,25 +310,7 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,= uint32_t ext) return; } =20 - /* - * We can't use riscv_cpu_cfg() in this case because it is - * a read-only inline and we're going to change the values - * of cpu->cfg. - */ - cpu =3D env_archcpu(env); - - cpu->cfg.ext_i =3D ext & RVI; - cpu->cfg.ext_e =3D ext & RVE; - cpu->cfg.ext_m =3D ext & RVM; - cpu->cfg.ext_a =3D ext & RVA; - cpu->cfg.ext_f =3D ext & RVF; - cpu->cfg.ext_d =3D ext & RVD; - cpu->cfg.ext_v =3D ext & RVV; - cpu->cfg.ext_c =3D ext & RVC; - cpu->cfg.ext_s =3D ext & RVS; - cpu->cfg.ext_u =3D ext & RVU; - cpu->cfg.ext_h =3D ext & RVH; - cpu->cfg.ext_j =3D ext & RVJ; + riscv_set_cpucfg_with_misa(&env_archcpu(env)->cfg, ext); } =20 #ifndef CONFIG_USER_ONLY @@ -1142,42 +1183,7 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } - if (cpu->cfg.ext_v) { - ext |=3D RVV; - } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } + ext =3D riscv_get_misa_ext_with_cpucfg(&cpu->cfg); =20 env->misa_ext_mask =3D env->misa_ext =3D ext; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f8baedd9c7..529d8044c4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,7 +66,8 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* - * Consider updating set_misa() when adding new + * Consider updating riscv_get_misa_ext_with_cpucfg() + * and riscv_set_cpucfg_with_misa() when adding new * MISA bits here. */ #define RVI RV('I') --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306943; cv=none; d=zohomail.com; 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([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sor+s3eQ6YdS90sfFqFUjUzQyje0tn81LV5CVbc+K3E=; b=fX5Hr9vurwT2ZCmmGnN7vixTIDanVoOIX7Jxodgh1UZ92VEifuTwQ8MXU1IEgCoRnu FIj2TNRR3wTS/0yF7W2K9G3w1vDjF3tlBPHGJ9cs13Rf1Jj+paBbta7CuUK94XvyG9sn 9meMgGVGICHy780E4793sR6PBKK1Tfp2maAZzliOd7xWH5scBb4+4vGCiK4NdJ8CU8kn FC/VWcZiAxnVTvB4ROSoKTr1YXqGxOrf96ElenjMmB+SqFpgacL90LzSkl7U3KoWH0dR aAz6Z2CBQ1axjY7i6Xg0Bi7Ci5cBt8sVaFmLnNdmf19I/IZkrPurACB1cJdtPgTqa7tp a0EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306810; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sor+s3eQ6YdS90sfFqFUjUzQyje0tn81LV5CVbc+K3E=; b=41Zf9vmTkcngG4Diqusr5381pXCTnjcBC3YBSrcoRy6k4wbRY4HLrktjeDoki/o/Xo QTnJ4bFO767ijOLKI34OrsdKD7hVvAe91ZQWgNqPtCDJWHabPsavl3TZhsPBs7PPGox8 dKzR723nD+QqRh4NgcXL9+LYjfSAGLVGED9XXuLYu8Jk3vP4/PAAKDMQESKtlQI9+b6o RxnOvbTZ3B6TjU4sTtXNTTHymuYpR1qeZMTUow2pzIfp/a8FzADkRrOYMcqZ6RctlLST tQFWLlt3nYS4nwtrzIMfPUn2TyNopPifGAf/1vaUadbdK1hEKTSBLpE0YHJVhv7x0EDF dSMw== X-Gm-Message-State: AO0yUKXtDj38T1tICK4we+Zi2rH1fJJBqts6JTnZX/0Ugxo6Pcaz4bHL a2J2H5tFpOqkrm1wxwY7ZPmrlHUcNCm8KHArWvY= X-Google-Smtp-Source: AK7set+Qu3T22mIft7fKLxZuMUJTOX0fcIb8aL9FR6OLtxWVoBOE1+NeSbQRfIbuBQQNEJM0PBKNZg== X-Received: by 2002:a05:6808:234b:b0:37b:1bf9:9cd6 with SMTP id ef11-20020a056808234b00b0037b1bf99cd6mr7748566oib.5.1678306810665; Wed, 08 Mar 2023 12:20:10 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 13/17] target/riscv/cpu.c: split riscv_cpu_validate_priv_spec() Date: Wed, 8 Mar 2023 17:19:21 -0300 Message-Id: <20230308201925.258223-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306944930100003 Content-Type: text/plain; charset="utf-8" This function will validate and change/disable extensions that aren't compatible with a certain spec version. Since the function is called at the start of riscv_cpu_validate_set_extensions(), we're disabling extensions without guaranteeing that they aren't being turned on again after the validation step. Create a new riscv_cpu_disable_priv_spec_isa_exts() helper and call it at the end of riscv_cpu_validate_set_extensions(), right before re-calculating the misa_ext value with the current config. This will ensure that we're not re-enabling extensions that should be disabled by the spec rula by accident. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a564de01df..49f0fd2c11 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -942,7 +942,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RI= SCVCPUConfig *cfg, static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) { CPURISCVState *env =3D &cpu->env; - int i, priv_version =3D -1; + int priv_version =3D -1; =20 if (cpu->cfg.priv_spec) { if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { @@ -962,6 +962,12 @@ static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu= , Error **errp) if (priv_version >=3D PRIV_VERSION_1_10_0) { env->priv_ver =3D priv_version; } +} + +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + int i; =20 /* Force disable extensions if priv spec version does not match */ for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { @@ -1183,6 +1189,12 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) cpu->cfg.ext_zksh =3D true; } =20 + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); + ext =3D riscv_get_misa_ext_with_cpucfg(&cpu->cfg); =20 env->misa_ext_mask =3D env->misa_ext =3D ext; --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306897; cv=none; d=zohomail.com; s=zohoarc; b=k03B/NQDYMWiXj6BcdLNKDelFMfAX+9CdzgBJkW2HCL0cJqjmpIFpF8gZxf84A+j3Bcwd8+ioKwvigDeR3MR0c5dm5ctzo9cLUlLSeK7ACENXYfP0mUUPQd8fBgBJR0ZwbbvFfkDfADPG0SiYCzEcHqPZarx+ipMX8ve9NyYCW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306897; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DjW2PxIff7WUC8TEvCQOmsPa06E64WLCwTpLzA9jEVc=; b=KnZpHmin9maQMO6IlwJTyEHhSo7jLHowjCGMPdSjCt48188btVXUPbhl089KqoQDmfD6L6iQn41MsqpjZbTq7I/IMi2VpQNvmT/hGZvC9CGXFxUKiZ1Y8BOxMENvdJqOaVUbSncUR8qIUg3ez4b+HGdp/RE16fxEZsLpxOPU3BU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306896787227.8743140807411; Wed, 8 Mar 2023 12:21:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0Gn-0008JM-Og; Wed, 08 Mar 2023 15:20:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0Gm-0008IM-5t for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:16 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0Gk-0002SA-Oj for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:15 -0500 Received: by mail-oi1-x22f.google.com with SMTP id bk32so13100536oib.10 for ; Wed, 08 Mar 2023 12:20:14 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306813; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DjW2PxIff7WUC8TEvCQOmsPa06E64WLCwTpLzA9jEVc=; b=iSRLjPSvBltwfW8ERamN+xLffumBPsIW5XKxwlt/cQPIugDdfgNunqPDAYwC/jmPpM QgcX4fvZUS1QZLhNLCiNJooa7YZbMLHcGjxXdbLCU6GW1/M/3MVF52D99KQdpM0ClaGv NcEoPEBRIwv6/2vLsgMZyBsuLTqsVSd6aqncVodeA3tC25rHDsXVlt76b3SVfa843uP6 MTkzygazlGlg2cpMGnGnt2RRp+C3bv1f4JxoIediyase/9ruR1+UvCo2DXR/4bd8ZOQ/ tjKvPmHr2gP2LLRsei3dPGOrdguIh/OoAAD37pHT+Cjli1Ikc8u0UjtIhW9u4+X16jbH +wiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306813; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DjW2PxIff7WUC8TEvCQOmsPa06E64WLCwTpLzA9jEVc=; b=E2/pUP5LqD883qmd1RvFHnrjggZGeSRIHjShc9LX+tnk7Mz3RYtNqIEmwZgJVps0SR 2epuYK5uBuTP012xYoGbmmOAuFxFDQXrXd8nz5ybwf27BHiU7p5FZnhYswFVJN4vHK7H +Kpe6hHO2JaJSl48hUExcrl3QqCJHbRGjJBfRM4u03GylRxojezUSCDBbZq73mGmO9h2 yJ6HxM+uQSRhclvXeSAAKIfjrPErwHco7WyL1WfEtOsxlQ/HtaEHLPwONhewGvNgrusF S7s2Ijp0JjycN1H85mL3XutqK99rNL7pPU/vJUF4s8KQEQnUfS8ipsj2jr3naphNkU3W DBww== X-Gm-Message-State: AO0yUKVlXHQFdv/JNnALzKocgCMjLocDZiRTUOwEcc71cTmvNnGG9r4F MIsfkNjqRDlBYznws7kUvH9PpjRe7mQRnkspZXk= X-Google-Smtp-Source: AK7set/07PVVxP5LDvmFSZtH5XQ6CMkz6B72/jKe/BSM1jwUIgLvsoKm8UNAxsreKCruRkyK9DykNw== X-Received: by 2002:a05:6808:8ef:b0:383:bdef:6589 with SMTP id d15-20020a05680808ef00b00383bdef6589mr8332866oic.56.1678306813713; Wed, 08 Mar 2023 12:20:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 14/17] target/riscv/cpu.c: do not allow RVE to be set Date: Wed, 8 Mar 2023 17:19:22 -0300 Message-Id: <20230308201925.258223-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306898614100011 Content-Type: text/plain; charset="utf-8" This restriction is found at the current implementation of write_misa() in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while also removing the checks we're doing considering that I or E can be enabled. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 49f0fd2c11..7a5d202069 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1045,15 +1045,15 @@ static void riscv_cpu_validate_set_extensions(RISCV= CPU *cpu, Error **errp) cpu->cfg.ext_ifencei =3D true; } =20 - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); + /* We do not have RV32E support */ + if (cpu->cfg.ext_e) { + error_setg(errp, "E extension (RV32E) is not supported"); return; } =20 - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); + /* When RV32E is supported we'll need to check for either I or E */ + if (!cpu->cfg.ext_i) { + error_setg(errp, "I extension must be set"); return; } =20 --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306889; cv=none; d=zohomail.com; s=zohoarc; b=nX9nab6TRzLSN+kGCb/M+Ja7MZoE5GkxryG11naEQsIY4WUxwgx5GIyQZ9wlsDOdaRip+7eFlankpMZcnw5353byOZwhq6WEltF7/nW6FGhH2iZRfiV7GPnX0zO2bKnP5ARDmnspJgP/ezaTaHJxLvenczHo9rmmw3RT6yd/LN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306889; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=m9NpxPjPbNb76kgwRaJeOFlL5VRSfrwmp90n6ZNiOSA=; b=BRSXf3s4uo0ogSHebRCsE0n4C91tQgA9ujjKiP0yuIFOk26MdDCfx7kVcVRG5AvSHWryE+QuY+frhbCPEmOEUY3CqwhKiCgeLPKdW2MVpW7ZvY4EzTadF6Dpz63o9aIaxVqnk6wt0k6XZlmswlRvOvd/BFKrIpYtF+bZSd22U+M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306889814954.3065291718447; Wed, 8 Mar 2023 12:21:29 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0Gq-0008KC-DT; Wed, 08 Mar 2023 15:20:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0Gp-0008Jk-IP for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:19 -0500 Received: from mail-oi1-x234.google.com ([2607:f8b0:4864:20::234]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0Go-0002mX-3e for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:19 -0500 Received: by mail-oi1-x234.google.com with SMTP id t22so13093018oiw.12 for ; Wed, 08 Mar 2023 12:20:17 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m9NpxPjPbNb76kgwRaJeOFlL5VRSfrwmp90n6ZNiOSA=; b=Fyt3VNrDCRGQMaTk5kOXrQBhZwVNq9DSjEzFW6hayibg0nWrQTZLC0faQKW/U7nirt D37lz/qnZwf4rA9tA7Ha/zp3MSVHYiLg4FCMe8jpR6bRCaKbZSMp7frYY0yLsoO90Pe5 H0l6RZOQsu/S/qZrVYqYBoQWNEG74OjvgyAXsi91uU8aFfJERezCiM+D6DvwkQOiBviO 2g+IMwbys6xUcyfqkfOnX3PJFu8OPUeLapAnxiu4AJDpKZz3C+pQ8lPXsJ3SFXfXakXR fWHLj/Rt75ax5dl37nmWOTH2iox8A3TJQg45+8ECjZzWf1STMJDTpXcdolUmGyk/TJ75 FV+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m9NpxPjPbNb76kgwRaJeOFlL5VRSfrwmp90n6ZNiOSA=; b=4xq2DxBGMO44uFnz/1qJn49CWIHHh4qQL/CMcEPOS2duWToiJdoc0duuqLPlVb7nV5 LPcWg9SOw4SEgTUgKQ/P9kOJmBckzv/NE2Ja98SHL7OBiyCpox8pKtkpuGvYFJwTKq83 drFRAFOGljdEiossbcTmR6XybX53o51vfIsANhgm+704LuxRWa0To77kp5+F6kV66bE7 bDe7V8F9L0CGtRoX5vDnWtP52FpGxXWC0gHVXLmVkfqhRYnt1IQUIsuf9vVSWkLPjnWb yEFyDNtTROcxQ1rChuSQxhYeN5khhJ1j/PIOqFY5rYl80VzSY4GyMN3H9SPw+/ap94C+ e6kg== X-Gm-Message-State: AO0yUKXgmZAz1z8KSMyj7n6M2Ea0IiVIGxLWd9XoJNoE4kyIOSIucxaF EZZks8U9CbzVmdASRr5TrzqlQ4ciP9MFY3I7DqU= X-Google-Smtp-Source: AK7set8dsKKu4T1E3obYPuwGiBgqIccB3QBl3fMdc7Gf4lV2atqIjbFaX+QCcJmW6Mddko54N2+Dbg== X-Received: by 2002:a05:6808:601:b0:37f:879d:f548 with SMTP id y1-20020a056808060100b0037f879df548mr8716974oih.14.1678306816660; Wed, 08 Mar 2023 12:20:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 15/17] target/riscv: add RVG Date: Wed, 8 Mar 2023 17:19:23 -0300 Message-Id: <20230308201925.258223-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::234; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x234.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306890680100001 Content-Type: text/plain; charset="utf-8" The 'G' bit in misa_ext is a virtual extension that enables a set of extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid setting it for write_misa(). Add it so we can gate write_misa() properly against it. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7a5d202069..7be6a86305 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,6 +274,9 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPU= Config *cfg) if (cfg->ext_j) { ext |=3D RVJ; } + if (cfg->ext_g) { + ext |=3D RVG; + } =20 return ext; } @@ -293,6 +296,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *= cfg, cfg->ext_u =3D misa_ext & RVU; cfg->ext_h =3D misa_ext & RVH; cfg->ext_j =3D misa_ext & RVJ; + cfg->ext_g =3D misa_ext & RVG; } =20 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 529d8044c4..013a1389d6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,6 +82,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') =20 =20 /* Privileged specification version */ --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306957; cv=none; d=zohomail.com; s=zohoarc; b=Kdh5kx3LMSrUMnD9Qeg1kjyt/aC2I7aV6vCnPFoGwR8ULH7HEPVLdfZluqvYwgdds69VOruqk8aQb4nJwom64KvpdoOZ7x+vq4e2UABmtoulcxWEuQv9ZL9JmT4BRfT5b7oCj/bJ5XxcdwjKcp4TCW16TKnGMK8cz2K6hvNTwmk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306957; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4/czgBHOiXNcAsTwIQvAKApd52rIzMfuuIKayIqgatA=; b=D0rIvyoBe3OjeeGmwmSa+bcJFGmYpO3treZwmHwP1T13uuxBRXAfrXFfZ/Dh4NwMiax2mA6mxN7IpIK1mpWKDWDwngg4U/6jX/i4zyVoycGVCSa0qDI+MZGupq8mgCRf6N8DXNX82meAYzBcv3Rz0h3ws0SDuTLvxzRHQrz5ZAc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306957707832.2723531256969; Wed, 8 Mar 2023 12:22:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0Gs-0008L6-TI; Wed, 08 Mar 2023 15:20:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0Gs-0008Kp-7T for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:22 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0Gq-0002TN-PS for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:22 -0500 Received: by mail-oi1-x22f.google.com with SMTP id s41so13091118oiw.13 for ; Wed, 08 Mar 2023 12:20:20 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4/czgBHOiXNcAsTwIQvAKApd52rIzMfuuIKayIqgatA=; b=GhlrTJYZdDM9eFNmVMH+FfO2cnavbf8JpfO7Sp3sn2TSvBC7PHLAkI+czJcJaugILQ o+ImB/GH+/PL3nvkWJ6GXoBrPKCo9RlyIxbUPtf2LT8eFahkfil6ofPM6mA1D34W5tom MCAO+uciq/0s7sRLXATdlyh4Q8fociWl4w5Z3nP3Uu6pDdM3NugwUfx34yh8cbRlHQ0u dIn/K9AjFbY2vVmfUhUVvzfSqWy81OnEgIdlIALqBdPQZgsDtpQrY18sB3oejztfmYyN jEt4tleYcxWIqd4GbfuonGu3z9YlrnaYFWvPhARn0chx9bbkBhzrX2nM0szVxdLo91Pm wjqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4/czgBHOiXNcAsTwIQvAKApd52rIzMfuuIKayIqgatA=; b=lwkc7bDzIOl5/xwf8QnRPiadgsYxhgXdmkE+MbDi4aHOorp6oj6Uvx1la7Iab2T0SS GuZvYCtEed99USgaucHHMHYs7l70JHlzykKesFNA0A9n3qG0lHsAhRFv+Cf9NPHMFxWM G+NgGWBFXbuUnEGGC21vTL/h5zOilcPzqjKYyWkaufwd9hPG0HC5kMdPxuvMmoXOFNO+ WdmpQS5X7kxVTbFXlgj/ocLKxSUSGTFaHcMo/4e/n8c+S7LbWf50Snm17XJtZrZ0c2/z PSnM3UU8FrQ81g+9uELrT/uyRn3svNs/39Tzrq+f5/CNjlvbiZ4YkE+UAFlV14wNViYQ xdHw== X-Gm-Message-State: AO0yUKXN9WHiKAQYSa5js4l5+JuRItAtWdqHruNDZHXdR/d15xtFZpUR W6nIaiF2CGQu4tPJ43tAyZHgt8OiM0OJ2lPaibc= X-Google-Smtp-Source: AK7set8q5hMtmbh/FlOOIxOlX79ppnjxa/9GV8cq2+GRqcErjRWgFWpeAiFOdTy5xyhUBkYmUHOjoQ== X-Received: by 2002:a54:4188:0:b0:364:9c99:f6cc with SMTP id 8-20020a544188000000b003649c99f6ccmr8220726oiy.22.1678306819784; Wed, 08 Mar 2023 12:20:19 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 16/17] target/riscv: do not allow RVG in write_misa() Date: Wed, 8 Mar 2023 17:19:24 -0300 Message-Id: <20230308201925.258223-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306958991100003 Content-Type: text/plain; charset="utf-8" We're getting ready to use riscv_cpu_validate_set_extensions() to unify the handling of write_misa() with the rest of the code base. But first we need to deal with RVG. The 'G' virtual extension enables a set of extensions in the CPU. At this moment, this is done at the start of our validation step in riscv_cpu_validate_set_extensions(). This means that enabling G will enable other extensions in the CPU before resuming the validation. This also means that, in case a write_misa() validation fails, we're going to set cpu->cfg attributes that are unrelated to misa_ext bits (icsr and ifencei). These would be 2 extra states that we would need to store to fallback from a validation failure. Since write_misa() is still on experimental state let's make our lives easier for now and disable RVG updates. Signed-off-by: Daniel Henrique Barboza --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab566639e5..02a5c2a5ca 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1347,6 +1347,11 @@ static RISCVException write_misa(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 + /* Changing 'G' state is unsupported */ + if (val & RVG) { + return RISCV_EXCP_NONE; + } + /* 'I' or 'E' must be present */ if (!(val & (RVI | RVE))) { /* It is not, drop write to misa */ --=20 2.39.2 From nobody Fri May 3 14:57:04 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678306925; cv=none; d=zohomail.com; s=zohoarc; b=fKom3aV3+vo70Kd5u48EY0ubJ6tTOJdgXynmy6kKRVSOlocmOZZDzVz3F46FVd1k5I0gc2ua3baw5BwaiY5Fd6znwrHkMMPrmVJ+r6lV5KIKsffNzo331oyjnBHgVvnPuAzwatEYoF32Z5Oe0plymCb1hfgt1TE4UEVkNUiEWVo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678306925; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EimxToi/BazSalyp/y380Q6hQb77b660ehnq+DK3D7I=; b=LbPnhmOn7TWPedUAEK5PU4uhSrpXWGexOfQ/y0M9mGqQuupnUwNktnLlqRjKIr8N8hplWiY1yCyziohunBBRwhAo+iTaaKYgDrDUJddYcDQVLGJOC7nB/7n2GcMFi55hW1ADBPTJ4+h/WaiwhqRdQwJbvaicbI8fWgstx/KefHs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678306925797125.98773061958548; Wed, 8 Mar 2023 12:22:05 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pa0Gx-0008OI-2A; Wed, 08 Mar 2023 15:20:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pa0Gw-0008O0-Bc for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:26 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pa0Gu-0002nG-86 for qemu-devel@nongnu.org; Wed, 08 Mar 2023 15:20:25 -0500 Received: by mail-oi1-x236.google.com with SMTP id be16so49197oib.0 for ; Wed, 08 Mar 2023 12:20:23 -0800 (PST) Received: from grind.. ([177.189.53.31]) by smtp.gmail.com with ESMTPSA id i66-20020aca3b45000000b00383e9fa1eaasm6705790oia.43.2023.03.08.12.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Mar 2023 12:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678306823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EimxToi/BazSalyp/y380Q6hQb77b660ehnq+DK3D7I=; b=k4V3Sf5/+dq3Dq3abaWsRUkMKiO32iqs55XXcZtAs8Ny5P1UuP0YOvo4/mlWthfm+E 2GeYol8V79yt3N87GHLxC1KuubCtYE6TMsGTryeT1EUxWsIePhD0KdumlHuJYMD6ur/8 SEAtLOhqRJmOTuaDLh/ygTV+qFVcwScCEQlI2rVG6tffQHVPc5oe+aEhVsRmIhJHdLJL TnYVtfEd3DIr/7vCYNprGd5WHmHMlPwQsXzZTIHFRnywj9EwujBBhd3hvmoJ3bwwNWW9 vH3XNAb96U1IO6ITo/LR9ruvc+VsFl9LhtlzpJI4O8juhjLUyJ2h0s3Umrsv3SbISkPc WdSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678306823; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EimxToi/BazSalyp/y380Q6hQb77b660ehnq+DK3D7I=; b=r5w93JURHKG3pK1CWa1S95Q4+dpgOH7EhuMmd1Elj76NLN4UbGw87IEfBea9GGuZ0I uHHFGpeifu/fBinnx9ug31SaoXYEtqvmnrKJBg5GTCOQTs3mbC+x9IMjhm+7w0AV1bEO aqQCOmOpE5SaUwLJpPB1zI9N0MedxJ6GJHNn9HmhTKUEiwfAvWKqcCFFbUEBZfDxeS38 fNg8lKbATZQ6ndl8aZbgPyrxZ7rzMN2/I6raH9FcKgzY7zRGBuvOVoagpdjZvLM3tjI+ DnmI4axDPtQydkkJHoA9TCJziadHL81CMavIykLCp+bcCJxqm1TMgi2h6GmlXTxhLCeC zwOA== X-Gm-Message-State: AO0yUKUPcNcsPdXhRJrL7XwmUIgA3wlNpPuI8ojjIcnOC5odavgWEnNN ASUmwdcZN9f1U27exIS9Tn4IE7NbeMezsWvFq64= X-Google-Smtp-Source: AK7set+sAzdLqPgAeeI7F5klEJ8lnp6NPg9uTtGWsr0Kvl4Cw02OE+eAiCrVDapvfNW9SJ3WLARRnQ== X-Received: by 2002:a05:6808:902:b0:378:a144:f7ad with SMTP id w2-20020a056808090200b00378a144f7admr9466837oih.17.1678306823184; Wed, 08 Mar 2023 12:20:23 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 17/17] target/riscv: rework write_misa() Date: Wed, 8 Mar 2023 17:19:25 -0300 Message-Id: <20230308201925.258223-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230308201925.258223-1-dbarboza@ventanamicro.com> References: <20230308201925.258223-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1678306926832100003 Content-Type: text/plain; charset="utf-8" write_misa() must use as much common logic as possible, only specifying the bits that are exclusive to the CSR write operation and TCG internals. Rewrite write_misa() to work as follows: - supress RVC right after verifying that we're not updating RVG; - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - emulate the steps done by the cpu init() functions: set cpu->cfg using the desired misa value, validate it, and then commit; - fallback if the validation step fails. We'll need to re-write cpu->cfg with the original misa_ext value for the hart. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +++--- target/riscv/cpu.h | 2 ++ target/riscv/csr.c | 53 +++++++++++++++++++++------------------------- 3 files changed, 29 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7be6a86305..4b2be32de3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -281,8 +281,7 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPU= Config *cfg) return ext; } =20 -static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, - uint32_t misa_ext) +static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, uint32_t misa_= ext) { cfg->ext_i =3D misa_ext & RVI; cfg->ext_e =3D misa_ext & RVE; @@ -299,7 +298,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *= cfg, cfg->ext_g =3D misa_ext & RVG; } =20 -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; @@ -995,7 +994,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVC= PU *cpu) * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. */ -static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); CPUClass *cc =3D CPU_CLASS(mcc); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 013a1389d6..d64d0f8dd6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -591,6 +591,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext); +void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 02a5c2a5ca..2e75c75fcc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1342,6 +1342,11 @@ static RISCVException read_misa(CPURISCVState *env, = int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu =3D env_archcpu(env); + uint32_t hart_ext_mask =3D env->misa_ext_mask; + uint32_t hart_ext =3D env->misa_ext; + Error *local_err =3D NULL; + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; @@ -1352,34 +1357,6 @@ static RISCVException write_misa(CPURISCVState *env,= int csrno, return RISCV_EXCP_NONE; } =20 - /* 'I' or 'E' must be present */ - if (!(val & (RVI | RVE))) { - /* It is not, drop write to misa */ - return RISCV_EXCP_NONE; - } - - /* 'E' excludes all other extensions */ - if (val & RVE) { - /* - * when we support 'E' we can do "val =3D RVE;" however - * for now we just drop writes if 'E' is present. - */ - return RISCV_EXCP_NONE; - } - - /* - * misa.MXL writes are not supported by QEMU. - * Drop writes to those bits. - */ - - /* Mask extensions that are not supported by this hart */ - val &=3D env->misa_ext_mask; - - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ - if ((val & RVD) && !(val & RVF)) { - val &=3D ~RVD; - } - /* * Suppress 'C' if next instruction is not aligned * TODO: this should check next_pc @@ -1388,18 +1365,36 @@ static RISCVException write_misa(CPURISCVState *env= , int csrno, val &=3D ~RVC; } =20 + /* Mask extensions that are not supported by this hart */ + val &=3D hart_ext_mask; + /* If nothing changed, do nothing. */ if (val =3D=3D env->misa_ext) { return RISCV_EXCP_NONE; } =20 + /* + * Validate the new configuration. Rollback to previous + * values if something goes wrong. + */ + set_misa(env, env->misa_mxl, val); + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err) { + set_misa(env, env->misa_mxl, hart_ext); + return RISCV_EXCP_NONE; + } + + /* + * Keep the original misa_ext_mask from the hart. + */ + env->misa_ext_mask =3D hart_ext_mask; + if (!(val & RVF)) { env->mstatus &=3D ~MSTATUS_FS; } =20 /* flush translation cache */ tb_flush(env_cpu(env)); - env->misa_ext =3D val; env->xl =3D riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } --=20 2.39.2