From nobody Fri May 3 20:00:31 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678346091333171.26870563011812; Wed, 8 Mar 2023 23:14:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATH-0004x2-9H; Thu, 09 Mar 2023 02:13:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paATE-0004um-FX; Thu, 09 Mar 2023 02:13:48 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATB-0005s6-GF; Thu, 09 Mar 2023 02:13:48 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowABHNxQdhwlk2VFnAA--.11047S3; Thu, 09 Mar 2023 15:13:35 +0800 (CST) From: Weiwei Li To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH 1/4] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Date: Thu, 9 Mar 2023 15:13:26 +0800 Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309071329.45932-1-liweiwei@iscas.ac.cn> References: <20230309071329.45932-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowABHNxQdhwlk2VFnAA--.11047S3 X-Coremail-Antispam: 1UD129KBjvJXoW3Wr1fXF1rZF4xAw4rXFyUtrb_yoWxZry7pr 4UuFZxGFW7ta4qva93Gr1DXF1rJ34xK3yYkws7Wa95tF45JrW5GF1DGaya9F4DWa48Z34j yayUCr1jyr4jvFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPj14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AK xVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrx kI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v2 6r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8Jw CI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU5SoXUUUU U X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678346093024100001 Content-Type: text/plain; charset="utf-8" Use riscv_cpu_cfg(env) instead of env_archcpu().cfg. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_helper.c | 9 ++++----- target/riscv/csr.c | 40 ++++++++++++--------------------------- target/riscv/gdbstub.c | 4 ++-- 3 files changed, 18 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f88c503cf4..e677255f87 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, int extirq, unsigned int extirq_def_pr= io, uint64_t pending, uint8_t *iprio) { - RISCVCPU *cpu =3D env_archcpu(env); int irq, best_irq =3D RISCV_EXCP_NONE; unsigned int prio, best_prio =3D UINT_MAX; =20 @@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env, } =20 irq =3D ctz64(pending); - if (!((extirq =3D=3D IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ss= aia)) { + if (!((extirq =3D=3D IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia : + riscv_cpu_cfg(env)->ext_ssaia)) { return irq; } =20 @@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; hwaddr ppn; - RISCVCPU *cpu =3D env_archcpu(env); int napot_bits =3D 0; target_ulong napot_mask; =20 @@ -946,7 +945,7 @@ restart: =20 if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { ppn =3D pte >> PTE_PPN_SHIFT; - } else if (pbmte || cpu->cfg.ext_svnapot) { + } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) { ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { ppn =3D pte >> PTE_PPN_SHIFT; @@ -1043,7 +1042,7 @@ restart: benefit. */ target_ulong vpn =3D addr >> PGSHIFT; =20 - if (cpu->cfg.ext_svnapot && (pte & PTE_N)) { + if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) { napot_bits =3D ctzl(ppn) + 1; if ((i !=3D (levels - 1)) || (napot_bits !=3D 4)) { return TRANSLATE_FAIL; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ab566639e5..b453d8e8ca 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -88,9 +88,7 @@ static RISCVException fs(CPURISCVState *env, int csrno) =20 static RISCVException vs(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (cpu->cfg.ext_zve32f) { + if (riscv_cpu_cfg(env)->ext_zve32f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; @@ -193,9 +191,7 @@ static RISCVException mctr32(CPURISCVState *env, int cs= rno) =20 static RISCVException sscofpmf(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (!cpu->cfg.ext_sscofpmf) { + if (!riscv_cpu_cfg(env)->ext_sscofpmf) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -310,9 +306,7 @@ static RISCVException umode32(CPURISCVState *env, int c= srno) =20 static RISCVException mstateen(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (!cpu->cfg.ext_smstateen) { + if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -321,9 +315,7 @@ static RISCVException mstateen(CPURISCVState *env, int = csrno) =20 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int bas= e) { - RISCVCPU *cpu =3D env_archcpu(env); - - if (!cpu->cfg.ext_smstateen) { + if (!riscv_cpu_cfg(env)->ext_smstateen) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -390,10 +382,9 @@ static RISCVException sstateen(CPURISCVState *env, int= csrno) =20 static RISCVException sstc(CPURISCVState *env, int csrno) { - RISCVCPU *cpu =3D env_archcpu(env); bool hmode_check =3D false; =20 - if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { + if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -1170,27 +1161,21 @@ static RISCVException write_ignore(CPURISCVState *e= nv, int csrno, static RISCVException read_mvendorid(CPURISCVState *env, int csrno, target_ulong *val) { - RISCVCPU *cpu =3D env_archcpu(env); - - *val =3D cpu->cfg.mvendorid; + *val =3D riscv_cpu_cfg(env)->mvendorid; return RISCV_EXCP_NONE; } =20 static RISCVException read_marchid(CPURISCVState *env, int csrno, target_ulong *val) { - RISCVCPU *cpu =3D env_archcpu(env); - - *val =3D cpu->cfg.marchid; + *val =3D riscv_cpu_cfg(env)->marchid; return RISCV_EXCP_NONE; } =20 static RISCVException read_mimpid(CPURISCVState *env, int csrno, target_ulong *val) { - RISCVCPU *cpu =3D env_archcpu(env); - - *val =3D cpu->cfg.mimpid; + *val =3D riscv_cpu_cfg(env)->mimpid; return RISCV_EXCP_NONE; } =20 @@ -1232,9 +1217,8 @@ static RISCVException read_mstatus(CPURISCVState *env= , int csrno, =20 static bool validate_vm(CPURISCVState *env, target_ulong vm) { - RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); - - return (vm & 0xf) <=3D satp_mode_max_from_map(cpu->cfg.satp_mode.map); + return (vm & 0xf) <=3D + satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map); } =20 static RISCVException write_mstatus(CPURISCVState *env, int csrno, @@ -1897,7 +1881,7 @@ static RISCVException read_menvcfg(CPURISCVState *env= , int csrno, static RISCVException write_menvcfg(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPUConfig *cfg =3D &env_archcpu(env)->cfg; + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCF= G_CBZE; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { @@ -1920,7 +1904,7 @@ static RISCVException read_menvcfgh(CPURISCVState *en= v, int csrno, static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPUConfig *cfg =3D &env_archcpu(env)->cfg; + const RISCVCPUConfig *cfg =3D riscv_cpu_cfg(env); uint64_t mask =3D (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) | (cfg->ext_sstc ? MENVCFG_STCE : 0) | (cfg->ext_svadu ? MENVCFG_HADE : 0); diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 6048541606..b2e08f1979 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -129,7 +129,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_= t *mem_buf, int n) =20 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n) { - uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; int cnt =3D 0; @@ -145,7 +145,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GBy= teArray *buf, int n) =20 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int = n) { - uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + uint16_t vlenb =3D riscv_cpu_cfg(env)->vlen >> 3; if (n < 32) { int i; for (i =3D 0; i < vlenb; i +=3D 8) { --=20 2.25.1 From nobody Fri May 3 20:00:31 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678346080356360.52079235927283; Wed, 8 Mar 2023 23:14:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATG-0004vL-5L; Thu, 09 Mar 2023 02:13:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paATE-0004uc-5i; Thu, 09 Mar 2023 02:13:48 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATB-0005sT-Gc; Thu, 09 Mar 2023 02:13:47 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowABHNxQdhwlk2VFnAA--.11047S4; Thu, 09 Mar 2023 15:13:36 +0800 (CST) From: Weiwei Li To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH 2/4] target/riscv: Simplify getting RISCVCPU pointer from env Date: Thu, 9 Mar 2023 15:13:27 +0800 Message-Id: <20230309071329.45932-3-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309071329.45932-1-liweiwei@iscas.ac.cn> References: <20230309071329.45932-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowABHNxQdhwlk2VFnAA--.11047S4 X-Coremail-Antispam: 1UD129KBjvJXoW7KFy7CF45AFWUKFyfCrW8Crg_yoW8WryUpr W8CFZ3XrW0qwnFg345tr1UAF4kJw45Kws0kw1DA3yYvFsxJFs5ZF1DGw1SyFsxCa48u34U t3y5ur13ZF4I9FDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AK xVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrx kI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v2 6r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8Jw CI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfU8BMNUUUU U X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678346081407100002 Content-Type: text/plain; charset="utf-8" Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/pmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index b8e56d2b7b..a200741083 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -223,7 +223,7 @@ bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *= env, return true; } =20 - cpu =3D RISCV_CPU(env_cpu(env)); + cpu =3D env_archcpu(env); if (!cpu->pmu_event_ctr_map) { return false; } @@ -249,7 +249,7 @@ bool riscv_pmu_ctr_monitor_cycles(CPURISCVState *env, u= int32_t target_ctr) return true; } =20 - cpu =3D RISCV_CPU(env_cpu(env)); + cpu =3D env_archcpu(env); if (!cpu->pmu_event_ctr_map) { return false; } @@ -289,7 +289,7 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint= 64_t value, uint32_t ctr_idx) { uint32_t event_idx; - RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + RISCVCPU *cpu =3D env_archcpu(env); =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->pmu_event_ctr_map)= { return -1; @@ -390,7 +390,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t = value, uint32_t ctr_idx) { uint64_t overflow_delta, overflow_at; int64_t overflow_ns, overflow_left =3D 0; - RISCVCPU *cpu =3D RISCV_CPU(env_cpu(env)); + RISCVCPU *cpu =3D env_archcpu(env); PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; =20 if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf) { --=20 2.25.1 From nobody Fri May 3 20:00:31 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678346091839423.05039399520206; Wed, 8 Mar 2023 23:14:51 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATI-0004zD-Qe; Thu, 09 Mar 2023 02:13:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paATG-0004w2-1C; Thu, 09 Mar 2023 02:13:50 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATB-0005sV-H3; Thu, 09 Mar 2023 02:13:49 -0500 Received: from localhost.localdomain (unknown [180.165.240.213]) by APP-05 (Coremail) with SMTP id zQCowABHNxQdhwlk2VFnAA--.11047S5; Thu, 09 Mar 2023 15:13:36 +0800 (CST) From: Weiwei Li To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH 3/4] target/riscv: Simplify type conversion for CPURISCVState Date: Thu, 9 Mar 2023 15:13:28 +0800 Message-Id: <20230309071329.45932-4-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230309071329.45932-1-liweiwei@iscas.ac.cn> References: <20230309071329.45932-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowABHNxQdhwlk2VFnAA--.11047S5 X-Coremail-Antispam: 1UD129KBjvAXoW3uFyfuFWrWrykuw4DJr43Jrb_yoW8JF15Zo WFgF4kAr1xG3WIyas09r17tryUGr1kJwsYvr4vyFWfW3WxWrn5Gr47tr12yF17trW3KFW8 Xa4xWF4UXa1xGay3n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOU7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r1rM28IrcIa0x kI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJw A2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAF wI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc4 0Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AK xVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr 1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbJ73DUU UUU== X-Originating-IP: [180.165.240.213] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678346093031100002 Content-Type: text/plain; charset="utf-8" Use CPURISCVState as argument directly in riscv_cpu_update_mip and riscv_timer_write_timecmp, since type converts from CPURISCVState to RISCVCPU in many caller of them and then back to CPURISCVState in them. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 6 +++--- target/riscv/cpu.h | 3 ++- target/riscv/cpu_helper.c | 8 ++++---- target/riscv/csr.c | 35 +++++++++++------------------------ target/riscv/pmu.c | 6 +++--- target/riscv/time_helper.c | 15 +++++++-------- target/riscv/time_helper.h | 2 +- 7 files changed, 31 insertions(+), 44 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..16e465a0ab 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1302,7 +1302,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) if (kvm_enabled()) { kvm_riscv_set_irq(cpu, irq, level); } else { - riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); + riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); } break; case IRQ_S_EXT: @@ -1310,7 +1310,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) kvm_riscv_set_irq(cpu, irq, level); } else { env->external_seip =3D level; - riscv_cpu_update_mip(cpu, 1 << irq, + riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level | env->software_se= ip)); } break; @@ -1336,7 +1336,7 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) } =20 /* Update mip.SGEIP bit */ - riscv_cpu_update_mip(cpu, MIP_SGEIP, + riscv_cpu_update_mip(env, MIP_SGEIP, BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); } else { g_assert_not_reached(); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..5adefe4ab5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -602,7 +602,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vad= dr addr); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value= ); +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, + uint64_t value); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), void *arg); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e677255f87..824f0cbd92 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -590,7 +590,7 @@ void riscv_cpu_set_virt_enabled(CPURISCVState *env, boo= l enable) * * To solve this, we check and inject interrupt after setting V=3D= 1. */ - riscv_cpu_update_mip(env_archcpu(env), 0, 0); + riscv_cpu_update_mip(env, 0, 0); } } =20 @@ -610,10 +610,10 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_= t interrupts) } } =20 -uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) +uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, + uint64_t value) { - CPURISCVState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); + CPUState *cs =3D env_cpu(env); uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; =20 if (riscv_cpu_virt_enabled(env)) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index b453d8e8ca..53143f4d9a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -990,15 +990,13 @@ static RISCVException read_vstimecmph(CPURISCVState *= env, int csrno, static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { env->vstimecmp =3D deposit64(env->vstimecmp, 0, 32, (uint64_t)val); } else { env->vstimecmp =3D val; } =20 - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); =20 return RISCV_EXCP_NONE; @@ -1007,10 +1005,8 @@ static RISCVException write_vstimecmp(CPURISCVState = *env, int csrno, static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - env->vstimecmp =3D deposit64(env->vstimecmp, 32, 32, (uint64_t)val); - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); =20 return RISCV_EXCP_NONE; @@ -1043,8 +1039,6 @@ static RISCVException read_stimecmph(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmp(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (riscv_cpu_virt_enabled(env)) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -1058,7 +1052,7 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, env->stimecmp =3D val; } =20 - riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP= ); =20 return RISCV_EXCP_NONE; } @@ -1066,8 +1060,6 @@ static RISCVException write_stimecmp(CPURISCVState *e= nv, int csrno, static RISCVException write_stimecmph(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (riscv_cpu_virt_enabled(env)) { if (env->hvictl & HVICTL_VTI) { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; @@ -1076,7 +1068,7 @@ static RISCVException write_stimecmph(CPURISCVState *= env, int csrno, } =20 env->stimecmp =3D deposit64(env->stimecmp, 32, 32, (uint64_t)val); - riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP= ); =20 return RISCV_EXCP_NONE; } @@ -2211,7 +2203,6 @@ static RISCVException rmw_mip64(CPURISCVState *env, i= nt csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) { - RISCVCPU *cpu =3D env_archcpu(env); uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 @@ -2220,14 +2211,14 @@ static RISCVException rmw_mip64(CPURISCVState *env,= int csrno, new_val |=3D env->external_seip * MIP_SEIP; } =20 - if (cpu->cfg.ext_sstc && (env->priv =3D=3D PRV_M) && + if (riscv_cpu_cfg(env)->ext_sstc && (env->priv =3D=3D PRV_M) && get_field(env->menvcfg, MENVCFG_STCE)) { /* sstc extension forbids STIP & VSTIP to be writeable in mip */ mask =3D mask & ~(MIP_STIP | MIP_VSTIP); } =20 if (mask) { - old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); + old_mip =3D riscv_cpu_update_mip(env, mask, (new_val & mask)); } else { old_mip =3D env->mip; } @@ -2987,7 +2978,7 @@ static RISCVException write_hgeie(CPURISCVState *env,= int csrno, val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; env->hgeie =3D val; /* Update mip.SGEIP bit */ - riscv_cpu_update_mip(env_archcpu(env), MIP_SGEIP, + riscv_cpu_update_mip(env, MIP_SGEIP, BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); return RISCV_EXCP_NONE; } @@ -3056,8 +3047,6 @@ static RISCVException read_htimedelta(CPURISCVState *= env, int csrno, static RISCVException write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -3068,8 +3057,8 @@ static RISCVException write_htimedelta(CPURISCVState = *env, int csrno, env->htimedelta =3D val; } =20 - if (cpu->cfg.ext_sstc && env->rdtime_fn) { - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); } =20 @@ -3090,16 +3079,14 @@ static RISCVException read_htimedeltah(CPURISCVStat= e *env, int csrno, static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) { - RISCVCPU *cpu =3D env_archcpu(env); - if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); =20 - if (cpu->cfg.ext_sstc && env->rdtime_fn) { - riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); } =20 diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index a200741083..22e2283c76 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -133,7 +133,7 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint3= 2_t ctr_idx) /* Generate interrupt only if OF bit is clear */ if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) { env->mhpmeventh_val[ctr_idx] |=3D MHPMEVENTH_BIT_OF; - riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } else { counter->mhpmcounterh_val++; @@ -172,7 +172,7 @@ static int riscv_pmu_incr_ctr_rv64(RISCVCPU *cpu, uint3= 2_t ctr_idx) /* Generate interrupt only if OF bit is clear */ if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) { env->mhpmevent_val[ctr_idx] |=3D MHPMEVENT_BIT_OF; - riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } else { counter->mhpmcounter_val++; @@ -371,7 +371,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu, /* Generate interrupt only if OF bit is clear */ if (!(*mhpmevent_val & of_bit_mask)) { *mhpmevent_val |=3D of_bit_mask; - riscv_cpu_update_mip(cpu, MIP_LCOFIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1)); } } } diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index b654f91af9..8d245bed3a 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -27,25 +27,24 @@ static void riscv_vstimer_cb(void *opaque) RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; env->vstime_irq =3D 1; - riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); } =20 static void riscv_stimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; - riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(&cpu->env, MIP_STIP, BOOL_TO_MASK(1)); } =20 /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <=3D current timer value. */ -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq) { uint64_t diff, ns_diff, next; - CPURISCVState *env =3D &cpu->env; RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_arg; uint32_t timebase_freq =3D mtimer->timebase_freq; uint64_t rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; @@ -57,9 +56,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *= timer, */ if (timer_irq =3D=3D MIP_VSTIP) { env->vstime_irq =3D 1; - riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(1)); } else { - riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(env, MIP_STIP, BOOL_TO_MASK(1)); } return; } @@ -67,9 +66,9 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *= timer, /* Clear the [VS|S]TIP bit in mip */ if (timer_irq =3D=3D MIP_VSTIP) { env->vstime_irq =3D 0; - riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); + riscv_cpu_update_mip(env, 0, BOOL_TO_MASK(0)); } else { - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); + riscv_cpu_update_mip(env, timer_irq, BOOL_TO_MASK(0)); } =20 /* diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h index 7b3cdcc350..cacd79b80c 100644 --- a/target/riscv/time_helper.h +++ b/target/riscv/time_helper.h @@ -22,7 +22,7 @@ #include "cpu.h" #include "qemu/timer.h" =20 -void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, +void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq); void riscv_timer_init(RISCVCPU *cpu); --=20 2.25.1 From nobody Fri May 3 20:00:31 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678346113639391.6764860361477; Wed, 8 Mar 2023 23:15:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATI-0004z8-LV; Thu, 09 Mar 2023 02:13:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paATF-0004vR-JM; Thu, 09 Mar 2023 02:13:49 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paATC-0005sU-Bf; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=159.226.251.25; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1678346115119100005 Content-Type: text/plain; charset="utf-8" Remove RISCVCPU argument, and get cfg infomation from CPURISCVState directly. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/csr.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 53143f4d9a..80fc15e4d6 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3755,15 +3755,14 @@ static RISCVException rmw_seed(CPURISCVState *env, = int csrno, =20 static inline RISCVException riscv_csrrw_check(CPURISCVState *env, int csrno, - bool write_mask, - RISCVCPU *cpu) + bool write_mask) { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ bool read_only =3D get_field(csrno, 0xC00) =3D=3D 3; int csr_min_priv =3D csr_ops[csrno].min_priv_ver; =20 /* ensure the CSR extension is enabled */ - if (!cpu->cfg.ext_icsr) { + if (!riscv_cpu_cfg(env)->ext_icsr) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -3859,9 +3858,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int cs= rno, target_ulong *ret_value, target_ulong new_value, target_ulong write_mask) { - RISCVCPU *cpu =3D env_archcpu(env); - - RISCVException ret =3D riscv_csrrw_check(env, csrno, write_mask, cpu); + RISCVException ret =3D riscv_csrrw_check(env, csrno, write_mask); if (ret !=3D RISCV_EXCP_NONE) { return ret; } @@ -3914,9 +3911,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, i= nt csrno, Int128 new_value, Int128 write_mask) { RISCVException ret; - RISCVCPU *cpu =3D env_archcpu(env); =20 - ret =3D riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); + ret =3D riscv_csrrw_check(env, csrno, int128_nz(write_mask)); if (ret !=3D RISCV_EXCP_NONE) { return ret; } --=20 2.25.1