From nobody Sun May 5 06:23:02 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1678370498; cv=none; d=zohomail.com; s=zohoarc; b=jRcsAmWQjdq72WBvbnsvnaaU0lCV6U1KWwpvNflMlURUCTcPO7jVbIgLRRuy71h0SOSD5EmG0IVtfzQwF5YMdR2YPjQIhYuUSQKf8zVjeHUy10rdRVvj5qhwwmsMKtyQsHWTZBmUvCLEZ9WRnfQN4bk93VLcUlDhniEfL+bloSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1678370498; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=eFm8VCL1PLveRB8WCNxZodpv/TMfY4YITyhE/ClC8l8=; b=Y7yhNn2vNOLjdjh2xHE95IXW5S1lx2B/g9f3bUle0WRV+7xaw+LzeY/QlYqO+yrxpJFQNQsSa/eIN+MeTqINIbDWfMyxIuLFFm63cZaUnLH42QYfZoWjgV5Smw61z8hRQFFKg0AnylGWkOg5cUXk4aGNYSZTY+eSH4qWD/kyNcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1678370498885569.7038645614814; Thu, 9 Mar 2023 06:01:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1paGpI-0004ja-Ve; Thu, 09 Mar 2023 09:01:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paGpB-0004bp-Qz; Thu, 09 Mar 2023 09:00:55 -0500 Received: from forward106j.mail.yandex.net ([2a02:6b8:0:801:2::109]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1paGp9-0001Ip-K9; Thu, 09 Mar 2023 09:00:53 -0500 Received: from iva3-dd2bb2ff2b5f.qloud-c.yandex.net (iva3-dd2bb2ff2b5f.qloud-c.yandex.net [IPv6:2a02:6b8:c0c:7611:0:640:dd2b:b2ff]) by forward106j.mail.yandex.net (Yandex) with ESMTP id 8480F6BD89B3; Thu, 9 Mar 2023 16:54:14 +0300 (MSK) Received: by iva3-dd2bb2ff2b5f.qloud-c.yandex.net (smtp/Yandex) with ESMTPSA id BsdJhR3bk8c1-0CWZd0hO; Thu, 09 Mar 2023 16:54:13 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=syntacore.com; s=mail; t=1678370053; bh=eFm8VCL1PLveRB8WCNxZodpv/TMfY4YITyhE/ClC8l8=; h=Message-Id:Date:Cc:Subject:To:From; b=eXO6xgfKMVH5YttMDw5vTLPnIxHBmLWpblKXzD9jQ30CGZnGI92I+GrTjuqsdHsXj snax24S5RkL5ff+OufcZSkRz+yiD1qmpy/P8OtA++8A3UDJ/AVZorlUvQoU4RSsQGq g2Lm4Axy6olegjmWxv6pEr1EdTEhOrgdr531f+6I= Authentication-Results: iva3-dd2bb2ff2b5f.qloud-c.yandex.net; dkim=pass header.i=@syntacore.com From: Ivan Klokov To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, marcel.apfelbaum@gmail.com, philmd@linaro.org, wangyanan55@huawei.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, liu@linux.alibaba.com, Ivan Klokov Subject: [PATCH v2] target/riscv: Add RVV registers to log Date: Thu, 9 Mar 2023 16:54:03 +0300 Message-Id: <20230309135403.102703-1-ivan.klokov@syntacore.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a02:6b8:0:801:2::109; envelope-from=ivan.klokov@syntacore.com; helo=forward106j.mail.yandex.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @syntacore.com) X-ZM-MESSAGEID: 1678370500657100001 Content-Type: text/plain; charset="utf-8" Added QEMU option 'rvv' to add RISC-V RVV registers to log like regular reg= s. Signed-off-by: Ivan Klokov --- v2: - fix option name - fix byte ordering --- accel/tcg/cpu-exec.c | 3 +++ include/hw/core/cpu.h | 2 ++ include/qemu/log.h | 1 + target/riscv/cpu.c | 59 ++++++++++++++++++++++++++++++++++++++++++- util/log.c | 2 ++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 56aaf58b9d..0dca69fccb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -319,6 +319,9 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, #if defined(TARGET_I386) flags |=3D CPU_DUMP_CCOP; #endif + if (qemu_loglevel_mask(CPU_LOG_TB_VPU)) { + flags |=3D CPU_DUMP_VPU; + } cpu_dump_state(cpu, logfile, flags); qemu_log_unlock(logfile); } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 75689bff02..7c9d25ff45 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -545,11 +545,13 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *c= pu); * @CPU_DUMP_CODE: * @CPU_DUMP_FPU: dump FPU register state, not just integer * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization = state + * @CPU_DUMP_VPU: dump VPU registers */ enum CPUDumpFlags { CPU_DUMP_CODE =3D 0x00010000, CPU_DUMP_FPU =3D 0x00020000, CPU_DUMP_CCOP =3D 0x00040000, + CPU_DUMP_VPU =3D 0x00080000, }; =20 /** diff --git a/include/qemu/log.h b/include/qemu/log.h index c5643d8dd5..df59bfabcd 100644 --- a/include/qemu/log.h +++ b/include/qemu/log.h @@ -35,6 +35,7 @@ bool qemu_log_separate(void); /* LOG_STRACE is used for user-mode strace logging. */ #define LOG_STRACE (1 << 19) #define LOG_PER_THREAD (1 << 20) +#define CPU_LOG_TB_VPU (1 << 21) =20 /* Lock/unlock output. */ =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5bc0005cc7..0b16c9c8e3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -172,6 +172,14 @@ const char * const riscv_fpr_regnames[] =3D { "f30/ft10", "f31/ft11" }; =20 +const char * const riscv_rvv_regnames[] =3D { + "v0", "v1", "v2", "v3", "v4", "v5", "v6", + "v7", "v8", "v9", "v10", "v11", "v12", "v13", + "v14", "v15", "v16", "v17", "v18", "v19", "v20", + "v21", "v22", "v23", "v24", "v25", "v26", "v27", + "v28", "v29", "v30", "v31" +}; + static const char * const riscv_excp_names[] =3D { "misaligned_fetch", "fault_fetch", @@ -422,7 +430,8 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,= int flags) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; - int i; + int i, j; + uint8_t *p; =20 #if !defined(CONFIG_USER_ONLY) if (riscv_has_ext(env, RVH)) { @@ -506,6 +515,54 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f= , int flags) } } } + if (riscv_has_ext(env, RVV)) { + if (flags & CPU_DUMP_VPU) { + + static const int dump_rvv_csrs[] =3D { + CSR_VSTART, + CSR_VXSAT, + CSR_VXRM, + CSR_VCSR, + CSR_VL, + CSR_VTYPE, + CSR_VLENB, + }; + for (int i =3D 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { + int csrno =3D dump_rvv_csrs[i]; + target_ulong val =3D 0; + RISCVException res =3D riscv_csrrw_debug(env, csrno, &val,= 0, 0); + + /* + * Rely on the smode, hmode, etc, predicates within csr.c + * to do the filtering of the registers that are present. + */ + if (res =3D=3D RISCV_EXCP_NONE) { + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", + csr_ops[csrno].name, val); + } + } + uint16_t vlenb =3D env_archcpu(env)->cfg.vlen >> 3; + +/* + * From vector_helper.c + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing bytes needs a host-endian fixup. + */ +#if HOST_BIG_ENDIAN +#define BYTE(x) ((x) ^ 7) +#else +#define BYTE(x) (x) +#endif + for (i =3D 0; i < 32; i++) { + qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); + p =3D (uint8_t *)env->vreg; + for (j =3D vlenb - 1 ; j >=3D 0; j--) { + qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); + } + qemu_fprintf(f, "\n"); + } + } + } } =20 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/util/log.c b/util/log.c index 7837ff9917..93dccee7b8 100644 --- a/util/log.c +++ b/util/log.c @@ -495,6 +495,8 @@ const QEMULogItem qemu_log_items[] =3D { "log every user-mode syscall, its input, and its result" }, { LOG_PER_THREAD, "tid", "open a separate log file per thread; filename must contain '%d'" }, + { CPU_LOG_TB_VPU, "vpu", + "include VPU registers in the 'cpu' logging" }, { 0, NULL, NULL }, }; =20 --=20 2.34.1