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a=ed25519-sha256; c=relaxed/relaxed; d=suse.de; s=susede2_ed25519; t=1678720267; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nptKRQnsHpIdNNKIq92B/YnmPkxjddmyC7pfo4kLYZI=; b=+FAt7f0hvZkRAbonQfIb3SSj+2KoEBqctLKY+vRu4i/4PemzwaPWPNRtthxFFqhdsNodZN +5/puTl8arWTUeCA== From: Fabiano Rosas To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Claudio Fontana , Eduardo Habkost , Alexander Graf , Cornelia Huck Subject: [PATCH v9 01/10] target/arm: Move cortex sysregs into a separate file Date: Mon, 13 Mar 2023 12:10:49 -0300 Message-Id: <20230313151058.19645-2-farosas@suse.de> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20230313151058.19645-1-farosas@suse.de> References: <20230313151058.19645-1-farosas@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.28; envelope-from=farosas@suse.de; helo=smtp-out1.suse.de X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @suse.de) X-ZM-MESSAGEID: 1678720429590100003 Content-Type: text/plain; charset="utf-8" The file cpu_tcg.c is about to be moved into the tcg/ directory, so move the register definitions into a new file. Also move the function declaration to the more appropriate cpregs.h. Reviewed-by: Richard Henderson Signed-off-by: Fabiano Rosas --- target/arm/cortex-regs.c | 69 ++++++++++++++++++++++++++++++++++++++++ target/arm/cpregs.h | 6 ++++ target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 59 ---------------------------------- target/arm/internals.h | 6 ---- target/arm/meson.build | 1 + 6 files changed, 77 insertions(+), 65 deletions(-) create mode 100644 target/arm/cortex-regs.c diff --git a/target/arm/cortex-regs.c b/target/arm/cortex-regs.c new file mode 100644 index 0000000000..17708480e7 --- /dev/null +++ b/target/arm/cortex-regs.c @@ -0,0 +1,69 @@ +/* + * ARM Cortex-A registers + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpregs.h" + + +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Number of cores is in [25:24]; otherwise we RAZ */ + return (cpu->core_count - 1) << 24; +} + +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { + { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2CTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ECTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR", + .cp =3D 15, .opc1 =3D 0, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR", + .cp =3D 15, .opc1 =3D 1, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUMERRSR", + .cp =3D 15, .opc1 =3D 2, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2MERRSR", + .cp =3D 15, .opc1 =3D 3, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, +}; + +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); +} diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1ee64e99de..b04d344a9f 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -1071,4 +1071,10 @@ static inline bool arm_cpreg_in_idspace(const ARMCPR= egInfo *ri) ri->crn, ri->crm); } =20 +#ifdef CONFIG_USER_ONLY +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } +#else +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); +#endif + #endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4066950da1..9f193927d8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,7 @@ #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "internals.h" +#include "cpregs.h" =20 static void aarch64_a35_initfn(Object *obj) { diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index df0c45e523..6ce728134f 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -93,65 +93,6 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_dfr0 =3D t; } =20 -#ifndef CONFIG_USER_ONLY -static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* Number of cores is in [25:24]; otherwise we RAZ */ - return (cpu->core_count - 1) << 24; -} - -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { - { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "L2CTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ECTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR", - .cp =3D 15, .opc1 =3D 0, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUECTLR", - .cp =3D 15, .opc1 =3D 1, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUMERRSR", - .cp =3D 15, .opc1 =3D 2, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2MERRSR", - .cp =3D 15, .opc1 =3D 3, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, -}; - -void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) -{ - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); -} -#endif /* !CONFIG_USER_ONLY */ - /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index b1ef05963f..46a1d06e15 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1370,12 +1370,6 @@ uint32_t arm_v7m_mrs_control(CPUARMState *env, uint3= 2_t secure); uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, bool spsel); =20 -#ifdef CONFIG_USER_ONLY -static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } -#else -void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); -#endif - bool el_is_in_host(CPUARMState *env, int el); =20 void aa32_max_features(ARMCPU *cpu); diff --git a/target/arm/meson.build b/target/arm/meson.build index 6226098ad5..3469926295 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -21,6 +21,7 @@ arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'arm-qmp-cmds.c', + 'cortex-regs.c', 'machine.c', 'ptw.c', )) --=20 2.35.3