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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679169974836100003 Content-Type: text/plain; charset="utf-8" The extremely tedious code that sets cpu->cfg based on misa_ext, and vice-versa, is scattered around riscv_cpu_validate_set_extensions() and set_misa(). Introduce helpers to do this work, cleaning up the logic of both functions a bit. While we're at it, add a note in cpu.h informing that any future change in MISA RV* bits should also be reflected in the helpers as well. We'll want to keep env->misa_ext changes in sync with cpu->cfg during realize() in the next patches, and both helpers will have a role to play in that. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 120 ++++++++++++++++++++++++--------------------- target/riscv/cpu.h | 3 +- 2 files changed, 65 insertions(+), 58 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b5096d25e..28d4c5f768 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -234,10 +234,69 @@ const char *riscv_cpu_get_trap_name(target_ulong caus= e, bool async) } } =20 -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) { - RISCVCPU *cpu; + uint32_t ext =3D 0; =20 + if (cfg->ext_i) { + ext |=3D RVI; + } + if (cfg->ext_e) { + ext |=3D RVE; + } + if (cfg->ext_m) { + ext |=3D RVM; + } + if (cfg->ext_a) { + ext |=3D RVA; + } + if (cfg->ext_f) { + ext |=3D RVF; + } + if (cfg->ext_d) { + ext |=3D RVD; + } + if (cfg->ext_c) { + ext |=3D RVC; + } + if (cfg->ext_s) { + ext |=3D RVS; + } + if (cfg->ext_u) { + ext |=3D RVU; + } + if (cfg->ext_h) { + ext |=3D RVH; + } + if (cfg->ext_v) { + ext |=3D RVV; + } + if (cfg->ext_j) { + ext |=3D RVJ; + } + + return ext; +} + +static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, + uint32_t misa_ext) +{ + cfg->ext_i =3D misa_ext & RVI; + cfg->ext_e =3D misa_ext & RVE; + cfg->ext_m =3D misa_ext & RVM; + cfg->ext_a =3D misa_ext & RVA; + cfg->ext_f =3D misa_ext & RVF; + cfg->ext_d =3D misa_ext & RVD; + cfg->ext_v =3D misa_ext & RVV; + cfg->ext_c =3D misa_ext & RVC; + cfg->ext_s =3D misa_ext & RVS; + cfg->ext_u =3D misa_ext & RVU; + cfg->ext_h =3D misa_ext & RVH; + cfg->ext_j =3D misa_ext & RVJ; +} + +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +{ env->misa_mxl_max =3D env->misa_mxl =3D mxl; env->misa_ext_mask =3D env->misa_ext =3D ext; =20 @@ -251,25 +310,7 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,= uint32_t ext) return; } =20 - /* - * We can't use riscv_cpu_cfg() in this case because it is - * a read-only inline and we're going to change the values - * of cpu->cfg. - */ - cpu =3D env_archcpu(env); - - cpu->cfg.ext_i =3D ext & RVI; - cpu->cfg.ext_e =3D ext & RVE; - cpu->cfg.ext_m =3D ext & RVM; - cpu->cfg.ext_a =3D ext & RVA; - cpu->cfg.ext_f =3D ext & RVF; - cpu->cfg.ext_d =3D ext & RVD; - cpu->cfg.ext_v =3D ext & RVV; - cpu->cfg.ext_c =3D ext & RVC; - cpu->cfg.ext_s =3D ext & RVS; - cpu->cfg.ext_u =3D ext & RVU; - cpu->cfg.ext_h =3D ext & RVH; - cpu->cfg.ext_j =3D ext & RVJ; + riscv_set_cpucfg_with_misa(&env_archcpu(env)->cfg, ext); } =20 #ifndef CONFIG_USER_ONLY @@ -1156,42 +1197,7 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) */ riscv_cpu_disable_priv_spec_isa_exts(cpu); =20 - if (cpu->cfg.ext_i) { - ext |=3D RVI; - } - if (cpu->cfg.ext_e) { - ext |=3D RVE; - } - if (cpu->cfg.ext_m) { - ext |=3D RVM; - } - if (cpu->cfg.ext_a) { - ext |=3D RVA; - } - if (cpu->cfg.ext_f) { - ext |=3D RVF; - } - if (cpu->cfg.ext_d) { - ext |=3D RVD; - } - if (cpu->cfg.ext_c) { - ext |=3D RVC; - } - if (cpu->cfg.ext_s) { - ext |=3D RVS; - } - if (cpu->cfg.ext_u) { - ext |=3D RVU; - } - if (cpu->cfg.ext_h) { - ext |=3D RVH; - } - if (cpu->cfg.ext_v) { - ext |=3D RVV; - } - if (cpu->cfg.ext_j) { - ext |=3D RVJ; - } + ext =3D riscv_get_misa_ext_with_cpucfg(&cpu->cfg); =20 env->misa_ext_mask =3D env->misa_ext =3D ext; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ebe0fff668..2263629332 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,7 +66,8 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) =20 /* - * Consider updating set_misa() when adding new + * Consider updating riscv_get_misa_ext_with_cpucfg() + * and riscv_set_cpucfg_with_misa() when adding new * MISA bits here. */ #define RVI RV('I') --=20 2.39.2