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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679170159645100003 Content-Type: text/plain; charset="utf-8" The 'G' bit in misa_ext is a virtual extension that enables a set of extensions (i, m, a, f, d, icsr and ifencei). We're already have code to handle it but no bit definition. Add it. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 28d4c5f768..48ad7372b9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,6 +274,9 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPU= Config *cfg) if (cfg->ext_j) { ext |=3D RVJ; } + if (cfg->ext_g) { + ext |=3D RVG; + } =20 return ext; } @@ -293,6 +296,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *= cfg, cfg->ext_u =3D misa_ext & RVU; cfg->ext_h =3D misa_ext & RVH; cfg->ext_j =3D misa_ext & RVJ; + cfg->ext_g =3D misa_ext & RVG; } =20 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2263629332..dbb4df9df0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,6 +82,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') =20 =20 /* Privileged specification version */ --=20 2.39.2