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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679169988939100006 Content-Type: text/plain; charset="utf-8" We can set all RVG related extensions during realize time, before validate_set_extensions() itself. Put it in a separated function so the validate function already uses the updated state. Note that we're adding an extra constraint: ext_zfinx is a blocker for F, which is a requirement to enable G. If zfinx is enabled we'll have to error out. Note that we're setting both cfg->ext_N and env->misa_ext bits, instead of just setting cfg->ext_N. The intention here is to start syncing all misa_ext operations with its cpu->cfg flags, in preparation to allow for the validate function to operate using a misa_ext. This doesn't make any difference for the current code state, but will be a requirement for write_misa() later on. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 66 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 51 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 48ad7372b9..110b52712c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -281,6 +281,42 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCP= UConfig *cfg) return ext; } =20 +static void riscv_cpu_enable_g(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env =3D &cpu->env; + RISCVCPUConfig *cfg =3D &cpu->cfg; + + if (cpu->cfg.ext_zfinx) { + error_setg(errp, "Unable to enable G: Zfinx is enabled, " + "so F can not be enabled"); + return; + } + + if (!(cfg->ext_i && cfg->ext_m && cfg->ext_a && + cfg->ext_f && cfg->ext_d && + cfg->ext_icsr && cfg->ext_ifencei)) { + + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cfg->ext_i =3D true; + env->misa_ext |=3D RVI; + + cfg->ext_m =3D true; + env->misa_ext |=3D RVM; + + cfg->ext_a =3D true; + env->misa_ext |=3D RVA; + + cfg->ext_f =3D true; + env->misa_ext |=3D RVF; + + cfg->ext_d =3D true; + env->misa_ext |=3D RVD; + + cfg->ext_icsr =3D true; + cfg->ext_ifencei =3D true; + } +} + static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, uint32_t misa_ext) { @@ -1036,21 +1072,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) return; } =20 - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i =3D true; - cpu->cfg.ext_m =3D true; - cpu->cfg.ext_a =3D true; - cpu->cfg.ext_f =3D true; - cpu->cfg.ext_d =3D true; - cpu->cfg.ext_icsr =3D true; - cpu->cfg.ext_ifencei =3D true; - } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); @@ -1293,6 +1314,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); + CPURISCVState *env =3D &cpu->env; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1313,6 +1335,20 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + if (cpu->cfg.ext_g) { + riscv_cpu_enable_g(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + /* + * Sync env->misa_ext_mask with the new + * env->misa_ext val. + */ + env->misa_ext_mask =3D env->misa_ext; + } + riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.39.2