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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679170147658100001 Content-Type: text/plain; charset="utf-8" Even after taking RVG off from riscv_cpu_validate_set_extensions(), the function is still doing too much. It is validating misa bits, then validating named extensions, and if the validation succeeds it's doing more changes in both cpu->cfg and MISA bits. It works for the support we have today, since we'll error out during realize() time. This is not enough to support write_misa() though - we don't want to error out if userspace writes something odd in the CSR. This patch starts splitting riscv_cpu_validate_set_extensions() into a three step process: validate misa_ext, validate cpu->cfg, then commit the configuration. This separation will allow us to use these functions in write_misa() without having to worry about saving CPU state during runtime because the function changed state but failed to validate. riscv_cpu_validate_misa_ext() will host all validations related to misa bits only. Validations using misa bits + name extensions will remain in validate_set_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 77 ++++++++++++++++++++++++++-------------------- 1 file changed, 43 insertions(+), 34 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 110b52712c..c7b05d7c4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1025,6 +1025,43 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RIS= CVCPU *cpu) } } =20 +static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) +{ + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers= "); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } +} + static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) { RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); @@ -1072,35 +1109,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers= "); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; @@ -1120,11 +1128,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) return; } =20 - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } - /* The V vector extension depends on the Zve64d extension */ if (cpu->cfg.ext_v) { cpu->cfg.ext_zve64d =3D true; @@ -1349,6 +1352,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) env->misa_ext_mask =3D env->misa_ext; } =20 + riscv_cpu_validate_misa_ext(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.39.2