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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679170115510100001 Content-Type: text/plain; charset="utf-8" In the process of creating the user-facing flags in register_generic_cpu_props() we're also setting default values for the cpu->cfg flags that represents MISA bits. Leaving it as is will cause a discrepancy between users of this function (at this moment the non-named CPUs) and named CPUs. Named CPUs are using set_misa() with a non-zero 'ext' value, writing cpu->cfg in the process. They'll reach riscv_cpu_realize() in a state where env->misa_ext will reflect cpu->cfg, allowing functions to choose whether to use env->misa_ext or cpu->cfg to validate MISA bits. If we guarantee that env->misa_ext will always reflect cpu->cfg at the start of riscv_cpu_realize(), functions will be able to no longer rely on cpu->cfg for MISA validation. This happens to be one blocker we have to properly support write_misa(). Sync env->misa_ext* in register_generic_cpu_props(). After that, there will be no more places where env->misa_ext needs to be sync back with cpu->cfg, so remove the now obsolete code at the end of riscv_cpu_validate_set_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d8f2eca6ca..992edd1735 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1116,14 +1116,10 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *c= pu, Error **errp) =20 /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, setting env->misa_ext and - * misa_ext_mask in the end. + * cpu->cfg accordingly. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { - CPURISCVState *env =3D &cpu->env; - uint32_t ext =3D 0; - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available @@ -1240,10 +1236,6 @@ static void riscv_cpu_validate_set_extensions(RISCVC= PU *cpu, Error **errp) * validated and set everything we need. */ riscv_cpu_disable_priv_spec_isa_exts(cpu); - - ext =3D riscv_get_misa_ext_with_cpucfg(&cpu->cfg); - - env->misa_ext_mask =3D env->misa_ext =3D ext; } =20 #ifndef CONFIG_USER_ONLY @@ -1354,6 +1346,10 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + /* + * This is the last point where env->misa_ext* can + * be changed. + */ if (cpu->cfg.ext_g) { riscv_cpu_enable_g(cpu, &local_err); if (local_err !=3D NULL) { @@ -1631,10 +1627,12 @@ static Property riscv_cpu_extensions[] =3D { * Register generic CPU props with user-facing flags declared * in riscv_cpu_extensions[]. * - * Note that this will overwrite existing values in cpu->cfg. + * Note that this will overwrite existing values in cpu->cfg + * and MISA. */ static void register_generic_cpu_props(Object *obj) { + RISCVCPU *cpu =3D RISCV_CPU(obj); Property *prop; DeviceState *dev =3D DEVICE(obj); =20 @@ -1645,6 +1643,10 @@ static void register_generic_cpu_props(Object *obj) #ifndef CONFIG_USER_ONLY riscv_add_satp_mode_properties(obj); #endif + + /* Keep env->misa_ext and misa_ext_mask updated */ + cpu->env.misa_ext =3D riscv_get_misa_ext_with_cpucfg(&cpu->cfg); + cpu->env.misa_ext_mask =3D cpu->env.misa_ext; } =20 static Property riscv_cpu_properties[] =3D { --=20 2.39.2