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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679170079458100001 Content-Type: text/plain; charset="utf-8" write_misa() is able to use the same validation workflow riscv_cpu_realize() uses. But it's still not capable of updating cpu->cfg misa props yet. We have no way of blocking future (and current) code from checking env->misa_ext (via riscv_has_ext()) or reading cpu->cfg directly, so our best alternative is to keep everything in sync. riscv_cpu_commit_cpu_cfg() now receives an extra 'misa_ext' parameter. If this val is different from the existing env->misa_ext, update env->misa and cpu->cfg with the new value. riscv_cpu_realize() will ignore this code since env->misa_ext isn't touched during validation, but write_misa() will use it to keep cpu->cfg in sync with the new env->misa_ext value. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 16 ++++++++++++++-- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 3 +-- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 67a46504bb..2d2a354af3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1213,8 +1213,20 @@ void riscv_cpu_validate_extensions(RISCVCPU *cpu, ui= nt32_t misa_ext, } } =20 -void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu) +void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu, uint32_t misa_ext) { + CPURISCVState *env =3D &cpu->env; + + /* + * write_misa() needs to update cpu->cfg with the new + * MISA bits. This is a no-op for the riscv_cpu_realize() + * path. + */ + if (env->misa_ext !=3D misa_ext) { + env->misa_ext =3D misa_ext; + riscv_set_cpucfg_with_misa(&cpu->cfg, misa_ext); + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn =3D true; cpu->cfg.ext_zkr =3D true; @@ -1383,7 +1395,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) return; } =20 - riscv_cpu_commit_cpu_cfg(cpu); + riscv_cpu_commit_cpu_cfg(cpu, env->misa_ext); =20 #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ca2ba6a647..befc3b8fff 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -597,7 +597,7 @@ void riscv_cpu_validate_misa_ext(CPURISCVState *env, ui= nt32_t misa_ext, Error **errp); void riscv_cpu_validate_extensions(RISCVCPU *cpu, uint32_t misa_ext, Error **errp); -void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu); +void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu, uint32_t misa_ext); =20 #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8d5e8f9ad1..839862f1a8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1396,7 +1396,7 @@ static RISCVException write_misa(CPURISCVState *env, = int csrno, return RISCV_EXCP_NONE; } =20 - riscv_cpu_commit_cpu_cfg(cpu); + riscv_cpu_commit_cpu_cfg(cpu, val); =20 if (!(val & RVF)) { env->mstatus &=3D ~MSTATUS_FS; @@ -1404,7 +1404,6 @@ static RISCVException write_misa(CPURISCVState *env, = int csrno, =20 /* flush translation cache */ tb_flush(env_cpu(env)); - env->misa_ext =3D val; env->xl =3D riscv_cpu_mxl(env); return RISCV_EXCP_NONE; } --=20 2.39.2