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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1679170063254100007 Content-Type: text/plain; charset="utf-8" Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max !=3D env->misa_mlx. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 51 ++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 17b301967c..1a298e5e55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -879,6 +879,33 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCV= CPU *cpu) } } =20 +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc =3D CPU_CLASS(mcc); + CPURISCVState *env =3D &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max !=3D env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -1180,9 +1207,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) { CPUState *cs =3D CPU(dev); RISCVCPU *cpu =3D RISCV_CPU(dev); - CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); - CPUClass *cc =3D CPU_CLASS(mcc); Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -1197,6 +1222,12 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) return; } =20 + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available @@ -1213,22 +1244,6 @@ static void riscv_cpu_realize(DeviceState *dev, Erro= r **errp) } #endif /* CONFIG_USER_ONLY */ =20 - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file =3D "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file =3D "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - assert(env->misa_mxl_max =3D=3D env->misa_mxl); - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.39.2