This patch series is aimed to add complete support of the
Ingenic MXU extensions of version 1 revision 2.
The serie doesn't split revision 1 and revision 2 of the
MXU ASE as it ought to be, because I have no hardware which
supports revision 1 only. The MXU version 2 is not the subject
of the patch series either.

All added/fixed instructions were tested on real hardware
via set of fuzz tests written for that purpose, although
the tests aren't subject of this patch series.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>

Siarhei Volkau (33):
  target/mips: Add emulation of MXU instructions for 32-bit load/store
  Add support of two XBurst CPUs
  target/mips: Add emulation of LXW LXB LXH LXBU LXHU instructions
  target/mips: Add emulation of S32MADD/MADDU/MSUB/MSUBU instructions
  target/mips: Add emulation of Q8SLT Q8SLTU instructions
  target/mips: fix MXU D16MAX D16MIN Q8MAX Q8MIN instructions
  target/mips: Add emulation of MXU S32SLT D16SLT D16AVG[R] Q8AVG[R]
    insns
  target/mips: Add emulation of Q8ADD instruction
  target/mips: Add emulation of MXU S32CPS D16CPS Q8ABD Q16SAT insns
  target/mips: Add emulation of MXU D16MULF D16MULE instructions
  target/mips: Add emulation of MXU D16MACF D16MACE instructions
  target/mips: Add emulation of MXU D16MADL instruction
  target/mips: Add emulation of MXU S16MAD instruction
  target/mips: Add emulation of MXU Q16ADD instruction
  target/mips: Add emulation of MXU D32ADD instruction
  target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions
  target/mips: Add emulation of MXU D32ADDC instruction
  target/mips: Add emulation of MXU Q16ACC Q16ACCM D16ASUM instructions
  target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC
    instructions
  target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions
  target/mips: Add emulation of MXU S16LDD S16STD S16LDI S16SDI
    instructions
  target/mips: Add emulation of MXU S32MUL S32MULU S32EXTR S32EXTRV
    insns
  target/mips: Add emulation of MXU S32ALN S32LUI insns
  target/mips: Add emulation of MXU D32SARL D32SARW instructions
  target/mips: Add emulation of MXU D32SLL D32SLR D32SAR instructions
  target/mips: Add emulation of MXU Q16SLL Q16SLR Q16SAR instructions
  target/mips: Add emulation of MXU D32/Q16- SLLV/SLRV/SARV instructions
  target/mips: Add emulation of MXU S32/D16/Q8- MOVZ/MOVN instructions
  target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions
  target/mips: Add emulation of MXU Q16SCOP instruction
  target/mips: Add emulation of MXU Q8MADL instruction
  target/mips: Add emulation of MXU S32SFL instruction
  target/mips: Add emulation of MXU Q8SAD instruction

 target/mips/cpu-defs.c.inc      |   46 +
 target/mips/tcg/mxu_translate.c | 3935 +++++++++++++++++++++++++++++--
 target/mips/tcg/translate.c     |    7 +-
 3 files changed, 3787 insertions(+), 201 deletions(-)

-- 
2.40.0

Hi Siarhei,

On 8/6/23 12:41, Siarhei Volkau wrote:
> This patch series is aimed to add complete support of the
> Ingenic MXU extensions of version 1 revision 2.
> The serie doesn't split revision 1 and revision 2 of the
> MXU ASE as it ought to be, because I have no hardware which
> supports revision 1 only. The MXU version 2 is not the subject
> of the patch series either.
> 
> All added/fixed instructions were tested on real hardware
> via set of fuzz tests written for that purpose, although
> the tests aren't subject of this patch series.

Thank you very much for your contribution.
This is a bit unfortunate that you did'nt implemented these
opcode using decodetree.
Also various opcodes are not well optimized, and would benefit
from using the TCG gvec API.
I imagine you have been rebasing that for some years now, so I'm
queuing as is to mips-next.
I hope you can share the tests so your work doesn't bitrot
with time (in particular when a good soul converts it to
decodetree).

Regards,

Phil.

пн, 10 июл. 2023 г. в 22:28, Philippe Mathieu-Daudé <philmd@linaro.org>:
>
> Hi Siarhei,
>
> On 8/6/23 12:41, Siarhei Volkau wrote:
> > This patch series is aimed to add complete support of the
> > Ingenic MXU extensions of version 1 revision 2.
> > The serie doesn't split revision 1 and revision 2 of the
> > MXU ASE as it ought to be, because I have no hardware which
> > supports revision 1 only. The MXU version 2 is not the subject
> > of the patch series either.
> >
> > All added/fixed instructions were tested on real hardware
> > via set of fuzz tests written for that purpose, although
> > the tests aren't subject of this patch series.
>
> Thank you very much for your contribution.
> This is a bit unfortunate that you did'nt implemented these
> opcode using decodetree.
> Also various opcodes are not well optimized, and would benefit
> from using the TCG gvec API.
> I imagine you have been rebasing that for some years now, so I'm
> queuing as is to mips-next.

Thanks so much for applying, Phil.
Unfortunately I have little expertise in the QEMU internals,
so, I just improved what was already here.

> I hope you can share the tests so your work doesn't bitrot
> with time (in particular when a good soul converts it to
> decodetree).

Here they are: https://github.com/SiarheiVolkau/mxu-tests.

BR,
Siarhei