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[176.184.10.225]) by smtp.gmail.com with ESMTPSA id w21-20020a1cf615000000b003f8126bcf34sm11050081wmc.48.2023.06.19.08.45.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 19 Jun 2023 08:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687189549; x=1689781549; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QJlkFGEL6RfrhNZjrerQLlrb1SfygyFO83NewYAdusE=; b=dG9Z/yU2e4/4bxI2ADoeRNEpNRIuzQBhDf5iCFKoNA92TfjgV3QuGLQjwKochpZTkR cSMEBeRdAYzmyWZO9x68NCYmJnrdkuU9xyQ347Jk33tYVmfEK1IDzP7JBHvcsu2LLjof t0A+n9tphxwVSs5FSNUGYMoy9WZfpalj4jfvieW8M16Etcnt386z6v/uxWpvCbHL5FXn n6p1/nHTrpd/Ix+0MMDh0/d3uf9mWRGRBltq5DJkSIPOxPdSU9DiHQI4sPprZEzdPf3o sY1NzyflG/1epWh7H3M3RwWKkM+43T82Dl/EtUZFTmkebqcRZfUdGIR+BBCjxv3cZXfT wIog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687189549; x=1689781549; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QJlkFGEL6RfrhNZjrerQLlrb1SfygyFO83NewYAdusE=; b=FpG2IzsU0ls1jAWjpHdZyZn0J1V5WOvYQco02AomfNEYnGBk9QISrKdqCxYOV5hqMj fIOzRkdrYWhJY4KFNdErC6WgRKTgwzW/lUeqggkG/48tzKgGcIg+x4SnF5gFBHs3SV+I 30D+Cxekxmurq5ttgZSGodRPQh/ubGRDLz8VF5AxID+0VOD9Ads+lNjtpRvTz98CJX2U xEqs73VQAeR6q247aoHiKmomr7lCcdmLRRkicHyQ61xLFEQSVHB0BeCLywa1CwI4OWuU pr6aEWvNYkAfd9IrpdG//VQoW8WVuYQIHVfx8AEnW10ws3uOHBYa33wgzGRVBNOhqPF/ Yj2w== X-Gm-Message-State: AC+VfDxDAOzS56PH3Nu9KJ0RE6txD8A624XdpxlDeQuKJcc+5ZDrydnZ 3Cg0mFOjd2urRnha/M3jHCM2Pxe8ZCRGcFJOU8/B8Q== X-Google-Smtp-Source: ACHHUZ4AKy9xorEkkkuhYEvBM+kTvGl0vtQQFrNhLPR/BDrO1C+4C0WuQaPcalQu6UxIC1oc4XC85Q== X-Received: by 2002:a05:6512:471:b0:4f8:578f:acf1 with SMTP id x17-20020a056512047100b004f8578facf1mr4641484lfd.46.1687189548691; Mon, 19 Jun 2023 08:45:48 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 12/34] target/arm/tcg: Move NEON helpers to neon_helper.c Date: Mon, 19 Jun 2023 17:42:40 +0200 Message-Id: <20230619154302.80350-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230619154302.80350-1-philmd@linaro.org> References: <20230619154302.80350-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=philmd@linaro.org; helo=mail-lf1-x12a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687189586408100003 Move various NEON helpers to the well named neon_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/tcg/helper-a64.c | 80 -------------------------- target/arm/tcg/neon_helper.c | 106 +++++++++++++++++++++++++++++++++++ target/arm/tcg/op_helper.c | 22 -------- 3 files changed, 106 insertions(+), 102 deletions(-) diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index c43f22e7d4..6312238676 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -93,25 +93,6 @@ void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t = imm) arm_rebuild_hflags(env); } =20 -/* 64bit/double versions of the neon float compare functions */ -uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) -{ - float_status *fpst =3D fpstp; - return -float64_eq_quiet(a, b, fpst); -} - -uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp) -{ - float_status *fpst =3D fpstp; - return -float64_le(b, a, fpst); -} - -uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) -{ - float_status *fpst =3D fpstp; - return -float64_lt(b, a, fpst); -} - /* Reciprocal step and sqrt step. Note that unlike the A32/T32 * versions, these do a fully fused multiply-add or * multiply-add-and-halve. @@ -207,67 +188,6 @@ float64 HELPER(rsqrtsf_f64)(float64 a, float64 b, void= *fpstp) return float64_muladd(a, b, float64_three, float_muladd_halve_result, = fpst); } =20 -/* Pairwise long add: add pairs of adjacent elements into - * double-width elements in the result (eg _s8 is an 8x8->16 op) - */ -uint64_t HELPER(neon_addlp_s8)(uint64_t a) -{ - uint64_t nsignmask =3D 0x0080008000800080ULL; - uint64_t wsignmask =3D 0x8000800080008000ULL; - uint64_t elementmask =3D 0x00ff00ff00ff00ffULL; - uint64_t tmp1, tmp2; - uint64_t res, signres; - - /* Extract odd elements, sign extend each to a 16 bit field */ - tmp1 =3D a & elementmask; - tmp1 ^=3D nsignmask; - tmp1 |=3D wsignmask; - tmp1 =3D (tmp1 - nsignmask) ^ wsignmask; - /* Ditto for the even elements */ - tmp2 =3D (a >> 8) & elementmask; - tmp2 ^=3D nsignmask; - tmp2 |=3D wsignmask; - tmp2 =3D (tmp2 - nsignmask) ^ wsignmask; - - /* calculate the result by summing bits 0..14, 16..22, etc, - * and then adjusting the sign bits 15, 23, etc manually. - * This ensures the addition can't overflow the 16 bit field. - */ - signres =3D (tmp1 ^ tmp2) & wsignmask; - res =3D (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask); - res ^=3D signres; - - return res; -} - -uint64_t HELPER(neon_addlp_u8)(uint64_t a) -{ - uint64_t tmp; - - tmp =3D a & 0x00ff00ff00ff00ffULL; - tmp +=3D (a >> 8) & 0x00ff00ff00ff00ffULL; - return tmp; -} - -uint64_t HELPER(neon_addlp_s16)(uint64_t a) -{ - int32_t reslo, reshi; - - reslo =3D (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16); - reshi =3D (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48); - - return (uint32_t)reslo | (((uint64_t)reshi) << 32); -} - -uint64_t HELPER(neon_addlp_u16)(uint64_t a) -{ - uint64_t tmp; - - tmp =3D a & 0x0000ffff0000ffffULL; - tmp +=3D (a >> 16) & 0x0000ffff0000ffffULL; - return tmp; -} - /* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp) { diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index bc6c4a54e9..cd668eb43a 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -1738,3 +1738,109 @@ void HELPER(neon_zip16)(void *vd, void *vm) rm[0] =3D m0; rd[0] =3D d0; } + +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, + uint64_t ireg, uint64_t def) +{ + uint64_t tmp, val =3D 0; + uint32_t maxindex =3D ((desc & 3) + 1) * 8; + uint32_t base_reg =3D desc >> 2; + uint32_t shift, index, reg; + + for (shift =3D 0; shift < 64; shift +=3D 8) { + index =3D (ireg >> shift) & 0xff; + if (index < maxindex) { + reg =3D base_reg + (index >> 3); + tmp =3D *aa32_vfp_dreg(env, reg); + tmp =3D ((tmp >> ((index & 7) << 3)) & 0xff) << shift; + } else { + tmp =3D def & (0xffull << shift); + } + val |=3D tmp; + } + return val; +} + +#ifdef TARGET_AARCH64 + +/* Pairwise long add: add pairs of adjacent elements into + * double-width elements in the result (eg _s8 is an 8x8->16 op) + */ +uint64_t HELPER(neon_addlp_s8)(uint64_t a) +{ + uint64_t nsignmask =3D 0x0080008000800080ULL; + uint64_t wsignmask =3D 0x8000800080008000ULL; + uint64_t elementmask =3D 0x00ff00ff00ff00ffULL; + uint64_t tmp1, tmp2; + uint64_t res, signres; + + /* Extract odd elements, sign extend each to a 16 bit field */ + tmp1 =3D a & elementmask; + tmp1 ^=3D nsignmask; + tmp1 |=3D wsignmask; + tmp1 =3D (tmp1 - nsignmask) ^ wsignmask; + /* Ditto for the even elements */ + tmp2 =3D (a >> 8) & elementmask; + tmp2 ^=3D nsignmask; + tmp2 |=3D wsignmask; + tmp2 =3D (tmp2 - nsignmask) ^ wsignmask; + + /* calculate the result by summing bits 0..14, 16..22, etc, + * and then adjusting the sign bits 15, 23, etc manually. + * This ensures the addition can't overflow the 16 bit field. + */ + signres =3D (tmp1 ^ tmp2) & wsignmask; + res =3D (tmp1 & ~wsignmask) + (tmp2 & ~wsignmask); + res ^=3D signres; + + return res; +} + +uint64_t HELPER(neon_addlp_u8)(uint64_t a) +{ + uint64_t tmp; + + tmp =3D a & 0x00ff00ff00ff00ffULL; + tmp +=3D (a >> 8) & 0x00ff00ff00ff00ffULL; + return tmp; +} + +uint64_t HELPER(neon_addlp_s16)(uint64_t a) +{ + int32_t reslo, reshi; + + reslo =3D (int32_t)(int16_t)a + (int32_t)(int16_t)(a >> 16); + reshi =3D (int32_t)(int16_t)(a >> 32) + (int32_t)(int16_t)(a >> 48); + + return (uint32_t)reslo | (((uint64_t)reshi) << 32); +} + +uint64_t HELPER(neon_addlp_u16)(uint64_t a) +{ + uint64_t tmp; + + tmp =3D a & 0x0000ffff0000ffffULL; + tmp +=3D (a >> 16) & 0x0000ffff0000ffffULL; + return tmp; +} + +/* 64bit/double versions of the neon float compare functions */ +uint64_t HELPER(neon_ceq_f64)(float64 a, float64 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + return -float64_eq_quiet(a, b, fpst); +} + +uint64_t HELPER(neon_cge_f64)(float64 a, float64 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + return -float64_le(b, a, fpst); +} + +uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp) +{ + float_status *fpst =3D fpstp; + return -float64_lt(b, a, fpst); +} + +#endif /* TARGET_AARCH64 */ diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 3baf8004f6..70a9c37b74 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -82,28 +82,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp,= uint32_t syndrome, raise_exception(env, excp, syndrome, target_el); } =20 -uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, - uint64_t ireg, uint64_t def) -{ - uint64_t tmp, val =3D 0; - uint32_t maxindex =3D ((desc & 3) + 1) * 8; - uint32_t base_reg =3D desc >> 2; - uint32_t shift, index, reg; - - for (shift =3D 0; shift < 64; shift +=3D 8) { - index =3D (ireg >> shift) & 0xff; - if (index < maxindex) { - reg =3D base_reg + (index >> 3); - tmp =3D *aa32_vfp_dreg(env, reg); - tmp =3D ((tmp >> ((index & 7) << 3)) & 0xff) << shift; - } else { - tmp =3D def & (0xffull << shift); - } - val |=3D tmp; - } - return val; -} - void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) { /* --=20 2.38.1