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Tue, 20 Jun 2023 05:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 18/20] target/arm: Implement GPC exceptions Date: Tue, 20 Jun 2023 14:44:16 +0200 Message-Id: <20230620124418.805717-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230620124418.805717-1-richard.henderson@linaro.org> References: <20230620124418.805717-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1687265198806100005 Content-Type: text/plain; charset="utf-8" Handle GPC Fault types in arm_deliver_fault, reporting as either a GPC exception at EL3, or falling through to insn or data aborts at various exception levels. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 27 +++++++++++ target/arm/helper.c | 5 ++ target/arm/tcg/tlb_helper.c | 96 +++++++++++++++++++++++++++++++++++-- 4 files changed, 126 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 590216b855..11c3850ad9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -57,6 +57,7 @@ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ #define EXCP_VSERR 24 +#define EXCP_GPC 25 /* v9 Granule Protection Check Fault */ /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 diff --git a/target/arm/internals.h b/target/arm/internals.h index e3029bdc37..0f01bc32a8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -358,14 +358,27 @@ typedef enum ARMFaultType { ARMFault_ICacheMaint, ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */ ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */ + ARMFault_GPCFOnWalk, + ARMFault_GPCFOnOutput, } ARMFaultType; =20 +typedef enum ARMGPCF { + GPCF_None, + GPCF_AddressSize, + GPCF_Walk, + GPCF_EABT, + GPCF_Fail, +} ARMGPCF; + /** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @type: Type of fault + * @gpcf: Subtype of ARMFault_GPCFOn{Walk,Output}. * @level: Table walk level (for translation, access flag and permission f= aults) * @domain: Domain of the fault address (for non-LPAE CPUs only) * @s2addr: Address that caused a fault at stage 2 + * @paddr: physical address that caused a fault for gpc + * @paddr_space: physical address space that caused a fault for gpc * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table = walk * @s1ns: True if we faulted on a non-secure IPA while in secure state @@ -374,7 +387,10 @@ typedef enum ARMFaultType { typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { ARMFaultType type; + ARMGPCF gpcf; target_ulong s2addr; + target_ulong paddr; + ARMSecuritySpace paddr_space; int level; int domain; bool stage2; @@ -548,6 +564,17 @@ static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo = *fi) case ARMFault_Exclusive: fsc =3D 0x35; break; + case ARMFault_GPCFOnWalk: + assert(fi->level >=3D -1 && fi->level <=3D 3); + if (fi->level < 0) { + fsc =3D 0b100011; + } else { + fsc =3D 0b100100 | fi->level; + } + break; + case ARMFault_GPCFOnOutput: + fsc =3D 0b101000; + break; default: /* Other faults can't occur in a context that requires a * long-format status code. diff --git a/target/arm/helper.c b/target/arm/helper.c index f68923d73b..323cadd3c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10184,6 +10184,7 @@ void arm_log_exception(CPUState *cs) [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", [EXCP_VSERR] =3D "Virtual SERR", + [EXCP_GPC] =3D "Granule Protection Check", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -10915,6 +10916,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) } =20 switch (cs->exception_index) { + case EXCP_GPC: + qemu_log_mask(CPU_LOG_INT, "...with MFAR 0x%" PRIx64 "\n", + env->cp15.mfar_el3); + /* fall through */ case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: /* diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 8df36c2cbf..b22b2a4c6e 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -107,17 +107,106 @@ static uint32_t compute_fsr_fsc(CPUARMState *env, AR= MMMUFaultInfo *fi, return fsr; } =20 +static bool report_as_gpc_exception(ARMCPU *cpu, int current_el, + ARMMMUFaultInfo *fi) +{ + bool ret; + + switch (fi->gpcf) { + case GPCF_None: + return false; + case GPCF_AddressSize: + case GPCF_Walk: + case GPCF_EABT: + /* R_PYTGX: GPT faults are reported as GPC. */ + ret =3D true; + break; + case GPCF_Fail: + /* + * R_BLYPM: A GPF at EL3 is reported as insn or data abort. + * R_VBZMW, R_LXHQR: A GPF at EL[0-2] is reported as a GPC + * if SCR_EL3.GPF is set, otherwise an insn or data abort. + */ + ret =3D (cpu->env.cp15.scr_el3 & SCR_GPF) && current_el !=3D 3; + break; + default: + g_assert_not_reached(); + } + + assert(cpu_isar_feature(aa64_rme, cpu)); + assert(fi->type =3D=3D ARMFault_GPCFOnWalk || + fi->type =3D=3D ARMFault_GPCFOnOutput); + if (fi->gpcf =3D=3D GPCF_AddressSize) { + assert(fi->level =3D=3D 0); + } else { + assert(fi->level >=3D 0 && fi->level <=3D 1); + } + + return ret; +} + +static unsigned encode_gpcsc(ARMMMUFaultInfo *fi) +{ + static uint8_t const gpcsc[] =3D { + [GPCF_AddressSize] =3D 0b000000, + [GPCF_Walk] =3D 0b000100, + [GPCF_Fail] =3D 0b001100, + [GPCF_EABT] =3D 0b010100, + }; + + /* Note that we've validated fi->gpcf and fi->level above. */ + return gpcsc[fi->gpcf] | fi->level; +} + static G_NORETURN void arm_deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; - int target_el; + int target_el =3D exception_target_el(env); + int current_el =3D arm_current_el(env); bool same_el; uint32_t syn, exc, fsr, fsc; =20 - target_el =3D exception_target_el(env); + if (report_as_gpc_exception(cpu, current_el, fi)) { + target_el =3D 3; + + fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); + + syn =3D syn_gpc(fi->stage2 && fi->type =3D=3D ARMFault_GPCFOnWalk, + access_type =3D=3D MMU_INST_FETCH, + encode_gpcsc(fi), 0, fi->s1ptw, + access_type =3D=3D MMU_DATA_STORE, fsc); + + env->cp15.mfar_el3 =3D fi->paddr; + switch (fi->paddr_space) { + case ARMSS_Secure: + break; + case ARMSS_NonSecure: + env->cp15.mfar_el3 |=3D R_MFAR_NS_MASK; + break; + case ARMSS_Root: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK; + break; + case ARMSS_Realm: + env->cp15.mfar_el3 |=3D R_MFAR_NSE_MASK | R_MFAR_NS_MASK; + break; + default: + g_assert_not_reached(); + } + + exc =3D EXCP_GPC; + goto do_raise; + } + + /* If SCR_EL3.GPF is unset, GPF may still be routed to EL2. */ + if (fi->gpcf =3D=3D GPCF_Fail && target_el < 2) { + if (arm_hcr_el2_eff(env) & HCR_GPF) { + target_el =3D 2; + } + } + if (fi->stage2) { target_el =3D 2; env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; @@ -125,8 +214,8 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |=3D HPFAR_NS; } } - same_el =3D (arm_current_el(env) =3D=3D target_el); =20 + same_el =3D current_el =3D=3D target_el; fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); =20 if (access_type =3D=3D MMU_INST_FETCH) { @@ -143,6 +232,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, exc =3D EXCP_DATA_ABORT; } =20 + do_raise: env->exception.vaddress =3D addr; env->exception.fsr =3D fsr; raise_exception(env, exc, syn, target_el); --=20 2.34.1