From nobody Wed Jan 14 04:23:48 2026 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1695116145; cv=none; d=zohomail.com; s=zohoarc; b=gDuaiRMWjORHOC8yTOEI02zzX4Tr/wacFHT4vIrMP5fJ2YdtLf99ZjA418M29mCUyeIHZAxjpxe1Zf2Tf5hYwjJR7CYpn9FY3Bg9nMVObkCBeddSodqJYxrl/q/aaFNQ5isTNzJkc2NIdb/Z4WILri8cPQldmh+eGx6HGah3eEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1695116145; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Hy7rkCsOAs/sZ50u+iAGur1ndtorsRHTicmSIYZexEA=; b=RUr8mPgFNAWZ1mPx0O0rCG/ZonwbgTVoXJ3p3KVaaoUhmeWr2K0fkSNdbbBpHWPOQh1Q5b+TLbrbb/j0IG7Z9vFKDP7kdM5kzgR+R6/Q7RJtFKPdWCGmbKQJ0YMg1/MnG+AfB+wAx7zv7dmhP0c/24PHValIASKYq3Y5woC1pSI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1695116145876123.75209173371582; Tue, 19 Sep 2023 02:35:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qiX8w-0003UK-MF; Tue, 19 Sep 2023 05:35:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qiX8t-0003F8-IC for qemu-devel@nongnu.org; Tue, 19 Sep 2023 05:35:39 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qiX8r-0004YQ-Q1 for qemu-devel@nongnu.org; Tue, 19 Sep 2023 05:35:39 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Rqc2D2ZbWz6K64p; Tue, 19 Sep 2023 17:34:44 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 19 Sep 2023 10:35:35 +0100 To: Michael Tokarev , , Michael Tsirkin , Fan Ni , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= CC: Subject: [PATCH v3 2/4] hw/cxl: Use switch statements for read and write of cachemem registers Date: Tue, 19 Sep 2023 10:34:32 +0100 Message-ID: <20230919093434.1194-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230919093434.1194-1-Jonathan.Cameron@huawei.com> References: <20230919093434.1194-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100004.china.huawei.com (7.191.162.219) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1695116147013100003 Content-Type: text/plain; charset="utf-8" Establishing that only register accesses of size 4 and 8 can occur using these functions requires looking at their callers. Make it easier to see that by using switch statements. Assertions are used to enforce that the register storage is of the matching size, allowing fixed values to be used for divisors of the array indices. Suggested-by: Michael Tokarev Signed-off-by: Jonathan Cameron Reviewed-by: Fan Ni --- hw/cxl/cxl-component-utils.c | 65 +++++++++++++++++++++++------------- 1 file changed, 42 insertions(+), 23 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index f3bbf0fd13..7ef3ef2bd6 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -67,16 +67,24 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hw= addr offset, CXLComponentState *cxl_cstate =3D opaque; ComponentRegisters *cregs =3D &cxl_cstate->crb; =20 - if (size =3D=3D 8) { + switch (size) { + case 4: + if (cregs->special_ops && cregs->special_ops->read) { + return cregs->special_ops->read(cxl_cstate, offset, 4); + } else { + static_assert(sizeof(*cregs->cache_mem_registers) =3D=3D 4); + return cregs->cache_mem_registers[offset / 4]; + } + case 8: qemu_log_mask(LOG_UNIMP, "CXL 8 byte cache mem registers not implemented\n"); return 0; - } - - if (cregs->special_ops && cregs->special_ops->read) { - return cregs->special_ops->read(cxl_cstate, offset, size); - } else { - return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_me= m_registers)]; + default: + /* + * In line with specifiction limitaions on access sizes, this + * routine is not called with other sizes. + */ + g_assert_not_reached(); } } =20 @@ -117,25 +125,36 @@ static void cxl_cache_mem_write_reg(void *opaque, hwa= ddr offset, uint64_t value, ComponentRegisters *cregs =3D &cxl_cstate->crb; uint32_t mask; =20 - if (size =3D=3D 8) { + switch (size) { + case 4: + static_assert(sizeof(*cregs->cache_mem_regs_write_mask) =3D=3D 4); + static_assert(sizeof(*cregs->cache_mem_registers) =3D=3D 4); + mask =3D cregs->cache_mem_regs_write_mask[offset / 4]; + value &=3D mask; + /* RO bits should remain constant. Done by reading existing value = */ + value |=3D ~mask & cregs->cache_mem_registers[offset / 4]; + if (cregs->special_ops && cregs->special_ops->write) { + cregs->special_ops->write(cxl_cstate, offset, value, size); + return; + } + + if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && + offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { + dumb_hdm_handler(cxl_cstate, offset, value); + } else { + cregs->cache_mem_registers[offset / 4] =3D value; + } + return; + case 8: qemu_log_mask(LOG_UNIMP, "CXL 8 byte cache mem registers not implemented\n"); return; - } - mask =3D cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cach= e_mem_regs_write_mask)]; - value &=3D mask; - /* RO bits should remain constant. Done by reading existing value */ - value |=3D ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->= cache_mem_registers)]; - if (cregs->special_ops && cregs->special_ops->write) { - cregs->special_ops->write(cxl_cstate, offset, value, size); - return; - } - - if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && - offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { - dumb_hdm_handler(cxl_cstate, offset, value); - } else { - cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_regis= ters)] =3D value; + default: + /* + * In line with specifiction limitaions on access sizes, this + * routine is not called with other sizes. + */ + g_assert_not_reached(); } } =20 --=20 2.39.2