Based-on: 20230920112020.651006-1-dbarboza@ventanamicro.com
("[PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c")

Hi,

The parent series is in a more stable state so I decided to go ahead
and post this work.

This series implements query-cpu-model-expansion for RISC-V. The
implementation was based on the ARM version of the same API in
target/arm/arm-qmp-cmds.c.

A couple of changes were made in the first 3 patches. The most impactful
is in patch 2, where we're now exposing extension properties for vendor
CPUs. This was done to allow the API to retrieve the extension state for
those CPUs, which were otherwise hidden inside cpu->cfg. The result is
that users will have a little more power because we're now allowing
vendor CPU extensions to be disabled. Enabling extensions for those CPUs
is still forbidden. Patch 2 commit msg gives more details on what is now
possible to do.

The first 3 patches can be pushed/merged separately from the API since
they can stand on their own.

A small tweak in the extension validation in the TCG driver was also
needed. We're now centralizing all extension validation in
finalize_features(), and exporting finalize_features() to be usable by
the new API. This will allow us to validate model properties and report
back if the desired model is valid or not.

This series can be tested directly using this branch:

https://gitlab.com/danielhb/qemu/-/tree/qmp-cpu-expansion_v1


Here's an usage example. Launch QEMU with "-S" to be able to issue QMP
query commands before the machine starts:

$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp  tcp:localhost:1234,server,wait=off

Then use QMP to access the API:

$ ./scripts/qmp/qmp-shell localhost:1234
Welcome to the QMP low-level shell!
Connected to QEMU 8.1.50

(QEMU)  query-cpu-model-expansion type=full model={"name":"rv64"}
{"return": {"model": {"name": "rv64", "props": {"zicond": false, "x-zvfh": false, "mmu": true, "x-zvfbfwma": false, "x-zvfbfmin": false, "xtheadbs": false, "xtheadbb": false, "xtheadba": false, "xtheadmemidx": false, "smstateen": false, "zfinx": false, "Zve64f": false, "Zve32f": false, "x-zvfhmin": false, "xventanacondops": false, "xtheadcondmov": false, "svpbmt": false, "zbs": true, "zbc": true, "zbb": true, "zba": true, "zicboz": true, "xtheadmac": false, "Zfh": false, "Zfa": true, "zbkx": false, "zbkc": false, "zbkb": false, "Zve64d": false, "x-zfbfmin": false, "zk": false, "x-epmp": false, "xtheadmempair": false, "zkt": false, "zks": false, "zkr": false, "zkn": false, "Zfhmin": false, "zksh": false, "zknh": false, "zkne": false, "zknd": false, "zhinx": false, "Zicsr": true, "sscofpmf": false, "Zihintntl": true, "sstc": true, "xtheadcmo": false, "x-zvbb": false, "zksed": false, "x-zvkned": false, "xtheadsync": false, "x-zvkg": false, "zhinxmin": false, "svadu": true, "xtheadfmv": false, "x-zvksed": false, "svnapot": false, "pmp": true, "x-zvknhb": false, "x-zvknha": false, "xtheadfmemidx": false, "x-zvksh": false, "zdinx": false, "zicbom": true, "Zihintpause": true, "svinval": false, "zcf": false, "zce": false, "zcd": false, "zcb": false, "zca": false, "x-ssaia": false, "x-smaia": false, "zmmul": false, "x-zvbc": false, "Zifencei": true, "zcmt": false, "zcmp": false, "Zawrs": true}}}}



Daniel Henrique Barboza (8):
  target/riscv: add riscv_cpu_get_name()
  target/riscv/tcg-cpu.c: add extension properties for all cpus
  target/riscv/kvm/kvm-cpu.c: add missing property getters()
  qapi,risc-v: add query-cpu-model-expansion
  target/riscv/tcg: add tcg_cpu_finalize_features()
  target/riscv: handle custom props in qmp_query_cpu_model_expansion
  target/riscv: add riscv_cpu_accelerator_compatible()
  target/riscv/riscv-qmp-cmds.c: check CPU accel in
    query-cpu-model-expansion

 qapi/machine-target.json      |   6 +-
 target/riscv/cpu.c            |  38 +++++++-
 target/riscv/cpu.h            |   3 +
 target/riscv/kvm/kvm-cpu.c    |  40 ++++++++-
 target/riscv/riscv-qmp-cmds.c | 160 ++++++++++++++++++++++++++++++++++
 target/riscv/tcg/tcg-cpu.c    | 122 ++++++++++++++++++--------
 target/riscv/tcg/tcg-cpu.h    |   2 +
 7 files changed, 327 insertions(+), 44 deletions(-)

-- 
2.41.0

Hi,

I'll split patches 1 and 2 and send those standalone. First because they
can stand on its own. Second because patch 2 in particular is going to be
a prerequisite for the profile support work.


Thanks,

Daniel


On 9/20/23 18:37, Daniel Henrique Barboza wrote:
> Based-on: 20230920112020.651006-1-dbarboza@ventanamicro.com
> ("[PATCH v3 00/19] riscv: split TCG/KVM accelerators from cpu.c")
> 
> Hi,
> 
> The parent series is in a more stable state so I decided to go ahead
> and post this work.
> 
> This series implements query-cpu-model-expansion for RISC-V. The
> implementation was based on the ARM version of the same API in
> target/arm/arm-qmp-cmds.c.
> 
> A couple of changes were made in the first 3 patches. The most impactful
> is in patch 2, where we're now exposing extension properties for vendor
> CPUs. This was done to allow the API to retrieve the extension state for
> those CPUs, which were otherwise hidden inside cpu->cfg. The result is
> that users will have a little more power because we're now allowing
> vendor CPU extensions to be disabled. Enabling extensions for those CPUs
> is still forbidden. Patch 2 commit msg gives more details on what is now
> possible to do.
> 
> The first 3 patches can be pushed/merged separately from the API since
> they can stand on their own.
> 
> A small tweak in the extension validation in the TCG driver was also
> needed. We're now centralizing all extension validation in
> finalize_features(), and exporting finalize_features() to be usable by
> the new API. This will allow us to validate model properties and report
> back if the desired model is valid or not.
> 
> This series can be tested directly using this branch:
> 
> https://gitlab.com/danielhb/qemu/-/tree/qmp-cpu-expansion_v1
> 
> 
> Here's an usage example. Launch QEMU with "-S" to be able to issue QMP
> query commands before the machine starts:
> 
> $ ./build/qemu-system-riscv64 -S -M virt -display none -qmp  tcp:localhost:1234,server,wait=off
> 
> Then use QMP to access the API:
> 
> $ ./scripts/qmp/qmp-shell localhost:1234
> Welcome to the QMP low-level shell!
> Connected to QEMU 8.1.50
> 
> (QEMU)  query-cpu-model-expansion type=full model={"name":"rv64"}
> {"return": {"model": {"name": "rv64", "props": {"zicond": false, "x-zvfh": false, "mmu": true, "x-zvfbfwma": false, "x-zvfbfmin": false, "xtheadbs": false, "xtheadbb": false, "xtheadba": false, "xtheadmemidx": false, "smstateen": false, "zfinx": false, "Zve64f": false, "Zve32f": false, "x-zvfhmin": false, "xventanacondops": false, "xtheadcondmov": false, "svpbmt": false, "zbs": true, "zbc": true, "zbb": true, "zba": true, "zicboz": true, "xtheadmac": false, "Zfh": false, "Zfa": true, "zbkx": false, "zbkc": false, "zbkb": false, "Zve64d": false, "x-zfbfmin": false, "zk": false, "x-epmp": false, "xtheadmempair": false, "zkt": false, "zks": false, "zkr": false, "zkn": false, "Zfhmin": false, "zksh": false, "zknh": false, "zkne": false, "zknd": false, "zhinx": false, "Zicsr": true, "sscofpmf": false, "Zihintntl": true, "sstc": true, "xtheadcmo": false, "x-zvbb": false, "zksed": false, "x-zvkned": false, "xtheadsync": false, "x-zvkg": false, "zhinxmin": false, "svadu": true, "xtheadfmv": false, "x-zvksed": false, "svnapot": false, "pmp": true, "x-zvknhb": false, "x-zvknha": false, "xtheadfmemidx": false, "x-zvksh": false, "zdinx": false, "zicbom": true, "Zihintpause": true, "svinval": false, "zcf": false, "zce": false, "zcd": false, "zcb": false, "zca": false, "x-ssaia": false, "x-smaia": false, "zmmul": false, "x-zvbc": false, "Zifencei": true, "zcmt": false, "zcmp": false, "Zawrs": true}}}}
> 
> 
> 
> Daniel Henrique Barboza (8):
>    target/riscv: add riscv_cpu_get_name()
>    target/riscv/tcg-cpu.c: add extension properties for all cpus
>    target/riscv/kvm/kvm-cpu.c: add missing property getters()
>    qapi,risc-v: add query-cpu-model-expansion
>    target/riscv/tcg: add tcg_cpu_finalize_features()
>    target/riscv: handle custom props in qmp_query_cpu_model_expansion
>    target/riscv: add riscv_cpu_accelerator_compatible()
>    target/riscv/riscv-qmp-cmds.c: check CPU accel in
>      query-cpu-model-expansion
> 
>   qapi/machine-target.json      |   6 +-
>   target/riscv/cpu.c            |  38 +++++++-
>   target/riscv/cpu.h            |   3 +
>   target/riscv/kvm/kvm-cpu.c    |  40 ++++++++-
>   target/riscv/riscv-qmp-cmds.c | 160 ++++++++++++++++++++++++++++++++++
>   target/riscv/tcg/tcg-cpu.c    | 122 ++++++++++++++++++--------
>   target/riscv/tcg/tcg-cpu.h    |   2 +
>   7 files changed, 327 insertions(+), 44 deletions(-)
>