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Wed, 18 Oct 2023 12:56:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH v3 2/6] qapi,risc-v: add query-cpu-model-expansion Date: Wed, 18 Oct 2023 16:56:34 -0300 Message-ID: <20231018195638.211151-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018195638.211151-1-dbarboza@ventanamicro.com> References: <20231018195638.211151-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1697659090906100001 Content-Type: text/plain; charset="utf-8" This API is used to inspect the characteristics of a given CPU model. It also allows users to validate a CPU model with a certain configuration, e.g. if "-cpu X,a=3Dtrue,b=3Dfalse" is a valid setup for a given QEMU binary. We'll start implementing the first part. The second requires more changes in RISC-V CPU boot flow. The implementation is inspired by the existing ARM query-cpu-model-expansion impl in target/arm/arm-qmp-cmds.c. We'll create a RISCVCPU object with the required model, fetch its existing properties, add a couple of relevant boolean options (pmp and mmu) and display it to users. Here's an usage example: ./build/qemu-system-riscv64 -S -M virt -display none \ -qmp tcp:localhost:1234,server,wait=3Doff ./scripts/qmp/qmp-shell localhost:1234 Welcome to the QMP low-level shell! Connected to QEMU 8.1.50 (QEMU) query-cpu-model-expansion type=3Dfull model=3D{"name":"rv64"} {"return": {"model": {"name": "rv64", "props": {"zicond": false, "x-zvfh": = false, "mmu": true, "x-zvfbfwma": false, "x-zvfbfmin": false, "xtheadbs": f= alse, "xtheadbb": false, "xtheadba": false, "xtheadmemidx": false, "smstate= en": false, "zfinx": false, "Zve64f": false, "Zve32f": false, "x-zvfhmin": = false, "xventanacondops": false, "xtheadcondmov": false, "svpbmt": false, "= zbs": true, "zbc": true, "zbb": true, "zba": true, "zicboz": true, "xtheadm= ac": false, "Zfh": false, "Zfa": true, "zbkx": false, "zbkc": false, "zbkb"= : false, "Zve64d": false, "x-zfbfmin": false, "zk": false, "x-epmp": false,= "xtheadmempair": false, "zkt": false, "zks": false, "zkr": false, "zkn": f= alse, "Zfhmin": false, "zksh": false, "zknh": false, "zkne": false, "zknd":= false, "zhinx": false, "Zicsr": true, "sscofpmf": false, "Zihintntl": true= , "sstc": true, "xtheadcmo": false, "x-zvbb": false, "zksed": false, "x-zvk= ned": false, "xtheadsync": false, "x-zvkg": false, "zhinxmin": false, "svad= u": true, "xtheadfmv": false, "x-zvksed": false, "svnapot": false, "pmp": t= rue, "x-zvknhb": false, "x-zvknha": false, "xtheadfmemidx": false, "x-zvksh= ": false, "zdinx": false, "zicbom": true, "Zihintpause": true, "svinval": f= alse, "zcf": false, "zce": false, "zcd": false, "zcb": false, "zca": false,= "x-ssaia": false, "x-smaia": false, "zmmul": false, "x-zvbc": false, "Zife= ncei": true, "zcmt": false, "zcmp": false, "Zawrs": true}}}} Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- qapi/machine-target.json | 6 ++- target/riscv/riscv-qmp-cmds.c | 75 +++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/qapi/machine-target.json b/qapi/machine-target.json index f0a6b72414..e5630e73aa 100644 --- a/qapi/machine-target.json +++ b/qapi/machine-target.json @@ -228,7 +228,8 @@ 'data': { 'model': 'CpuModelInfo' }, 'if': { 'any': [ 'TARGET_S390X', 'TARGET_I386', - 'TARGET_ARM' ] } } + 'TARGET_ARM', + 'TARGET_RISCV' ] } } =20 ## # @query-cpu-model-expansion: @@ -273,7 +274,8 @@ 'returns': 'CpuModelExpansionInfo', 'if': { 'any': [ 'TARGET_S390X', 'TARGET_I386', - 'TARGET_ARM' ] } } + 'TARGET_ARM', + 'TARGET_RISCV' ] } } =20 ## # @CpuDefinitionInfo: diff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c index 5ecff1afb3..2170562e3a 100644 --- a/target/riscv/riscv-qmp-cmds.c +++ b/target/riscv/riscv-qmp-cmds.c @@ -24,8 +24,12 @@ =20 #include "qemu/osdep.h" =20 +#include "qapi/error.h" #include "qapi/qapi-commands-machine-target.h" +#include "qapi/qmp/qdict.h" +#include "qom/qom-qobject.h" #include "cpu-qom.h" +#include "cpu.h" =20 static void riscv_cpu_add_definition(gpointer data, gpointer user_data) { @@ -55,3 +59,74 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error *= *errp) =20 return cpu_list; } + +static void riscv_obj_add_qdict_prop(Object *obj, QDict *qdict_out, + const char *name) +{ + ObjectProperty *prop =3D object_property_find(obj, name); + + if (prop) { + QObject *value; + + assert(prop->get); + value =3D object_property_get_qobject(obj, name, &error_abort); + + qdict_put_obj(qdict_out, name, value); + } +} + +static void riscv_obj_add_multiext_props(Object *obj, QDict *qdict_out, + const RISCVCPUMultiExtConfig *arr) +{ + for (int i =3D 0; arr[i].name !=3D NULL; i++) { + riscv_obj_add_qdict_prop(obj, qdict_out, arr[i].name); + } +} + +CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType= type, + CpuModelInfo *model, + Error **errp) +{ + CpuModelExpansionInfo *expansion_info; + QDict *qdict_out; + ObjectClass *oc; + Object *obj; + + if (type !=3D CPU_MODEL_EXPANSION_TYPE_FULL) { + error_setg(errp, "The requested expansion type is not supported"); + return NULL; + } + + oc =3D cpu_class_by_name(TYPE_RISCV_CPU, model->name); + if (!oc) { + error_setg(errp, "The CPU type '%s' is not a known RISC-V CPU type= ", + model->name); + return NULL; + } + + obj =3D object_new(object_class_get_name(oc)); + + expansion_info =3D g_new0(CpuModelExpansionInfo, 1); + expansion_info->model =3D g_malloc0(sizeof(*expansion_info->model)); + expansion_info->model->name =3D g_strdup(model->name); + + qdict_out =3D qdict_new(); + + riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions); + riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_experimental_ex= ts); + riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts); + + /* Add our CPU boolean options too */ + riscv_obj_add_qdict_prop(obj, qdict_out, "mmu"); + riscv_obj_add_qdict_prop(obj, qdict_out, "pmp"); + + if (!qdict_size(qdict_out)) { + qobject_unref(qdict_out); + } else { + expansion_info->model->props =3D QOBJECT(qdict_out); + } + + object_unref(obj); + + return expansion_info; +} --=20 2.41.0