From nobody Sat Dec 27 13:34:48 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1698069807; cv=none; d=zohomail.com; s=zohoarc; b=R1CjgIROWXTau/hXMSsQQz7FpztatMUPp1Lr+pq39QC1TLWRkegfCtdc7jBztaalntPrNb4YJ0CiFMFbCIizlmFg2uzYq1Nf9eWuXMYHq1pHzIsU/uwy3gPGoFgXvzEJC7WHUw45ogN7iGY7D+pI2dPX5y+ReiBaVhYGoDdzQcM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698069807; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=EfF3IR25OTEFtIBahaFeOPOHt8h/XvZX0HSiawmevFE=; b=CInxJQpbdzD0eBUAi8j8RxE5iw173MSltV+4qvATQJH1aiC7UEJpV9GJVVRDvufjNYXlZgpj5mLLYzDV3O5Thx7IztN0zdbDjs0bCNAZmfMtmcchShgSetYL9/1+jWkawM4tIaVBXbMm4+MaVD6PpTbi0qH3FBebW/DcnT1HgLM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698069806986293.2147640300507; Mon, 23 Oct 2023 07:03:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1quvWX-0005wJ-9o; Mon, 23 Oct 2023 10:03:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1quvWV-0005s0-UO for qemu-devel@nongnu.org; Mon, 23 Oct 2023 10:03:15 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1quvWT-0003jD-Bo for qemu-devel@nongnu.org; Mon, 23 Oct 2023 10:03:15 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4SDcJ74pK2z67DRW; Mon, 23 Oct 2023 21:59:35 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Mon, 23 Oct 2023 15:03:11 +0100 To: , , Michael Tsirkin , Michael Tokarev CC: , Fan Ni , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 2/5] hw/cxl: Use switch statements for read and write of cachemem registers Date: Mon, 23 Oct 2023 15:02:07 +0100 Message-ID: <20231023140210.3089-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231023140210.3089-1-Jonathan.Cameron@huawei.com> References: <20231023140210.3089-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500005.china.huawei.com (7.191.163.240) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1698069809105100001 Content-Type: text/plain; charset="utf-8" Establishing that only register accesses of size 4 and 8 can occur using these functions requires looking at their callers. Make it easier to see that by using switch statements. Assertions are used to enforce that the register storage is of the matching size, allowing fixed values to be used for divisors of the array indices. Suggested-by: Michael Tokarev Signed-off-by: Jonathan Cameron Reviewed-by: Fan Ni --- v5: _Static_assert() is a declaration in C, so may not follow a label. Hence wrap it in {} to ensure it doesn't. Issue seen with clang builds (and in some cases at least older GCC). We can't wrap it in {} in the QEMU_BUILD_BUG_ON() define as that is used in a few places outside of functions. hw/cxl/cxl-component-utils.c | 66 +++++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 23 deletions(-) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index f3bbf0fd13..9d4f4bc8d4 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -67,16 +67,24 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hw= addr offset, CXLComponentState *cxl_cstate =3D opaque; ComponentRegisters *cregs =3D &cxl_cstate->crb; =20 - if (size =3D=3D 8) { + switch (size) { + case 4: + if (cregs->special_ops && cregs->special_ops->read) { + return cregs->special_ops->read(cxl_cstate, offset, 4); + } else { + QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) !=3D 4); + return cregs->cache_mem_registers[offset / 4]; + } + case 8: qemu_log_mask(LOG_UNIMP, "CXL 8 byte cache mem registers not implemented\n"); return 0; - } - - if (cregs->special_ops && cregs->special_ops->read) { - return cregs->special_ops->read(cxl_cstate, offset, size); - } else { - return cregs->cache_mem_registers[offset / sizeof(*cregs->cache_me= m_registers)]; + default: + /* + * In line with specifiction limitaions on access sizes, this + * routine is not called with other sizes. + */ + g_assert_not_reached(); } } =20 @@ -117,25 +125,37 @@ static void cxl_cache_mem_write_reg(void *opaque, hwa= ddr offset, uint64_t value, ComponentRegisters *cregs =3D &cxl_cstate->crb; uint32_t mask; =20 - if (size =3D=3D 8) { - qemu_log_mask(LOG_UNIMP, - "CXL 8 byte cache mem registers not implemented\n"); + switch (size) { + case 4: { + QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_regs_write_mask) !=3D 4= ); + QEMU_BUILD_BUG_ON(sizeof(*cregs->cache_mem_registers) !=3D 4); + mask =3D cregs->cache_mem_regs_write_mask[offset / 4]; + value &=3D mask; + /* RO bits should remain constant. Done by reading existing value = */ + value |=3D ~mask & cregs->cache_mem_registers[offset / 4]; + if (cregs->special_ops && cregs->special_ops->write) { + cregs->special_ops->write(cxl_cstate, offset, value, size); + return; + } + + if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && + offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { + dumb_hdm_handler(cxl_cstate, offset, value); + } else { + cregs->cache_mem_registers[offset / 4] =3D value; + } return; } - mask =3D cregs->cache_mem_regs_write_mask[offset / sizeof(*cregs->cach= e_mem_regs_write_mask)]; - value &=3D mask; - /* RO bits should remain constant. Done by reading existing value */ - value |=3D ~mask & cregs->cache_mem_registers[offset / sizeof(*cregs->= cache_mem_registers)]; - if (cregs->special_ops && cregs->special_ops->write) { - cregs->special_ops->write(cxl_cstate, offset, value, size); + case 8: + qemu_log_mask(LOG_UNIMP, + "CXL 8 byte cache mem registers not implemented\n"); return; - } - - if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && - offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { - dumb_hdm_handler(cxl_cstate, offset, value); - } else { - cregs->cache_mem_registers[offset / sizeof(*cregs->cache_mem_regis= ters)] =3D value; + default: + /* + * In line with specifiction limitaions on access sizes, this + * routine is not called with other sizes. + */ + g_assert_not_reached(); } } =20 --=20 2.39.2