From nobody Mon May 12 19:15:56 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1698069848; cv=none; d=zohomail.com; s=zohoarc; b=lGZDilLBIz5MnvlnXWvNTOFzhSNHOwd+TI9pRwgRwmUKxzqq/zToSjMPBmqagClUbl4meJ1VmGD4gfriE27JCRUk61QQmS3dedmGI2t5mWJGWUDxVMGZfBOKT4HG26Umy1xZR6d6phEqxY2dwWRWZx/kqIIKQbAP/sF9gc2tCBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1698069848; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=EBF2JLeqhV9VBzlump19fYGapNQkBdblNbybdS06biw=; b=ObYoaam7YH7SXABpM8E9mM+NzSH9Dpg/CznoorCdH8QRMeP8xMBROamenwigGBuNjL8wuq1YQGzr6j4WcCT/35CA6BG6jfsMWieQSvypSgYpcAyceNNYMIjp7WSFyn3i0GWlVPqwdS0/CBL1T+5EwN7b6rkKiO7ZYJtUwhNMN8g= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1698069848526523.5360788805891; Mon, 23 Oct 2023 07:04:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1quvX1-0007Fc-6O; Mon, 23 Oct 2023 10:03:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1quvWz-0007CY-Lu for qemu-devel@nongnu.org; Mon, 23 Oct 2023 10:03:45 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1quvWx-0003uK-NO for qemu-devel@nongnu.org; Mon, 23 Oct 2023 10:03:45 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4SDcKq2W27z6K6jn; Mon, 23 Oct 2023 22:01:03 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Mon, 23 Oct 2023 15:03:41 +0100 To: , , Michael Tsirkin , Michael Tokarev CC: , Fan Ni , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 3/5] hw/cxl: CXLDVSECPortExtensions renamed to CXLDVSECPortExt Date: Mon, 23 Oct 2023 15:02:08 +0100 Message-ID: <20231023140210.3089-4-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231023140210.3089-1-Jonathan.Cameron@huawei.com> References: <20231023140210.3089-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml500005.china.huawei.com (7.191.163.240) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1698069849534100001 Done to reduce line lengths where this is used. Ext seems sufficiently obvious that it need not be spelt out fully. Signed-off-by: Jonathan Cameron Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Fan Ni --- include/hw/cxl/cxl_pci.h | 6 ++--- hw/cxl/cxl-component-utils.c | 49 ++++++++++++++++++++-------------- hw/pci-bridge/cxl_downstream.c | 2 +- hw/pci-bridge/cxl_root_port.c | 2 +- hw/pci-bridge/cxl_upstream.c | 2 +- 5 files changed, 35 insertions(+), 26 deletions(-) diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h index 407be95b9e..ddf01a543b 100644 --- a/include/hw/cxl/cxl_pci.h +++ b/include/hw/cxl/cxl_pci.h @@ -86,7 +86,7 @@ typedef struct CXLDVSECDevice { QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) !=3D 0x38); =20 /* CXL 2.0 - 8.1.5 (ID 0003) */ -typedef struct CXLDVSECPortExtensions { +typedef struct CXLDVSECPortExt { DVSECHeader hdr; uint16_t status; uint16_t control; @@ -100,8 +100,8 @@ typedef struct CXLDVSECPortExtensions { uint32_t alt_prefetch_limit_high; uint32_t rcrb_base; uint32_t rcrb_base_high; -} CXLDVSECPortExtensions; -QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExtensions) !=3D 0x28); +} CXLDVSECPortExt; +QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExt) !=3D 0x28); =20 #define PORT_CONTROL_OFFSET 0xc #define PORT_CONTROL_UNMASK_SBR 1 diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 9d4f4bc8d4..1f4ea11640 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -393,26 +393,35 @@ void cxl_component_create_dvsec(CXLComponentState *cx= l, case NON_CXL_FUNCTION_MAP_DVSEC: break; /* Not yet implemented */ case EXTENSIONS_PORT_DVSEC: - wmask[offset + offsetof(CXLDVSECPortExtensions, control)] =3D 0x0F; - wmask[offset + offsetof(CXLDVSECPortExtensions, control) + 1] =3D = 0x40; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_base)] =3D= 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_bus_limit)] = =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base)] = =3D 0xF0; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_base) += 1] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit)]= =3D 0xF0; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_memory_limit) = + 1] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)= ] =3D 0xF0; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base)= + 1] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit= )] =3D 0xF0; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit= ) + 1] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_= high)] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_= high) + 1] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_= high) + 2] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_base_= high) + 3] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit= _high)] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit= _high) + 1] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit= _high) + 2] =3D 0xFF; - wmask[offset + offsetof(CXLDVSECPortExtensions, alt_prefetch_limit= _high) + 3] =3D 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, control)] =3D 0x0F; + wmask[offset + offsetof(CXLDVSECPortExt, control) + 1] =3D 0x40; + wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_base)] =3D 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_bus_limit)] =3D 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base)] =3D 0xF= 0; + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_base) + 1] =3D= 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit)] =3D 0x= F0; + wmask[offset + offsetof(CXLDVSECPortExt, alt_memory_limit) + 1] = =3D 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base)] =3D 0= xF0; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base) + 1] = =3D 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit)] =3D = 0xF0; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit) + 1] = =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high)] = =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) += 1] =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) += 2] =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_base_high) += 3] =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high)]= =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) = + 1] =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) = + 2] =3D + 0xFF; + wmask[offset + offsetof(CXLDVSECPortExt, alt_prefetch_limit_high) = + 3] =3D + 0xFF; break; case GPF_PORT_DVSEC: wmask[offset + offsetof(CXLDVSECPortGPF, phase1_ctrl)] =3D 0x0F; diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 5a2b749c8e..8c0f759add 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -98,7 +98,7 @@ static void build_dvsecs(CXLComponentState *cxl) { uint8_t *dvsec; =20 - dvsec =3D (uint8_t *)&(CXLDVSECPortExtensions){ 0 }; + dvsec =3D (uint8_t *)&(CXLDVSECPortExt){ 0 }; cxl_component_create_dvsec(cxl, CXL2_DOWNSTREAM_PORT, EXTENSIONS_PORT_DVSEC_LENGTH, EXTENSIONS_PORT_DVSEC, diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 7dfd20aa67..8f97697631 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -107,7 +107,7 @@ static void build_dvsecs(CXLComponentState *cxl) { uint8_t *dvsec; =20 - dvsec =3D (uint8_t *)&(CXLDVSECPortExtensions){ 0 }; + dvsec =3D (uint8_t *)&(CXLDVSECPortExt){ 0 }; cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT, EXTENSIONS_PORT_DVSEC_LENGTH, EXTENSIONS_PORT_DVSEC, diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index a57806fb31..b81bb5fec9 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -116,7 +116,7 @@ static void build_dvsecs(CXLComponentState *cxl) { uint8_t *dvsec; =20 - dvsec =3D (uint8_t *)&(CXLDVSECPortExtensions){ + dvsec =3D (uint8_t *)&(CXLDVSECPortExt){ .status =3D 0x1, /* Port Power Management Init Complete */ }; cxl_component_create_dvsec(cxl, CXL2_UPSTREAM_PORT, --=20 2.39.2