From nobody Wed May 14 22:22:05 2025 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1699516317; cv=none; d=zohomail.com; s=zohoarc; b=GVU8UhYe1GxmVSyEHnLCqRlPeVa7w73/sfdPI9SLsM/4sh6cF5SNDkeMLYcraMLVEe+q4h9olfsm8Y2qUvMnT0/ViRUOq//JVbA8Oth7RKcA+zJUM69uIJzKKpw4uYREr2Nijp7MG4XLKmg1BOgF22jo8tngBlMtDMqOnLkYHJI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1699516317; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lQOD165aMVikf2RKVcW7Rj21iS2BYWjNZJ0rG9ADB5c=; b=FwzuffeRopPAtw4WiAuJgV5yFEIlwBfhs5klfw0AS677nuwMGlDH1DRU3QCOXmgnZs2HVuABMbGBHkJ3UTGcYi6Qm4MUa5BTow/jQKF53/4ACAvdkidns/yIxBzHCvPIxjSniV32UCXgDELHpvwQJAmDR8yXQk3hNEamM91GKC0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1699516317658232.3737494479284; Wed, 8 Nov 2023 23:51:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1r0zoL-0007L1-SO; Thu, 09 Nov 2023 02:50:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0zoJ-0007JD-0B for qemu-devel@nongnu.org; Thu, 09 Nov 2023 02:50:43 -0500 Received: from mgamail.intel.com ([192.55.52.43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1r0zoF-0001o2-Qn for qemu-devel@nongnu.org; Thu, 09 Nov 2023 02:50:41 -0500 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2023 23:50:22 -0800 Received: from unknown (HELO fred..) ([172.25.112.68]) by orsmga002.jf.intel.com with ESMTP; 08 Nov 2023 23:50:22 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699516239; x=1731052239; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OTzIm8gCXp6Ung+Q+TxnUDKEdG2Zy3BQi6wounkD6Es=; b=JAXKgNVvtyh/zDFlbj7L698woHPVYg1kGF5g0FBwX0I7WIcqeGK2PtEa NLXmcXOjxqHB2l2OiIJ6glSHjIvGwMJUQjHqVFUrZ/ZiQsEht+jb9OhRJ aZiVk35Ocl/XQpy++UoRRUVFa6seVTPTyyV8gYphfdUIoJsdxYi4Q9ZDO MF1+PcFOyyJ5H4b3trBQhIpSJJpQeknsp8NUzm67oJtwTt2MYnaybmB0a o0NZ0eXkAWtLmoC6J0LArYQ5NT3GxdwAmk71m8ZK3YW6IqS0sYkIkG9fc pF0Gpd8UQA8tM9VHdouSPsiuRRT/oLCg1qNljaH4EvR1o4xztFbA8f3dk Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="476165145" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="476165145" X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10888"; a="763329279" X-IronPort-AV: E=Sophos;i="6.03,288,1694761200"; d="scan'208";a="763329279" From: Xin Li To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, richard.henderson@linaro.org, pbonzini@redhat.com, eduardo@habkost.net, seanjc@google.com, chao.gao@intel.com, hpa@zytor.com, xiaoyao.li@intel.com, weijiang.yang@intel.com Subject: [PATCH v3 3/6] target/i386: add the secondary VM exit controls MSR Date: Wed, 8 Nov 2023 23:20:09 -0800 Message-ID: <20231109072012.8078-4-xin3.li@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231109072012.8078-1-xin3.li@intel.com> References: <20231109072012.8078-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=xin3.li@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1699516319932100003 Content-Type: text/plain; charset="utf-8" Add the secondary VM exit controls MSR to prepare for KVM FRED enabling. Tested-by: Shan Kang Signed-off-by: Xin Li --- scripts/kvm/vmxcap | 9 +++++++++ target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap index 3fb4d5b342..7da1e00ca8 100755 --- a/scripts/kvm/vmxcap +++ b/scripts/kvm/vmxcap @@ -24,6 +24,7 @@ MSR_IA32_VMX_TRUE_EXIT_CTLS =3D 0x48F MSR_IA32_VMX_TRUE_ENTRY_CTLS =3D 0x490 MSR_IA32_VMX_VMFUNC =3D 0x491 MSR_IA32_VMX_PROCBASED_CTLS3 =3D 0x492 +MSR_IA32_VMX_EXIT_CTLS2 =3D 0x493 =20 class msr(object): def __init__(self): @@ -219,11 +220,19 @@ controls =3D [ 23: 'Clear IA32_BNDCFGS', 24: 'Conceal VM exits from PT', 25: 'Clear IA32_RTIT_CTL', + 31: 'Activate secondary VM-exit controls', }, cap_msr =3D MSR_IA32_VMX_EXIT_CTLS, true_cap_msr =3D MSR_IA32_VMX_TRUE_EXIT_CTLS, ), =20 + Allowed1Control( + name =3D 'secondary VM-Exit controls', + bits =3D { + }, + cap_msr =3D MSR_IA32_VMX_EXIT_CTLS2, + ), + Control( name =3D 'VM-Entry controls', bits =3D { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 403c84177a..227ee1c759 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1270,7 +1270,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "vmx-exit-save-efer", "vmx-exit-load-efer", "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, - NULL, "vmx-exit-load-pkrs", NULL, NULL, + NULL, "vmx-exit-load-pkrs", NULL, "vmx-exit-secondary-ctls", }, .msr =3D { .index =3D MSR_IA32_VMX_TRUE_EXIT_CTLS, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e210957cba..a4d3702621 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -551,6 +551,7 @@ typedef enum X86Seg { #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 #define MSR_IA32_VMX_VMFUNC 0x00000491 +#define MSR_IA32_VMX_EXIT_CTLS2 0x00000493 =20 #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 --=20 2.42.0