target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of
* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 7d84e7d812..ef568e263d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -50,6 +50,22 @@ static bool require_rvf(DisasContext *s)
}
}
+static bool require_rvfmin(DisasContext *s)
+{
+ if (s->mstatus_fs == EXT_STATUS_DISABLED) {
+ return false;
+ }
+
+ switch (s->sew) {
+ case MO_16:
+ return s->cfg_ptr->ext_zvfhmin;
+ case MO_32:
+ return s->cfg_ptr->ext_zve32f;
+ default:
+ return false;
+ }
+}
+
static bool require_scale_rvf(DisasContext *s)
{
if (s->mstatus_fs == EXT_STATUS_DISABLED) {
@@ -75,8 +91,6 @@ static bool require_scale_rvfmin(DisasContext *s)
}
switch (s->sew) {
- case MO_8:
- return s->cfg_ptr->ext_zvfhmin;
case MO_16:
return s->cfg_ptr->ext_zve32f;
case MO_32:
@@ -2685,6 +2699,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a)
static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
{
return opfv_widen_check(s, a) &&
+ require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
}
@@ -2790,6 +2805,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a)
static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
{
return opfv_narrow_check(s, a) &&
+ require_rvfmin(s) &&
require_scale_rvfmin(s) &&
(s->sew != MO_8);
}
--
2.31.1
On 3/20/24 04:25, Max Chou wrote: > According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w > instructions will be affected by Zvfhmin extension. > And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the > conversions of > > * From 1*SEW(16/32) to 2*SEW(32/64) > * From 2*SEW(32/64) to 1*SEW(16/32) > > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 7d84e7d812..ef568e263d 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -50,6 +50,22 @@ static bool require_rvf(DisasContext *s) > } > } > > +static bool require_rvfmin(DisasContext *s) > +{ > + if (s->mstatus_fs == EXT_STATUS_DISABLED) { > + return false; > + } > + > + switch (s->sew) { > + case MO_16: > + return s->cfg_ptr->ext_zvfhmin; > + case MO_32: > + return s->cfg_ptr->ext_zve32f; > + default: > + return false; > + } > +} > + > static bool require_scale_rvf(DisasContext *s) > { > if (s->mstatus_fs == EXT_STATUS_DISABLED) { > @@ -75,8 +91,6 @@ static bool require_scale_rvfmin(DisasContext *s) > } > > switch (s->sew) { > - case MO_8: > - return s->cfg_ptr->ext_zvfhmin; > case MO_16: > return s->cfg_ptr->ext_zve32f; > case MO_32: > @@ -2685,6 +2699,7 @@ static bool opxfv_widen_check(DisasContext *s, arg_rmr *a) > static bool opffv_widen_check(DisasContext *s, arg_rmr *a) > { > return opfv_widen_check(s, a) && > + require_rvfmin(s) && > require_scale_rvfmin(s) && > (s->sew != MO_8); > } > @@ -2790,6 +2805,7 @@ static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) > static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > { > return opfv_narrow_check(s, a) && > + require_rvfmin(s) && > require_scale_rvfmin(s) && > (s->sew != MO_8); > }
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