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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bt30-20020a056000081e00b00341b9e11b11sm2067039wrb.24.2024.03.28.08.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 08:33:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711640015; x=1712244815; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=HoXcWIswnaiYn+YGfxoqs8bfwHg7SCgsOteFXjUUrDI=; b=lrPq1BXStVueusSFfHC1HToxaenBcx4LtMGLV9TidOCdtHYBLjtDSt3tb29WngSAoC NeLSh7tRkAOSWCCuONOA+gByvIB/WXOkP7yPVcj61ZTLxijaCwaVfCzyjSSlkGgFHM/B hgZEwl1HyEQHibBhwfcQQ9qRHGaR0cGk7JGcnpSXyYB6LjIM7LMAQJ7TlC0j06MNE4hf uVkMNYbx0gu8pV3C+jciXZECTny49b9nY9Tr4L6P5fFXH23hYxNUkoK//zX1OOH4btFb 4zpZZ2Bxu+BXbxkW9+AZWwgE1xyDU/eHyMjitF4Ijs/eg3ZZWolcxKb3/LZY3vKyBknv qrZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711640015; x=1712244815; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HoXcWIswnaiYn+YGfxoqs8bfwHg7SCgsOteFXjUUrDI=; b=i0iE6aefeCMxfOAHxKvrgaIIV8cP2ai/AIBxnXuB/nDa/CP+03e2UPcSU7xu2zeFZ4 tkVpz+odQ3nsaH7hte7GJofCBKIKE0eWnUKcdIyalmsUs024ZQZ1Mj43cSBZNeT0IwZG zRj8mQ+zqOxuL3rHi1RNfXVjtLhEr468M1YzemZ1tIc425tf1+uVawuc7NXwhCtTJGWU 5+CSMAScCsa63fjkZ+QTVMMH6lC+u/c8g1mpfCCHIMsN0C2Qbm3USqcaVPOk1nLmQe7g 3sVAhi1ucyrd9iRz7kEt4NCZrSPIKhdkl/WWSdV8lDAGdD2Wgz/cRCjMXSy6CHaT/iik Bl3A== X-Forwarded-Encrypted: i=1; AJvYcCVsrsp5/TtW3W2blFzzVdUargIu2MUNQ7xPhsQA/SHXnOtm7sQYkl6WzlD0pZfQasFJl8UdgDR5luN10S7k7XnpsSyLFTk= X-Gm-Message-State: AOJu0YxOFBQvKI9hkPoxsEYu3zTkV48yVMo6nyFwxjygYBsh9GFgcL19 PGtN0xktQUoWyb/0bNsKW1bQtlFSPrGO9/p0wedjsbCYzbTy7qcyAKUz/nQEMoI= X-Google-Smtp-Source: AGHT+IEJQrbm8joYzk/e6QuZrkxTUptRMqeUoXjYFQtfyn+KXmfNHVxZTB4Bid6M1w70nAMAkaKobg== X-Received: by 2002:a5d:6586:0:b0:33e:34aa:d78a with SMTP id q6-20020a5d6586000000b0033e34aad78amr3033455wru.8.1711640014748; Thu, 28 Mar 2024 08:33:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org Subject: [PATCH] hw/intc/arm_gicv3: ICC_HPPIR* return SPURIOUS if int group is disabled Date: Thu, 28 Mar 2024 15:33:33 +0000 Message-Id: <20240328153333.2522667-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1711640096543100003 Content-Type: text/plain; charset="utf-8" If the group of the highest priority pending interrupt is disabled via ICC_IGRPEN*, the ICC_HPPIR* registers should return INTID_SPURIOUS, not the interrupt ID. (See the GIC architecture specification pseudocode functions ICC_HPPIR1_EL1[] and HighestPriorityPendingInterrupt().) Make HPPIR reads honour the group disable, the way we already do when determining whether to preempt in icc_hppi_can_preempt(). Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Pre-existing bug which I happened to notice while working on review of the FEAT_NMI patches. I don't suppose real world code disables interrupt groups which it's actually using, which is why nobody's noticed it. Still, it's a safe bugfix so might as well go to stable too. --- hw/intc/arm_gicv3_cpuif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e1a60d8c15b..67d8fd07b7f 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1067,7 +1067,7 @@ static uint64_t icc_hppir0_value(GICv3CPUState *cs, C= PUARMState *env) */ bool irq_is_secure; =20 - if (cs->hppi.prio =3D=3D 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } =20 @@ -1104,7 +1104,7 @@ static uint64_t icc_hppir1_value(GICv3CPUState *cs, C= PUARMState *env) */ bool irq_is_secure; =20 - if (cs->hppi.prio =3D=3D 0xff) { + if (icc_no_enabled_hppi(cs)) { return INTID_SPURIOUS; } =20 --=20 2.34.1