From nobody Mon Sep 16 20:02:37 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712728062176712.769950461671; Tue, 9 Apr 2024 22:47:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ruQnw-0001F5-I6; Wed, 10 Apr 2024 01:47:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruQmN-0005QT-KT; Wed, 10 Apr 2024 01:45:59 -0400 Received: from isrv.corpit.ru ([86.62.121.231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ruQmL-0001iP-K8; Wed, 10 Apr 2024 01:45:51 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id BD1825D4E9; Wed, 10 Apr 2024 08:46:15 +0300 (MSK) Received: from tls.msk.ru (mjt.wg.tls.msk.ru [192.168.177.130]) by tsrv.corpit.ru (Postfix) with SMTP id 81605B0150; Wed, 10 Apr 2024 08:44:17 +0300 (MSK) Received: (nullmailer pid 4182052 invoked by uid 1000); Wed, 10 Apr 2024 05:44:16 -0000 From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Klaus Jensen , Jesper Wendel Devantier , Michael Tokarev Subject: [Stable-7.2.11 17/41] hw/nvme: generalize the mbar size helper Date: Wed, 10 Apr 2024 08:43:38 +0300 Message-Id: <20240410054416.4181891-17-mjt@tls.msk.ru> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=86.62.121.231; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZM-MESSAGEID: 1712728064266100007 Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Generalize the mbar size helper such that it can handle cases where the MSI-X table and PBA are expected to be in an exclusive bar. Cc: qemu-stable@nongnu.org Reviewed-by: Jesper Wendel Devantier Signed-off-by: Klaus Jensen (cherry picked from commit ee7bda4d38cda3eaf114c850a723dd12e23d3abc) Signed-off-by: Michael Tokarev diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index c2c0fc991d..32df214762 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -7221,13 +7221,18 @@ static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *p= ci_dev) memory_region_set_enabled(&n->pmr.dev->mr, false); } =20 -static uint64_t nvme_bar_size(unsigned total_queues, unsigned total_irqs, - unsigned *msix_table_offset, - unsigned *msix_pba_offset) +static uint64_t nvme_mbar_size(unsigned total_queues, unsigned total_irqs, + unsigned *msix_table_offset, + unsigned *msix_pba_offset) { - uint64_t bar_size, msix_table_size, msix_pba_size; + uint64_t bar_size, msix_table_size; =20 bar_size =3D sizeof(NvmeBar) + 2 * total_queues * NVME_DB_SIZE; + + if (total_irqs =3D=3D 0) { + goto out; + } + bar_size =3D QEMU_ALIGN_UP(bar_size, 4 * KiB); =20 if (msix_table_offset) { @@ -7242,11 +7247,10 @@ static uint64_t nvme_bar_size(unsigned total_queues= , unsigned total_irqs, *msix_pba_offset =3D bar_size; } =20 - msix_pba_size =3D QEMU_ALIGN_UP(total_irqs, 64) / 8; - bar_size +=3D msix_pba_size; + bar_size +=3D QEMU_ALIGN_UP(total_irqs, 64) / 8; =20 - bar_size =3D pow2ceil(bar_size); - return bar_size; +out: + return pow2ceil(bar_size); } =20 static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offs= et) @@ -7254,7 +7258,7 @@ static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *p= ci_dev, uint16_t offset) uint16_t vf_dev_id =3D n->params.use_intel_id ? PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_N= VME; NvmePriCtrlCap *cap =3D &n->pri_ctrl_cap; - uint64_t bar_size =3D nvme_bar_size(le16_to_cpu(cap->vqfrsm), + uint64_t bar_size =3D nvme_mbar_size(le16_to_cpu(cap->vqfrsm), le16_to_cpu(cap->vifrsm), NULL, NULL); =20 @@ -7293,7 +7297,7 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) ERRP_GUARD(); uint8_t *pci_conf =3D pci_dev->config; uint64_t bar_size; - unsigned msix_table_offset, msix_pba_offset; + unsigned msix_table_offset =3D 0, msix_pba_offset =3D 0; int ret; =20 pci_conf[PCI_INTERRUPT_PIN] =3D 1; @@ -7316,8 +7320,8 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice *pci= _dev, Error **errp) } =20 /* add one to max_ioqpairs to account for the admin queue pair */ - bar_size =3D nvme_bar_size(n->params.max_ioqpairs + 1, n->params.msix_= qsize, - &msix_table_offset, &msix_pba_offset); + bar_size =3D nvme_mbar_size(n->params.max_ioqpairs + 1, n->params.msix= _qsize, + &msix_table_offset, &msix_pba_offset); =20 memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", --=20 2.39.2