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([2a01:e0a:999:a3a0:3624:d9b3:4998:d76b]) by smtp.gmail.com with ESMTPSA id g13-20020a05600c4ecd00b004148d7b889asm5255206wmq.8.2024.04.11.04.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Apr 2024 04:34:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1712835256; x=1713440056; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=dhg1qThRQZKAnIydYrVnrsjqRJWIakORnGcfY7auAjk=; b=dlAWOl07dmv5BDTIDCHkJSf1KLsfmFDalgVCWQS+4atdz5ccLfzKtPC0385xknAvuY nbGZWoPqxmX3CwJY+nW4g+CZC+ImFUuuhe9higa+CfJi85WQqsizb5wMHcLRgWdJpogR 63kZvO45mpMJNiNZJW2hLhzUBkjLkSegvFvvTxPUpO5Ziy3AFSJHgBDefcB4uCSgPtm2 TMG2k73IKG1XbMR+OatVCGNuQ1rl7jJRdzPOrP5AcmPh4WDcgbs96HTXFx/B0NNKlp1D fwq4JUBKdccWo/yu+s9DWbp9Ubm0xym+e4rYiNgm8kEfzBuSbPqHmpWIGTf8tnAGT1hW H/Kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1712835256; x=1713440056; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=dhg1qThRQZKAnIydYrVnrsjqRJWIakORnGcfY7auAjk=; b=PUyr0xolgX5UrwIX3Kr/sHirIS/xDuiXgWClrX4DWuFBENOrks03cCMgray6+YhMtv FzYa+9id4xlJhcZ4tAYIEqEVzi4VjGi2vaLkp4/iYHlMkff+OwbJNjPOnHiiD2vNNSWa bqnLJuyavehrN7z9alf+d022RqXvoJIqgN/rA4N8jZQeZnxwvU/1AECLVG/fgy0FCvYd hCEgO7mMgpveyIuU+pLzn9d5kvDxkHTDh3H78eoyjSUWfyZgWlRh4hmGwQL4UpuTmxjK kK0knSlCNH06RlbVdAzTy3pIOndslXgbWe8S/iY6i36RGYjkAcip+K66/Jwu/i+59tQB F5cg== X-Forwarded-Encrypted: i=1; AJvYcCUCcI4IgHQpBEvcEt7krVdtHDeiAAgIM7q4+XRICnasHToQb8YUJBayUQnkXJnPc4jyFnAHotY2QskWl0bqmKNUjrmJaro= X-Gm-Message-State: AOJu0YznU3bqEMCAdbJ3mfiwPFz0TRRORebnfUSjh0MzIZyMy2aQqfpu nRyX+dBEDOHIs+zvT/h3zARHaNJgyPqufbzFUk99XNBNQaANKqkJVi4KoBO0JxQ= X-Google-Smtp-Source: AGHT+IEO7pMDVJ2m1BQnxpFZfRC9wCMiPpcU79+9F6yA31evVKJ9UWkG+3omotzVD6/S+lU12TPbEQ== X-Received: by 2002:a05:600c:5104:b0:416:a773:7d18 with SMTP id o4-20020a05600c510400b00416a7737d18mr3775149wms.0.1712835256118; Thu, 11 Apr 2024 04:34:16 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= To: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , qemu-devel@nongnu.org, Atish Patra Subject: [PATCH] target/riscv: fix instructions count handling in icount mode Date: Thu, 11 Apr 2024 13:34:05 +0200 Message-ID: <20240411113406.1301906-1-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=cleger@rivosinc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1712835298919100003 When icount is enabled, rather than returning the virtual CPU time, we should return the instruction count itself. Add an instructions bool parameter to get_ticks() to correctly return icount_get_raw() when icount_enabled() =3D=3D 1 and instruction count is queried. This will modify the existing behavior which was returning an instructions count close to the number of cycles (CPI ~=3D 1). Signed-off-by: Cl=C3=A9ment L=C3=A9ger Reviewed-by: Atish Patra --- target/riscv/csr.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444f..5f1dcee102 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -762,14 +762,17 @@ static RISCVException write_vcsr(CPURISCVState *env, = int csrno, } =20 /* User Timers and Counters */ -static target_ulong get_ticks(bool shift) +static target_ulong get_ticks(bool shift, bool instructions) { int64_t val; target_ulong result; =20 #if !defined(CONFIG_USER_ONLY) if (icount_enabled()) { - val =3D icount_get(); + if (instructions) + val =3D icount_get_raw(); + else + val =3D icount_get(); } else { val =3D cpu_get_host_ticks(); } @@ -804,14 +807,14 @@ static RISCVException read_timeh(CPURISCVState *env, = int csrno, static RISCVException read_hpmcounter(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D get_ticks(false); + *val =3D get_ticks(false, (csrno =3D=3D CSR_INSTRET)); return RISCV_EXCP_NONE; } =20 static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D get_ticks(true); + *val =3D get_ticks(true, (csrno =3D=3D CSR_INSTRETH)); return RISCV_EXCP_NONE; } =20 @@ -875,11 +878,11 @@ static RISCVException write_mhpmcounter(CPURISCVState= *env, int csrno, int ctr_idx =3D csrno - CSR_MCYCLE; PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D val; + bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 counter->mhpmcounter_val =3D val; - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounter_prev =3D get_ticks(false); + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { + counter->mhpmcounter_prev =3D get_ticks(false, instr); if (ctr_idx > 2) { if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { mhpmctr_val =3D mhpmctr_val | @@ -902,12 +905,12 @@ static RISCVException write_mhpmcounterh(CPURISCVStat= e *env, int csrno, PMUCTRState *counter =3D &env->pmu_ctrs[ctr_idx]; uint64_t mhpmctr_val =3D counter->mhpmcounter_val; uint64_t mhpmctrh_val =3D val; + bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 counter->mhpmcounterh_val =3D val; mhpmctr_val =3D mhpmctr_val | (mhpmctrh_val << 32); - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - counter->mhpmcounterh_prev =3D get_ticks(true); + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { + counter->mhpmcounterh_prev =3D get_ticks(true, instr); if (ctr_idx > 2) { riscv_pmu_setup_timer(env, mhpmctr_val, ctr_idx); } @@ -926,6 +929,7 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, counter->mhpmcounter_prev; target_ulong ctr_val =3D upper_half ? counter->mhpmcounterh_val : counter->mhpmcounter_val; + bool instr =3D riscv_pmu_ctr_monitor_instructions(env, ctr_idx); =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { /* @@ -946,9 +950,8 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVState = *env, target_ulong *val, * The kernel computes the perf delta by subtracting the current value= from * the value it initialized previously (ctr_val). */ - if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || - riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) { - *val =3D get_ticks(upper_half) - ctr_prev + ctr_val; + if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) || instr) { + *val =3D get_ticks(upper_half, instr) - ctr_prev + ctr_val; } else { *val =3D ctr_val; } --=20 2.43.0