[PATCH 00/65]target/riscv: Support XTheadVector extension

Huang Tao posted 65 patches 1 month, 1 week ago
target/riscv/cpu.c                            |    4 +
target/riscv/cpu.h                            |   39 +
target/riscv/cpu_bits.h                       |   18 +
target/riscv/cpu_cfg.h                        |    2 +
target/riscv/cpu_helper.c                     |    2 +-
target/riscv/csr.c                            |   42 +-
target/riscv/helper.h                         | 1067 +++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 2933 +++++++++++++
target/riscv/internals.h                      |   12 +
target/riscv/meson.build                      |    3 +
target/riscv/tcg/tcg-cpu.c                    |   33 +
target/riscv/th_csr.c                         |  250 ++
target/riscv/translate.c                      |    7 +
target/riscv/vector_helper.c                  |  306 +-
target/riscv/vector_internals.h               |  187 +
target/riscv/xtheadvector.decode              |  390 ++
target/riscv/xtheadvector_helper.c            | 3894 +++++++++++++++++
17 files changed, 8983 insertions(+), 206 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_xtheadvector.c.inc
create mode 100644 target/riscv/th_csr.c
create mode 100644 target/riscv/xtheadvector.decode
create mode 100644 target/riscv/xtheadvector_helper.c
[PATCH 00/65]target/riscv: Support XTheadVector extension
Posted by Huang Tao 1 month, 1 week ago
This patchset implements the XTheadVector extension for RISC-V on QEMU.

You can find the full description of the XTheadVector extension at:
https://github.com/RISCV-SPEC/thead-extension-spec/blob/master/xtheadvector.adoc

The XTheadvector extension is a non-standard extension for RISC-V. The
encoding space of the XTheadVector instructions overlaps with those of
the V extension.

The XTheadVector is similar to the V extension v0.7.1, so it has several
differences with the current V extension v1.0 which is supported by
QEMU.

Here is a simple list of the differences:
  * Different instructions
  * Different CSR behaviors
  * Different mask register layout
  * Different overlap policy
  * Different masked/tail element processing policy
  * Same instructions have different behaviors in detail

This patchset is based on https://github.com/alistair23/qemu/tree/riscv-to-apply.next,
relay on some former patches which are not merged into upstream yet:
  * target/riscv: Implement dynamic establishment of custom decoder
  (https://patchew.org/QEMU/20240314092158.65866-1-eric.huang@linux.alibaba.com/)
  * riscv: set vstart_eq_zero on vector insns
  (https://patchew.org/QEMU/20240313220141.427730-1-dbarboza@ventanamicro.com/)
  * riscv: thead: Add th.sxstatus CSR emulation
  (https://patchew.org/QEMU/20240329120427.684677-1-christoph.muellner@vrull.eu/)


The patch 'riscv: thead: Add th.sxstatus CSR emulation' is included in the patchset
for we need to change it to support XTheadVector csrs.

Christoph Müllner (1):
  riscv: thead: Add th.sxstatus CSR emulation

Huang Tao (64):
  target/riscv: Reuse th_csr.c to add user-mode csrs
  target/riscv: Add properties for XTheadVector extension
  target/riscv: Override some csr ops for XTheadVector
  target/riscv: Add mlen in DisasContext
  target/riscv: Implement insns decode rules for XTheadVector
  target/riscv: implement th.vsetvl{i} for XTheadVector
  target/riscv: Add strided load instructions for XTheadVector
  target/riscv: Add strided store instructions for XTheadVector
  target/riscv: Add unit-stride load instructions for XTheadVector
  target/riscv: Add unit-stride store instructions for XTheadVector
  target/riscv: Add indexed load instructions for XTheadVector
  target/riscv: Add indexed store instructions for XTheadVector
  target/riscv: Add unit-stride fault-only-first instructions for
    XTheadVector
  target/riscv: Add vector amo operations for XTheadVector
  target/riscv: Add single-width integer add and subtract instructions
    for XTheadVector
  target/riscv: Add widening integer add/subtract instructions for
    XTheadVector
  target/riscv: Add integer add-with-carry/sub-with-borrow instructions
    for XTheadVector
  target/riscv: Add bitwise logical instructions for XTheadVector
  target/riscv: Add single-width bit shift instructions for XTheadVector
  target/riscv: Add narrowing integer right shift instructions for
    XTheadVector
  target/riscv: Add integer compare instructions for XTheadVector
  target/riscv: Add integer min/max instructions for XTheadVector
  target/riscv: Add single-width integer multiply instructions for
    XTheadVector
  target/riscv: Add integer divide instructions for XTheadVector
  target/riscv: Add widening integer multiply instructions for
    XTheadVector
  target/riscv: Add single-width integer multiply-add instructions for
    XTheadVector
  target/riscv: Add widening integer multiply-add instructions for
    XTheadVector
  target/riscv: Add integer merge and move instructions for XTheadVector
  target/riscv: Add single-width saturating add and sub instructions for
    XTheadVector
  target/riscv: Add single-width average add and sub instructions for
    XTheadVector
  target/riscv: Add single-width fractional mul with rounding and
    saturation for XTheadVector
  target/riscv: Add widening saturating scaled multiply-add instructions
    for XTheadVector
  target/riscv: Add single-width scaling shift instructions for
    XTheadVector
  target/riscv: Add narrowing fixed-point clip instructions for
    XTheadVector
  target/riscv: Add single-width floating-point add/sub instructions for
    XTheadVector
  target/riscv: Add widening floating-point add/sub instructions for
    XTheadVector
  target/riscv: Add single-width floating-point multiply/divide
    instructions for XTheadVector
  target/riscv: Add widening floating-point multiply instructions for
    XTheadVector
  target/riscv: Add single-width floating-point fused multiply-add
    instructions for XTheadVector
  target/riscv: Add widening floating-point fused mul-add instructions
    for XTheadVector
  target/riscv: Add floating-pointing square-root instructions for
    XTheadVector
  target/riscv: Add floating-point MIN/MAX instructions for XTheadVector
  target/riscv: Add floating-point sign-injection instructions for
    XTheadVector
  target/riscv: Add floating-point compare instructions for XTheadVector
  target/riscv: Add floating-point classify and merge instructions for
    XTheadVector
  target/riscv: Add single-width floating-point/integer type-convert
    instructions for XTheadVector
  target/riscv: Add widening floating-point/integer type-convert
    instructions for XTheadVector
  target/riscv: Add narrowing floating-point/integer type-convert
    instructions for XTheadVector
  target/riscv: Add single-width integer reduction instructions for
    XTheadVector
  target/riscv: Add widening integer reduction instructions for
    XTheadVector
  target/riscv: Add single-width floating-point reduction instructions
    for XTheadVector
  target/riscv: Add widening floating-point reduction instructions for
    XTheadVector
  target/riscv: Add mask-register logical instructions for XTheadVector
  target/riscv: Add vector mask population count vmpopc for XTheadVector
  target/riscv: Add th.vmfirst.m for XTheadVector
  target/riscv: Add set-X-first mask bit instructrions for XTheadVector
  target/riscv: Add vector iota instruction for XTheadVector
  target/riscv: Add vector element index instruction for XTheadVector
  target/riscv: Add integer extract and scalar move instructions for
    XTheadVector
  target/riscv: Add floating-point scalar move instructions for
    XTheadVector
  target/riscv: Add vector slide instructions for XTheadVector
  target/riscv: Add vector register gather instructions for XTheadVector
  target/riscv: Add vector compress instruction for XTheadVector
  target/riscv: Enable XTheadVector extension for c906

 target/riscv/cpu.c                            |    4 +
 target/riscv/cpu.h                            |   39 +
 target/riscv/cpu_bits.h                       |   18 +
 target/riscv/cpu_cfg.h                        |    2 +
 target/riscv/cpu_helper.c                     |    2 +-
 target/riscv/csr.c                            |   42 +-
 target/riscv/helper.h                         | 1067 +++++
 .../riscv/insn_trans/trans_xtheadvector.c.inc | 2933 +++++++++++++
 target/riscv/internals.h                      |   12 +
 target/riscv/meson.build                      |    3 +
 target/riscv/tcg/tcg-cpu.c                    |   33 +
 target/riscv/th_csr.c                         |  250 ++
 target/riscv/translate.c                      |    7 +
 target/riscv/vector_helper.c                  |  306 +-
 target/riscv/vector_internals.h               |  187 +
 target/riscv/xtheadvector.decode              |  390 ++
 target/riscv/xtheadvector_helper.c            | 3894 +++++++++++++++++
 17 files changed, 8983 insertions(+), 206 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_xtheadvector.c.inc
 create mode 100644 target/riscv/th_csr.c
 create mode 100644 target/riscv/xtheadvector.decode
 create mode 100644 target/riscv/xtheadvector_helper.c

-- 
2.44.0