From nobody Fri Oct 18 04:34:12 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1712907653; cv=none; d=zohomail.com; s=zohoarc; b=OWItPjJgTEHv5lj9HETasivfDz4V+TcBaqwmhUTOUcU+ChecezskcZME7HIJMmiYN3Qs4JDPrigCzTci90tsG3GLbl2Vn9FKuzU0ARMziMo++HI/OaI+ZfVcVbB5jTTpi5vmlyOSjpRyIADwBQeYjgSKIK1vr0Oc46xnn7ea6l0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712907653; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CD1rIM6sbmEHK27xeJ6Gn+PBG5c5/nQVoK5CDrnnAhI=; b=T/7CDk+EwWUCP97uBOrn27b+WjDuAOmGR4kTg5DW5ijxWlwY0aqqBRemuquyEi8cQhOEvkgdV/AcFmfOG3KKOT3uT8KVpFW1smkieTtTpVRP9TmR/iW2z1Fkyj35DFVTfCoVcIGhq/ZqPMG8/DodRubEbrY72hrcH5LO60veLaU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712907653309369.51496090444505; Fri, 12 Apr 2024 00:40:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvBWT-0007br-S9; Fri, 12 Apr 2024 03:40:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvBWS-0007ae-OU; Fri, 12 Apr 2024 03:40:32 -0400 Received: from out30-133.freemail.mail.aliyun.com ([115.124.30.133]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvBWP-0008K2-OR; Fri, 12 Apr 2024 03:40:32 -0400 Received: from localhost.localdomain(mailfrom:eric.huang@linux.alibaba.com fp:SMTPD_---0W4NVQ9._1712907621) by smtp.aliyun-inc.com; Fri, 12 Apr 2024 15:40:22 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1712907623; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; bh=CD1rIM6sbmEHK27xeJ6Gn+PBG5c5/nQVoK5CDrnnAhI=; b=pPtwjQ6yESukCRYn31MSE4ZfutVIQ00PPJKamGYbxAhUQAASV6rl47+FPQmru1S0LvYl6/YDvjSTMrsWRkEvVTRBMkvmIJbSOIhRsrQP4ViM/deuyG9CvprfhMx+uYIQf3KSH6nBBcLSP+UU2Idz1H/AlRxPBxpnQuo7GN+CLtw= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R611e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045170; MF=eric.huang@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W4NVQ9._1712907621; From: Huang Tao To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation Date: Fri, 12 Apr 2024 15:36:31 +0800 Message-ID: <20240412073735.76413-2-eric.huang@linux.alibaba.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com> References: <20240412073735.76413-1-eric.huang@linux.alibaba.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.133; envelope-from=eric.huang@linux.alibaba.com; helo=out30-133.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1712907654010100003 From: Christoph M=C3=BCllner The th.sxstatus CSR can be used to identify available custom extension on T-Head CPUs. The CSR is documented here: https://github.com/T-head-Semi/thead-extension-spec/pull/46 An important property of this patch is, that the th.sxstatus MAEE field is not set (indicating that XTheadMaee is not available). XTheadMaee is a memory attribute extension (similar to Svpbmt) which is implemented in many T-Head CPUs (C906, C910, etc.) and utilizes bits in PTEs that are marked as reserved. QEMU maintainers prefer to not implement XTheadMaee, so we need give kernels a mechanism to identify if XTheadMaee is available in a system or not. And this patch introduces this mechanism in QEMU in a way that's compatible with real HW (i.e., probing the th.sxstatus.MAEE bit). Further context can be found on the list: https://lists.gnu.org/archive/html/qemu-devel/2024-02/msg00775.html Signed-off-by: Christoph M=C3=BCllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 3 ++ target/riscv/meson.build | 1 + target/riscv/th_csr.c | 78 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 83 insertions(+) create mode 100644 target/riscv/th_csr.c diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 193dbf7fe8..46a66cdbbb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -545,6 +545,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); + th_register_custom_csrs(cpu); #endif =20 /* inherited from parent obj via riscv_cpu_init() */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 48e67410e1..8d0b500758 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -825,4 +825,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState = *cs); uint8_t satp_mode_max_from_map(uint32_t map); const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); =20 +/* Implemented in th_csr.c */ +void th_register_custom_csrs(RISCVCPU *cpu); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/meson.build b/target/riscv/meson.build index a5e0734e7f..a4bd61e52a 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -33,6 +33,7 @@ riscv_system_ss.add(files( 'monitor.c', 'machine.c', 'pmu.c', + 'th_csr.c', 'time_helper.c', 'riscv-qmp-cmds.c', )) diff --git a/target/riscv/th_csr.c b/target/riscv/th_csr.c new file mode 100644 index 0000000000..66d260cabd --- /dev/null +++ b/target/riscv/th_csr.c @@ -0,0 +1,78 @@ +/* + * T-Head-specific CSRs. + * + * Copyright (c) 2024 VRULL GmbH + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_vendorid.h" + +#define CSR_TH_SXSTATUS 0x5c0 + +/* TH_SXSTATUS bits */ +#define TH_SXSTATUS_UCME BIT(16) +#define TH_SXSTATUS_MAEE BIT(21) +#define TH_SXSTATUS_THEADISAEE BIT(22) + +typedef struct { + int csrno; + int (*insertion_test)(RISCVCPU *cpu); + riscv_csr_operations csr_ops; +} riscv_csr; + +static RISCVException s_mode_csr(CPURISCVState *env, int csrno) +{ + if (env->debugger) + return RISCV_EXCP_NONE; + + if (env->priv >=3D PRV_S) + return RISCV_EXCP_NONE; + + return RISCV_EXCP_ILLEGAL_INST; +} + +static int test_thead_mvendorid(RISCVCPU *cpu) +{ + if (cpu->cfg.mvendorid !=3D THEAD_VENDOR_ID) + return -1; + return 0; +} + +static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* We don't set MAEE here, because QEMU does not implement MAEE. */ + *val =3D TH_SXSTATUS_UCME | TH_SXSTATUS_THEADISAEE; + return RISCV_EXCP_NONE; +} + +static riscv_csr th_csr_list[] =3D { + { + .csrno =3D CSR_TH_SXSTATUS, + .insertion_test =3D test_thead_mvendorid, + .csr_ops =3D { "th.sxstatus", s_mode_csr, read_th_sxstatus } + } +}; + +void th_register_custom_csrs(RISCVCPU *cpu) +{ + for (size_t i =3D 0; i < ARRAY_SIZE(th_csr_list); i++) { + int csrno =3D th_csr_list[i].csrno; + riscv_csr_operations *csr_ops =3D &th_csr_list[i].csr_ops; + if (!th_csr_list[i].insertion_test(cpu)) + riscv_set_csr_ops(csrno, csr_ops); + } +} --=20 2.44.0