From nobody Mon Sep 16 18:53:08 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1712914115; cv=none; d=zohomail.com; s=zohoarc; b=XsHOGOhl4scnaO+BjolSkpjrDNEdSMFmAhzyWUKBFaHUIk4xCxVAf/zNO87r5wChV8xOeKuVf+1qLpBSZaHuhmvBOwg/ZG9Tc/xJgGRFUc4r1pOTikJdWCxRvlSiNH0WnhXpAcVg4/guVPCt+kslAtZAjm6EVqmu1IUu1UwyB2U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712914115; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=u18ajQw8BnyfQfbSYOWjFV4OF+CR1EdD+IwPlrADmSY=; b=KihbQip3Mw0rYlbz4IVUsL8q6cwPwFKFBvDl9GVuvZhGceAeZpByndmZHzgBYoDhkNAwytK8fl+Gx/fdwVaOJK8vDXtAvin9cjS6NRak6RMZCuXTpXdOyo7nYyfU/KvWIc/UJ9VNTIHD+0VfN7IZLICMCyVfyWZWwxtW+PRy4Ko= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712914115732440.3799222657336; Fri, 12 Apr 2024 02:28:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvDCM-0001a6-00; Fri, 12 Apr 2024 05:27:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvDCH-0001Xs-9k; Fri, 12 Apr 2024 05:27:49 -0400 Received: from out30-110.freemail.mail.aliyun.com ([115.124.30.110]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvDCD-0003X4-3Y; Fri, 12 Apr 2024 05:27:48 -0400 Received: from localhost.localdomain(mailfrom:eric.huang@linux.alibaba.com fp:SMTPD_---0W4Novpj_1712914053) by smtp.aliyun-inc.com; Fri, 12 Apr 2024 17:27:34 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1712914055; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=u18ajQw8BnyfQfbSYOWjFV4OF+CR1EdD+IwPlrADmSY=; b=qQGukJHBu0ps21+a/jPDEDmO0OBJ5sWDwXztUD5e96fI6xjt2iN23HvZBL3nRNQGjXM+ZZa7HuFxmI1RBwqUadn6eM3lnTfdn4Aiz9uRfsG5p2RFqOhytw4hSL8Xtz+HZkpH9OcYBaqmeVoyyPbneHjj5C8IxMitaHrq1TzYQSs= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R191e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046059; MF=eric.huang@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W4Novpj_1712914053; From: Huang Tao To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, Huang Tao Subject: [PATCH 46/65] target/riscv: Add floating-point classify and merge instructions for XTheadVector Date: Fri, 12 Apr 2024 15:37:16 +0800 Message-ID: <20240412073735.76413-47-eric.huang@linux.alibaba.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com> References: <20240412073735.76413-1-eric.huang@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.110; envelope-from=eric.huang@linux.alibaba.com; helo=out30-110.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1712914117543100001 Content-Type: text/plain; charset="utf-8" The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 8 +++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 51 +++++++++++++++- target/riscv/xtheadvector_helper.c | 58 +++++++++++++++++++ 3 files changed, 114 insertions(+), 3 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5771a4fa8a..886655899e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -2189,3 +2189,11 @@ DEF_HELPER_6(th_vmford_vv_d, void, ptr, ptr, ptr, pt= r, env, i32) DEF_HELPER_6(th_vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(th_vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(th_vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_5(th_vfclass_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(th_vfclass_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(th_vfclass_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(th_vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(th_vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/risc= v/insn_trans/trans_xtheadvector.c.inc index 1e773c673e..8e928febb7 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -2143,15 +2143,60 @@ GEN_OPFVF_TRANS_TH(th_vmfgt_vf, opfvf_cmp_check_th) GEN_OPFVF_TRANS_TH(th_vmfge_vf, opfvf_cmp_check_th) GEN_OPFVF_TRANS_TH(th_vmford_vf, opfvf_cmp_check_th) =20 +/* Vector Floating-Point Classify Instruction */ +GEN_OPFV_TRANS_TH(th_vfclass_v, opfv_check_th) + +/* Vector Floating-Point Merge Instruction */ +GEN_OPFVF_TRANS_TH(th_vfmerge_vfm, opfvf_check_th) + +/* Besides of check function, th_vfmv_v_f just reuse the helper_th_vmv_v_x= */ +static bool trans_th_vfmv_v_f(DisasContext *s, arg_th_vfmv_v_f *a) +{ + if (require_xtheadvector(s) && + vext_check_isa_ill(s) && + th_check_reg(s, a->rd, false) && + (s->sew !=3D 0)) { + + TCGv_i64 t1; + + if (s->vl_eq_vlmax) { + t1 =3D tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd), + MAXSZ(s), MAXSZ(s), t1); + } else { + TCGv_ptr dest; + TCGv_i32 desc; + uint32_t data =3D FIELD_DP32(0, VDATA_TH, LMUL, s->lmul); + static gen_helper_vmv_vx_th * const fns[3] =3D { + gen_helper_th_vmv_v_x_h, + gen_helper_th_vmv_v_x_w, + gen_helper_th_vmv_v_x_d, + }; + + t1 =3D tcg_temp_new_i64(); + /* NaN-box f[rs1] */ + do_nanbox(s, t1, cpu_fpr[a->rs1]); + + dest =3D tcg_temp_new_ptr(); + desc =3D tcg_constant_i32(simd_desc(s->cfg_ptr->vlenb, + s->cfg_ptr->vlenb, data)); + tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd)); + fns[s->sew - 1](dest, t1, tcg_env, desc); + } + finalize_rvv_inst(s); + return true; + } + return false; +} + #define TH_TRANS_STUB(NAME) \ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { \ return require_xtheadvector(s); \ } =20 -TH_TRANS_STUB(th_vfclass_v) -TH_TRANS_STUB(th_vfmerge_vfm) -TH_TRANS_STUB(th_vfmv_v_f) TH_TRANS_STUB(th_vfcvt_xu_f_v) TH_TRANS_STUB(th_vfcvt_x_f_v) TH_TRANS_STUB(th_vfcvt_f_xu_v) diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector= _helper.c index 603b34a094..e31e13dff3 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -3147,3 +3147,61 @@ GEN_TH_CMP_VV_ENV(th_vmford_vv_d, uint64_t, H8, !flo= at64_unordered_quiet) GEN_TH_CMP_VF(th_vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) GEN_TH_CMP_VF(th_vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) GEN_TH_CMP_VF(th_vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) + +/* Vector Floating-Point Classify Instruction */ +#define TH_OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ + OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) + +#define GEN_TH_V(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax =3D th_maxsz(desc) / ESZ; \ + uint32_t mlen =3D th_mlen(desc); \ + uint32_t vm =3D th_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i =3D env->vstart; i < vl; i++) { \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + env->vstart =3D 0; \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ +} + +THCALL(TH_OPIVV1, th_vfclass_v_h, OP_UU_H, H2, H2, fclass_h) +THCALL(TH_OPIVV1, th_vfclass_v_w, OP_UU_W, H4, H4, fclass_s) +THCALL(TH_OPIVV1, th_vfclass_v_d, OP_UU_D, H8, H8, fclass_d) +GEN_TH_V(th_vfclass_v_h, 2, 2, clearh_th) +GEN_TH_V(th_vfclass_v_w, 4, 4, clearl_th) +GEN_TH_V(th_vfclass_v_d, 8, 8, clearq_th) + +/* Vector Floating-Point Merge Instruction */ +#define GEN_VFMERGE_VF_TH(NAME, ETYPE, H, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t mlen =3D th_mlen(desc); \ + uint32_t vm =3D th_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t esz =3D sizeof(ETYPE); \ + uint32_t vlmax =3D th_maxsz(desc) / esz; \ + uint32_t i; \ + \ + VSTART_CHECK_EARLY_EXIT(env); \ + for (i =3D env->vstart; i < vl; i++) { \ + ETYPE s2 =3D *((ETYPE *)vs2 + H(i)); \ + *((ETYPE *)vd + H(i)) \ + =3D (!vm && !th_elem_mask(v0, mlen, i) ? s2 : s1); \ + } \ + env->vstart =3D 0; \ + CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ +} + +GEN_VFMERGE_VF_TH(th_vfmerge_vfm_h, int16_t, H2, clearh_th) +GEN_VFMERGE_VF_TH(th_vfmerge_vfm_w, int32_t, H4, clearl_th) +GEN_VFMERGE_VF_TH(th_vfmerge_vfm_d, int64_t, H8, clearq_th) --=20 2.44.0