From nobody Mon Sep 16 19:02:06 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.alibaba.com ARC-Seal: i=1; a=rsa-sha256; t=1712914843; cv=none; d=zohomail.com; s=zohoarc; b=bQFW26l/t2LGSnBPmwgxPPzt4RN63Y8TTn9Dvq0VlLthuLZtyWMCqi/Af3Ivnf0jh5J604286rTYYeEppXvpYe695aIysT3fC+egx2uPXfZuPVk6GCfnKfiUnhP0CBT/08+83Y+ZqoE1HD6tWa8f29LIfjm4Ogw61QiA8FvusuE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1712914843; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JwaMqiHOkzXwc6HLXGIISXAQVZZqsuqU7z1zj4QhC1U=; b=XC2dbF2wapYjBtyE8YBcc+kKX6+hSQRa6nF9u6Tf8TpJD3ennBa9Uniq/mDWe4wrhrQIdvgkgaJfUJ7sH0xzzil2DBy8Q5eLFQa8P2dOmOo2U7AfK0qAYOpjHJysMnRPsTbYge6D9c142IrX7Q2yrhdTqNF7H+dOhduksrDY6x4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1712914843834392.0803314045355; Fri, 12 Apr 2024 02:40:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rvDO1-0007HI-JE; Fri, 12 Apr 2024 05:39:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvDNz-0007GX-AC; Fri, 12 Apr 2024 05:39:55 -0400 Received: from out30-101.freemail.mail.aliyun.com ([115.124.30.101]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rvDNw-0005Wb-6E; Fri, 12 Apr 2024 05:39:55 -0400 Received: from localhost.localdomain(mailfrom:eric.huang@linux.alibaba.com fp:SMTPD_---0W4NtKZ-_1712914781) by smtp.aliyun-inc.com; Fri, 12 Apr 2024 17:39:42 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1712914783; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=JwaMqiHOkzXwc6HLXGIISXAQVZZqsuqU7z1zj4QhC1U=; b=HyYQ4XQKpdmB3lAbgAGZxmfswsraichiQ5UH6SAbD0/ffoVHilzoWwpodN8h4XLDio94AgRgz88O4b6XAmQu0suJPW2xvia3c//d8CyrtHze3TqSk1xVG2nLqMLK4WrYl5eZ26lq2j3eNd1l27JZSyHLTrxumfWzDx8+yBjiU8E= X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R101e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046059; MF=eric.huang@linux.alibaba.com; NM=1; PH=DS; RN=9; SR=0; TI=SMTPD_---0W4NtKZ-_1712914781; From: Huang Tao To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, zhiwei_liu@linux.alibaba.com, dbarboza@ventanamicro.com, liwei1518@gmail.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, Huang Tao Subject: [PATCH 52/65] target/riscv: Add single-width floating-point reduction instructions for XTheadVector Date: Fri, 12 Apr 2024 15:37:22 +0800 Message-ID: <20240412073735.76413-53-eric.huang@linux.alibaba.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240412073735.76413-1-eric.huang@linux.alibaba.com> References: <20240412073735.76413-1-eric.huang@linux.alibaba.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=115.124.30.101; envelope-from=eric.huang@linux.alibaba.com; helo=out30-101.freemail.mail.aliyun.com X-Spam_score_int: -174 X-Spam_score: -17.5 X-Spam_bar: ----------------- X-Spam_report: (-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linux.alibaba.com) X-ZM-MESSAGEID: 1712914845808100003 Content-Type: text/plain; charset="utf-8" The instructions have the same function as RVV1.0. Overall there are only general differences between XTheadVector and RVV1.0. Signed-off-by: Huang Tao --- target/riscv/helper.h | 10 ++++ .../riscv/insn_trans/trans_xtheadvector.c.inc | 8 +-- target/riscv/xtheadvector_helper.c | 49 +++++++++++++++++++ 3 files changed, 64 insertions(+), 3 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 2cd4a7401f..24bb8479a4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -2276,3 +2276,13 @@ DEF_HELPER_6(th_vwredsumu_vs_w, void, ptr, ptr, ptr,= ptr, env, i32) DEF_HELPER_6(th_vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(th_vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(th_vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(th_vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(th_vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc b/target/risc= v/insn_trans/trans_xtheadvector.c.inc index 8a1f0e1e74..f77d76dc5e 100644 --- a/target/riscv/insn_trans/trans_xtheadvector.c.inc +++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc @@ -2397,15 +2397,17 @@ GEN_OPIVV_TRANS_TH(th_vredxor_vs, reduction_check_t= h) GEN_OPIVV_WIDEN_TRANS_TH(th_vwredsum_vs, reduction_check_th) GEN_OPIVV_WIDEN_TRANS_TH(th_vwredsumu_vs, reduction_check_th) =20 +/* Vector Single-Width Floating-Point Reduction Instructions */ +GEN_OPFVV_TRANS_TH(th_vfredsum_vs, reduction_check_th) +GEN_OPFVV_TRANS_TH(th_vfredmax_vs, reduction_check_th) +GEN_OPFVV_TRANS_TH(th_vfredmin_vs, reduction_check_th) + #define TH_TRANS_STUB(NAME) \ static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ { \ return require_xtheadvector(s); \ } =20 -TH_TRANS_STUB(th_vfredsum_vs) -TH_TRANS_STUB(th_vfredmin_vs) -TH_TRANS_STUB(th_vfredmax_vs) TH_TRANS_STUB(th_vfwredsum_vs) TH_TRANS_STUB(th_vmand_mm) TH_TRANS_STUB(th_vmnand_mm) diff --git a/target/riscv/xtheadvector_helper.c b/target/riscv/xtheadvector= _helper.c index f802b2c5ac..2a241aed65 100644 --- a/target/riscv/xtheadvector_helper.c +++ b/target/riscv/xtheadvector_helper.c @@ -3410,3 +3410,52 @@ GEN_TH_RED(th_vwredsum_vs_w, int64_t, int32_t, H8, H= 4, TH_ADD, clearq_th) GEN_TH_RED(th_vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, TH_ADD, clearh_th) GEN_TH_RED(th_vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, TH_ADD, clearl_t= h) GEN_TH_RED(th_vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, TH_ADD, clearq_t= h) + +/* Vector Single-Width Floating-Point Reduction Instructions */ +#define GEN_TH_FRED(NAME, TD, TS2, HD, HS2, OP, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint32_t mlen =3D th_mlen(desc); \ + uint32_t vm =3D th_vm(desc); \ + uint32_t vl =3D env->vl; \ + uint32_t i; \ + uint32_t tot =3D env_archcpu(env)->cfg.vlenb; \ + TD s1 =3D *((TD *)vs1 + HD(0)); \ + \ + for (i =3D env->vstart; i < vl; i++) { \ + TS2 s2 =3D *((TS2 *)vs2 + HS2(i)); \ + if (!vm && !th_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + s1 =3D OP(s1, (TD)s2, &env->fp_status); \ + } \ + *((TD *)vd + HD(0)) =3D s1; \ + env->vstart =3D 0; \ + CLEAR_FN(vd, 1, sizeof(TD), tot); \ +} + +/* Unordered sum */ +GEN_TH_FRED(th_vfredsum_vs_h, uint16_t, uint16_t, H2, H2, + float16_add, clearh_th) +GEN_TH_FRED(th_vfredsum_vs_w, uint32_t, uint32_t, H4, H4, + float32_add, clearl_th) +GEN_TH_FRED(th_vfredsum_vs_d, uint64_t, uint64_t, H8, H8, + float64_add, clearq_th) + +/* Maximum value */ +GEN_TH_FRED(th_vfredmax_vs_h, uint16_t, uint16_t, H2, H2, + float16_maxnum, clearh_th) +GEN_TH_FRED(th_vfredmax_vs_w, uint32_t, uint32_t, H4, H4, + float32_maxnum, clearl_th) +GEN_TH_FRED(th_vfredmax_vs_d, uint64_t, uint64_t, H8, H8, + float64_maxnum, clearq_th) + +/* Minimum value */ +GEN_TH_FRED(th_vfredmin_vs_h, uint16_t, uint16_t, H2, H2, + float16_minnum, clearh_th) +GEN_TH_FRED(th_vfredmin_vs_w, uint32_t, uint32_t, H4, H4, + float32_minnum, clearl_th) +GEN_TH_FRED(th_vfredmin_vs_d, uint64_t, uint64_t, H8, H8, + float64_minnum, clearq_th) --=20 2.44.0