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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dc; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1713100043886100001 Content-Type: text/plain; charset="utf-8" This device implements the IM120417002 colors shield v1.1 for Arduino (which relies on the DM163 8x3-channel led driving logic) and features a simple display of an 8x8 RGB matrix. The columns of the matrix are driven by the DM163 and the rows are driven externally. Acked-by: Alistair Francis Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol --- docs/system/arm/b-l475e-iot01a.rst | 3 +- include/hw/display/dm163.h | 58 +++++ hw/display/dm163.c | 333 +++++++++++++++++++++++++++++ hw/display/Kconfig | 3 + hw/display/meson.build | 1 + hw/display/trace-events | 14 ++ 6 files changed, 411 insertions(+), 1 deletion(-) create mode 100644 include/hw/display/dm163.h create mode 100644 hw/display/dm163.c diff --git a/docs/system/arm/b-l475e-iot01a.rst b/docs/system/arm/b-l475e-i= ot01a.rst index 0afef8e4f4..91de5e82fc 100644 --- a/docs/system/arm/b-l475e-iot01a.rst +++ b/docs/system/arm/b-l475e-iot01a.rst @@ -12,13 +12,14 @@ USART, I2C, SPI, CAN and USB OTG, as well as a variety = of sensors. Supported devices """"""""""""""""" =20 -Currently B-L475E-IOT01A machine's only supports the following devices: +Currently B-L475E-IOT01A machines support the following devices: =20 - Cortex-M4F based STM32L4x5 SoC - STM32L4x5 EXTI (Extended interrupts and events controller) - STM32L4x5 SYSCFG (System configuration controller) - STM32L4x5 RCC (Reset and clock control) - STM32L4x5 GPIOs (General-purpose I/Os) +- optional 8x8 led display (based on DM163 driver) =20 Missing devices """"""""""""""" diff --git a/include/hw/display/dm163.h b/include/hw/display/dm163.h new file mode 100644 index 0000000000..00d0504640 --- /dev/null +++ b/include/hw/display/dm163.h @@ -0,0 +1,58 @@ +/* + * QEMU DM163 8x3-channel constant current led driver + * driving columns of associated 8x8 RGB matrix. + * + * Copyright (C) 2024 Samuel Tardieu + * Copyright (C) 2024 Arnaud Minier + * Copyright (C) 2024 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_DISPLAY_DM163_H +#define HW_DISPLAY_DM163_H + +#include "qom/object.h" +#include "hw/qdev-core.h" + +#define TYPE_DM163 "dm163" +OBJECT_DECLARE_SIMPLE_TYPE(DM163State, DM163); + +#define DM163_NUM_LEDS 24 +#define RGB_MATRIX_NUM_ROWS 8 +#define RGB_MATRIX_NUM_COLS (DM163_NUM_LEDS / 3) +#define COLOR_BUFFER_SIZE RGB_MATRIX_NUM_ROWS + +typedef struct DM163State { + DeviceState parent_obj; + + /* DM163 driver */ + uint64_t bank0_shift_register[3]; + uint64_t bank1_shift_register[3]; + uint16_t latched_outputs[DM163_NUM_LEDS]; + uint16_t outputs[DM163_NUM_LEDS]; + qemu_irq sout; + + uint8_t sin; + uint8_t dck; + uint8_t rst_b; + uint8_t lat_b; + uint8_t selbk; + uint8_t en_b; + + /* IM120417002 colors shield */ + uint8_t activated_rows; + + /* 8x8 RGB matrix */ + QemuConsole *console; + uint8_t redraw; + /* Rows currently being displayed on the matrix. */ + /* The last row is filled with 0 (turned off row) */ + uint32_t buffer[COLOR_BUFFER_SIZE + 1][RGB_MATRIX_NUM_COLS]; + uint8_t last_buffer_idx; + uint8_t buffer_idx_of_row[RGB_MATRIX_NUM_ROWS]; + /* Used to simulate retinal persistence of rows */ + uint8_t age_of_row[RGB_MATRIX_NUM_ROWS]; +} DM163State; + +#endif /* HW_DISPLAY_DM163_H */ diff --git a/hw/display/dm163.c b/hw/display/dm163.c new file mode 100644 index 0000000000..d4e89dd344 --- /dev/null +++ b/hw/display/dm163.c @@ -0,0 +1,333 @@ +/* + * QEMU DM163 8x3-channel constant current led driver + * driving columns of associated 8x8 RGB matrix. + * + * Copyright (C) 2024 Samuel Tardieu + * Copyright (C) 2024 Arnaud Minier + * Copyright (C) 2024 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * The reference used for the DM163 is the following : + * http://www.siti.com.tw/product/spec/LED/DM163.pdf + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/display/dm163.h" +#include "ui/console.h" +#include "trace.h" + +#define LED_SQUARE_SIZE 100 +/* Number of frames a row stays visible after being turned off. */ +#define ROW_PERSISTENCE 3 +#define TURNED_OFF_ROW COLOR_BUFFER_SIZE + +static const VMStateDescription vmstate_dm163 =3D { + .name =3D TYPE_DM163, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT64_ARRAY(bank0_shift_register, DM163State, 3), + VMSTATE_UINT64_ARRAY(bank1_shift_register, DM163State, 3), + VMSTATE_UINT16_ARRAY(latched_outputs, DM163State, DM163_NUM_LEDS), + VMSTATE_UINT16_ARRAY(outputs, DM163State, DM163_NUM_LEDS), + VMSTATE_UINT8(dck, DM163State), + VMSTATE_UINT8(en_b, DM163State), + VMSTATE_UINT8(lat_b, DM163State), + VMSTATE_UINT8(rst_b, DM163State), + VMSTATE_UINT8(selbk, DM163State), + VMSTATE_UINT8(sin, DM163State), + VMSTATE_UINT8(activated_rows, DM163State), + VMSTATE_UINT32_2DARRAY(buffer, DM163State, + COLOR_BUFFER_SIZE + 1, RGB_MATRIX_NUM_COLS), + VMSTATE_UINT8(last_buffer_idx, DM163State), + VMSTATE_UINT8_ARRAY(buffer_idx_of_row, DM163State, RGB_MATRIX_NUM_= ROWS), + VMSTATE_UINT8_ARRAY(age_of_row, DM163State, RGB_MATRIX_NUM_ROWS), + VMSTATE_END_OF_LIST() + } +}; + +static void dm163_reset_hold(Object *obj) +{ + DM163State *s =3D DM163(obj); + + s->sin =3D 0; + s->dck =3D 0; + s->rst_b =3D 0; + /* Ensuring the first falling edge of lat_b isn't missed */ + s->lat_b =3D 1; + s->selbk =3D 0; + s->en_b =3D 0; + /* Reset stops the PWM, not the shift and latched registers. */ + memset(s->outputs, 0, sizeof(s->outputs)); + + s->activated_rows =3D 0; + s->redraw =3D 0; + trace_dm163_redraw(s->redraw); + for (unsigned i =3D 0; i < COLOR_BUFFER_SIZE + 1; i++) { + memset(s->buffer[i], 0, sizeof(s->buffer[0])); + } + s->last_buffer_idx =3D 0; + memset(s->buffer_idx_of_row, TURNED_OFF_ROW, sizeof(s->buffer_idx_of_r= ow)); + memset(s->age_of_row, 0, sizeof(s->age_of_row)); +} + +static void dm163_dck_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s =3D DM163(opaque); + + if (new_state && !s->dck) { + /* + * On raising dck, sample selbk to get the bank to use, and + * sample sin for the bit to enter into the bank shift buffer. + */ + uint64_t *sb =3D + s->selbk ? s->bank1_shift_register : s->bank0_shift_register; + /* Output the outgoing bit on sout */ + const bool sout =3D (s->selbk ? sb[2] & MAKE_64BIT_MASK(63, 1) : + sb[2] & MAKE_64BIT_MASK(15, 1)) !=3D 0; + qemu_set_irq(s->sout, sout); + /* Enter sin into the shift buffer */ + sb[2] =3D (sb[2] << 1) | ((sb[1] >> 63) & 1); + sb[1] =3D (sb[1] << 1) | ((sb[0] >> 63) & 1); + sb[0] =3D (sb[0] << 1) | s->sin; + } + + s->dck =3D new_state; + trace_dm163_dck(new_state); +} + +static void dm163_propagate_outputs(DM163State *s) +{ + s->last_buffer_idx =3D (s->last_buffer_idx + 1) % COLOR_BUFFER_SIZE; + /* Values are output when reset is high and enable is low. */ + if (s->rst_b && !s->en_b) { + memcpy(s->outputs, s->latched_outputs, sizeof(s->outputs)); + } else { + memset(s->outputs, 0, sizeof(s->outputs)); + } + for (unsigned x =3D 0; x < RGB_MATRIX_NUM_COLS; x++) { + trace_dm163_channels(3 * x, (uint8_t)(s->outputs[3 * x] >> 6)); + trace_dm163_channels(3 * x + 1, (uint8_t)(s->outputs[3 * x + 1] >>= 6)); + trace_dm163_channels(3 * x + 2, (uint8_t)(s->outputs[3 * x + 2] >>= 6)); + s->buffer[s->last_buffer_idx][x] =3D + (s->outputs[3 * x + 2] >> 6) | + ((s->outputs[3 * x + 1] << 2) & 0xFF00) | + (((uint32_t)s->outputs[3 * x] << 10) & 0xFF0000); + } + for (unsigned row =3D 0; row < RGB_MATRIX_NUM_ROWS; row++) { + if (s->activated_rows & (1 << row)) { + s->buffer_idx_of_row[row] =3D s->last_buffer_idx; + s->redraw |=3D (1 << row); + trace_dm163_redraw(s->redraw); + } + } +} + +static void dm163_en_b_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s =3D DM163(opaque); + + s->en_b =3D new_state; + dm163_propagate_outputs(s); + trace_dm163_en_b(new_state); +} + +static inline uint8_t dm163_bank0(const DM163State *s, uint8_t led) +{ + /* + * Bank 1 uses 6 bits per led, so a value may be stored accross + * two uint64_t entries. + */ + const uint8_t low_bit =3D 6 * led; + const uint8_t low_word =3D low_bit / 64; + const uint8_t high_word =3D (low_bit + 5) / 64; + const uint8_t low_shift =3D low_bit % 64; + + if (low_word =3D=3D high_word) { + /* Simple case: the value belongs to one entry. */ + return (s->bank0_shift_register[low_word] & + MAKE_64BIT_MASK(low_shift, 6)) >> low_shift; + } + + const uint8_t bits_in_low_word =3D 64 - low_shift; + const uint8_t bits_in_high_word =3D 6 - bits_in_low_word; + return ((s->bank0_shift_register[low_word] & + MAKE_64BIT_MASK(low_shift, bits_in_low_word)) >> + low_shift) | + ((s->bank0_shift_register[high_word] & + MAKE_64BIT_MASK(0, bits_in_high_word)) + << bits_in_low_word); +} + +static inline uint8_t dm163_bank1(const DM163State *s, uint8_t led) +{ + const uint64_t entry =3D s->bank1_shift_register[led / 8]; + const unsigned shift =3D 8 * (led % 8); + return (entry & MAKE_64BIT_MASK(shift, 8)) >> shift; +} + +static void dm163_lat_b_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s =3D DM163(opaque); + + if (s->lat_b && !new_state) { + for (int led =3D 0; led < DM163_NUM_LEDS; led++) { + s->latched_outputs[led] =3D dm163_bank0(s, led) * dm163_bank1(= s, led); + } + dm163_propagate_outputs(s); + } + + s->lat_b =3D new_state; + trace_dm163_lat_b(new_state); +} + +static void dm163_rst_b_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s =3D DM163(opaque); + + s->rst_b =3D new_state; + dm163_propagate_outputs(s); + trace_dm163_rst_b(new_state); +} + +static void dm163_selbk_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s =3D DM163(opaque); + + s->selbk =3D new_state; + trace_dm163_selbk(new_state); +} + +static void dm163_sin_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s =3D DM163(opaque); + + s->sin =3D new_state; + trace_dm163_sin(new_state); +} + +static void dm163_rows_gpio_handler(void *opaque, int line, int new_state) +{ + DM163State *s =3D DM163(opaque); + + if (new_state) { + s->activated_rows |=3D (1 << line); + s->buffer_idx_of_row[line] =3D s->last_buffer_idx; + s->redraw |=3D (1 << line); + trace_dm163_redraw(s->redraw); + } else { + s->activated_rows &=3D ~(1 << line); + s->age_of_row[line] =3D ROW_PERSISTENCE; + } + trace_dm163_activated_rows(s->activated_rows); +} + +static void dm163_invalidate_display(void *opaque) +{ + DM163State *s =3D (DM163State *)opaque; + s->redraw =3D 0xFF; + trace_dm163_redraw(s->redraw); +} + +static void update_age_of_row(DM163State *s, unsigned row) +{ + if (s->age_of_row[row]) { + s->age_of_row[row]--; + } else { + /* + * If the ROW_PERSISTENCE delay is up, + * the row is turned off. + */ + s->buffer_idx_of_row[row] =3D TURNED_OFF_ROW; + s->redraw |=3D (1 << row); + trace_dm163_redraw(s->redraw); + } +} + +static uint32_t *update_display_of_row(DM163State *s, uint32_t *dest, + unsigned row) +{ + for (unsigned _ =3D 0; _ < LED_SQUARE_SIZE; _++) { + for (int x =3D RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE - 1; x >=3D 0= ; x--) { + /* UI layer guarantees that there's 32 bits per pixel (Mar 202= 4) */ + *dest++ =3D s->buffer[s->buffer_idx_of_row[row]][x / LED_SQUAR= E_SIZE]; + } + } + + dpy_gfx_update(s->console, 0, LED_SQUARE_SIZE * row, + RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, LED_SQUARE_SIZE= ); + s->redraw &=3D ~(1 << row); + trace_dm163_redraw(s->redraw); + + return dest; +} + +static void dm163_update_display(void *opaque) +{ + DM163State *s =3D (DM163State *)opaque; + DisplaySurface *surface =3D qemu_console_surface(s->console); + uint32_t *dest; + + dest =3D surface_data(surface); + for (unsigned row =3D 0; row < RGB_MATRIX_NUM_ROWS; row++) { + update_age_of_row(s, row); + if (!extract8(s->redraw, row, 1)) { + dest +=3D LED_SQUARE_SIZE * LED_SQUARE_SIZE * RGB_MATRIX_NUM_C= OLS; + continue; + } + dest =3D update_display_of_row(s, dest, row); + } +} + +static const GraphicHwOps dm163_ops =3D { + .invalidate =3D dm163_invalidate_display, + .gfx_update =3D dm163_update_display, +}; + +static void dm163_realize(DeviceState *dev, Error **errp) +{ + DM163State *s =3D DM163(dev); + + qdev_init_gpio_in(dev, dm163_rows_gpio_handler, 8); + qdev_init_gpio_in(dev, dm163_sin_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_dck_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_rst_b_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_lat_b_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_selbk_gpio_handler, 1); + qdev_init_gpio_in(dev, dm163_en_b_gpio_handler, 1); + qdev_init_gpio_out_named(dev, &s->sout, "sout", 1); + + s->console =3D graphic_console_init(dev, 0, &dm163_ops, s); + qemu_console_resize(s->console, RGB_MATRIX_NUM_COLS * LED_SQUARE_SIZE, + RGB_MATRIX_NUM_ROWS * LED_SQUARE_SIZE); +} + +static void dm163_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->desc =3D "DM163"; + dc->vmsd =3D &vmstate_dm163; + dc->realize =3D dm163_realize; + rc->phases.hold =3D dm163_reset_hold; + set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); +} + +static const TypeInfo dm163_types[] =3D { + { + .name =3D TYPE_DM163, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(DM163State), + .class_init =3D dm163_class_init + } +}; + +DEFINE_TYPES(dm163_types) diff --git a/hw/display/Kconfig b/hw/display/Kconfig index 234c7de027..a4552c8ed7 100644 --- a/hw/display/Kconfig +++ b/hw/display/Kconfig @@ -140,3 +140,6 @@ config XLNX_DISPLAYPORT bool # defaults to "N", enabled by specific boards depends on PIXMAN + +config DM163 + bool diff --git a/hw/display/meson.build b/hw/display/meson.build index f93a69f70f..71e489308e 100644 --- a/hw/display/meson.build +++ b/hw/display/meson.build @@ -38,6 +38,7 @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('ne= xt-fb.c')) =20 system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c')) system_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-dmabuf.c')) +system_ss.add(when: 'CONFIG_DM163', if_true: files('dm163.c')) =20 if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or config_all_devices.has_key('CONFIG_VGA_PCI') or diff --git a/hw/display/trace-events b/hw/display/trace-events index 2336a0ca15..fc7cbdcd36 100644 --- a/hw/display/trace-events +++ b/hw/display/trace-events @@ -177,3 +177,17 @@ macfb_ctrl_write(uint64_t addr, uint64_t value, unsign= ed int size) "addr 0x%"PRI macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32 macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32 macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting= mode to width %"PRId32 " height %"PRId32 " size %d" + +# dm163.c +dm163_redraw(uint8_t redraw) "0x%02x" +dm163_dck(int new_state) "dck : %d" +dm163_en_b(int new_state) "en_b : %d" +dm163_rst_b(int new_state) "rst_b : %d" +dm163_lat_b(int new_state) "lat_b : %d" +dm163_sin(int new_state) "sin : %d" +dm163_selbk(int new_state) "selbk : %d" +dm163_activated_rows(int new_state) "Activated rows : 0x%" PRIx32 "" +dm163_bits_ppi(unsigned dest_width) "dest_width : %u" +dm163_leds(int led, uint32_t value) "led %d: 0x%x" +dm163_channels(int channel, uint8_t value) "channel %d: 0x%x" +dm163_refresh_rate(uint32_t rr) "refresh rate %d" --=20 2.43.2 From nobody Fri May 17 05:35:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1713100071; cv=none; d=zohomail.com; s=zohoarc; b=PXQFiw1tRMHqqBylqkxmFOy7sVHHZCXBaFjRFOS/1+LpLlLAjCNnwIFe0R3YGodfPajer1O4a+v0Urs3iMQ9C5aer2qsThmnr1OFfF7sA0MgZ2n8E1AYPlTN/HhJ6jwT7nVAUurT+QeJn2TmoQb9ur+adTuTjOJNO79TeYf8q3o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1713100071; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/o1ab/cxfRN6X232LswwPlcMA4iU/ZqxyADyzyD45ek=; b=JGJCJvLDy7oRN2W04hluyUyKdu7qG3KB8RYRo0ssHUHj2pUqvKtHbgB5WKXwaT2GQS9cCgql/GN8eaczkUZRjcmsYcbBkOpN8j+odZnsc4WlksdfPVNR7fzodjzOJ9Iam1lSvnCMBsZdKh0SxMZk3sCcBcemh2ooLpu6f7zKoZU= ARC-Authentication-Results: i=1; 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Sun, 14 Apr 2024 15:06:18 +0200 (CEST) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10032) with ESMTP id oWntk_Dx0LQf; Sun, 14 Apr 2024 15:06:17 +0200 (CEST) Received: from localhost (localhost [IPv6:::1]) by zproxy1.enst.fr (Postfix) with ESMTP id D375CC062F; Sun, 14 Apr 2024 15:06:17 +0200 (CEST) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id 7dghrslxCNKr; Sun, 14 Apr 2024 15:06:17 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy1.enst.fr (Postfix) with ESMTPSA id D923BC0593; Sun, 14 Apr 2024 15:06:16 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy1.enst.fr D375CC062F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1713099977; bh=/o1ab/cxfRN6X232LswwPlcMA4iU/ZqxyADyzyD45ek=; h=From:To:Date:Message-ID:MIME-Version; b=m2C8M+I6hRKb9bitarjXjFymZzOj9vLOb9fYRqt6Q1ymlP7lpWEViYkQUEjQkIq3g 7o7h/OQtFE3BbWLVz+2ScwYPdP+duZGNLGFSDPrkHYy7MWzTqoAaFeZMm4SIjib7rm /DkL2Z1EM/jN51BLhBJnMBF3lXzFNbLcS0vxdL1I= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Thomas Huth , =?UTF-8?q?In=C3=A8s=20Varhol?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-arm@nongnu.org, Laurent Vivier , Samuel Tardieu , Arnaud Minier , Peter Maydell Subject: [PATCH v4 2/5] hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC Date: Sun, 14 Apr 2024 15:05:45 +0200 Message-ID: <20240414130604.182059-3-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> References: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dc; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1713100072943100007 Content-Type: text/plain; charset="utf-8" Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC to the optional DM163 display from the board code (GPIOs outputs need to be connected to both SYSCFG inputs and DM163 inputs). STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/stm32l4x5_soc.c | 6 ++++-- tests/qtest/stm32l4x5_gpio-test.c | 12 +++++++----- tests/qtest/stm32l4x5_syscfg-test.c | 16 +++++++++------- 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/arm/stm32l4x5_soc.c b/hw/arm/stm32l4x5_soc.c index 40e294f838..c4b45e6956 100644 --- a/hw/arm/stm32l4x5_soc.c +++ b/hw/arm/stm32l4x5_soc.c @@ -1,8 +1,8 @@ /* * STM32L4x5 SoC family * - * Copyright (c) 2023 Arnaud Minier - * Copyright (c) 2023 In=C3=A8s Varhol + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 In=C3=A8s Varhol * * SPDX-License-Identifier: GPL-2.0-or-later * @@ -221,6 +221,8 @@ static void stm32l4x5_soc_realize(DeviceState *dev_soc,= Error **errp) } } =20 + qdev_pass_gpios(DEVICE(&s->syscfg), dev_soc, NULL); + /* EXTI device */ busdev =3D SYS_BUS_DEVICE(&s->exti); if (!sysbus_realize(busdev, errp)) { diff --git a/tests/qtest/stm32l4x5_gpio-test.c b/tests/qtest/stm32l4x5_gpio= -test.c index 0f6bda54d3..495a6fc413 100644 --- a/tests/qtest/stm32l4x5_gpio-test.c +++ b/tests/qtest/stm32l4x5_gpio-test.c @@ -43,6 +43,8 @@ #define OTYPER_PUSH_PULL 0 #define OTYPER_OPEN_DRAIN 1 =20 +#define SYSCFG "/machine/soc" + const uint32_t moder_reset[NUM_GPIOS] =3D { 0xABFFFFFF, 0xFFFFFEBF, @@ -284,7 +286,7 @@ static void test_gpio_output_mode(const void *data) uint32_t gpio =3D test_gpio_addr(data); unsigned int gpio_id =3D get_gpio_id(gpio); =20 - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); =20 /* Set a bit in ODR and check nothing happens */ gpio_set_bit(gpio, ODR, pin, 1); @@ -319,7 +321,7 @@ static void test_gpio_input_mode(const void *data) uint32_t gpio =3D test_gpio_addr(data); unsigned int gpio_id =3D get_gpio_id(gpio); =20 - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); =20 /* Configure a line as input, raise it, and check that the pin is high= */ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); @@ -348,7 +350,7 @@ static void test_pull_up_pull_down(const void *data) uint32_t gpio =3D test_gpio_addr(data); unsigned int gpio_id =3D get_gpio_id(gpio); =20 - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); =20 /* Configure a line as input with pull-up, check the line is set high = */ gpio_set_2bits(gpio, MODER, pin, MODER_INPUT); @@ -378,7 +380,7 @@ static void test_push_pull(const void *data) uint32_t gpio =3D test_gpio_addr(data); uint32_t gpio2 =3D GPIO_BASE_ADDR + (GPIO_H - gpio); =20 - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); =20 /* Setting a line high externally, configuring it in push-pull output = */ /* And checking the pin was disconnected */ @@ -425,7 +427,7 @@ static void test_open_drain(const void *data) uint32_t gpio =3D test_gpio_addr(data); uint32_t gpio2 =3D GPIO_BASE_ADDR + (GPIO_H - gpio); =20 - qtest_irq_intercept_in(global_qtest, "/machine/soc/syscfg"); + qtest_irq_intercept_in(global_qtest, SYSCFG); =20 /* Setting a line high externally, configuring it in open-drain output= */ /* And checking the pin was disconnected */ diff --git a/tests/qtest/stm32l4x5_syscfg-test.c b/tests/qtest/stm32l4x5_sy= scfg-test.c index ed4801798d..eed9d5940b 100644 --- a/tests/qtest/stm32l4x5_syscfg-test.c +++ b/tests/qtest/stm32l4x5_syscfg-test.c @@ -1,8 +1,8 @@ /* * QTest testcase for STM32L4x5_SYSCFG * - * Copyright (c) 2023 Arnaud Minier - * Copyright (c) 2023 In=C3=A8s Varhol + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 In=C3=A8s Varhol * * This work is licensed under the terms of the GNU GPL, version 2 or late= r. * See the COPYING file in the top-level directory. @@ -25,6 +25,9 @@ #define SYSCFG_SWPR2 0x28 #define INVALID_ADDR 0x2C =20 +#define EXTI "/machine/soc/exti" +#define SYSCFG "/machine/soc" + static void syscfg_writel(unsigned int offset, uint32_t value) { writel(SYSCFG_BASE_ADDR + offset, value); @@ -37,8 +40,7 @@ static uint32_t syscfg_readl(unsigned int offset) =20 static void syscfg_set_irq(int num, int level) { - qtest_set_irq_in(global_qtest, "/machine/soc/syscfg", - NULL, num, level); + qtest_set_irq_in(global_qtest, SYSCFG, NULL, num, level); } =20 static void system_reset(void) @@ -197,7 +199,7 @@ static void test_interrupt(void) * Test that GPIO rising lines result in an irq * with the right configuration */ - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); + qtest_irq_intercept_in(global_qtest, EXTI); =20 /* GPIOA is the default source for EXTI lines 0 to 15 */ =20 @@ -230,7 +232,7 @@ static void test_irq_pin_multiplexer(void) * Test that syscfg irq sets the right exti irq */ =20 - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); + qtest_irq_intercept_in(global_qtest, EXTI); =20 syscfg_set_irq(0, 1); =20 @@ -257,7 +259,7 @@ static void test_irq_gpio_multiplexer(void) * Test that an irq is generated only by the right GPIO */ =20 - qtest_irq_intercept_in(global_qtest, "/machine/soc/exti"); + qtest_irq_intercept_in(global_qtest, EXTI); =20 /* GPIOA is the default source for EXTI lines 0 to 15 */ =20 --=20 2.43.2 From nobody Fri May 17 05:35:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1713100074; cv=none; d=zohomail.com; s=zohoarc; b=e1AWiJkHU5cnmlMnfFboknPv0LjD+KfChDm/qos/3/J3ucOo4QsfP37PcESBNcILLcMjn4x/F5M8bxtDcjmdzFoh5TmGqtu0WYncbI4NlvCgz8xK1cR3LALFJQUF7Ohg2yKCAuTg+1Nf66lTRElz5CsjlH7bkO0nGjuHW7vfsG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1713100074; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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t=1713099978; bh=j1OLjRXz8cKZbnXoeuqFRRV9nutmUnwXbF7aVzmCyuQ=; h=From:To:Date:Message-ID:MIME-Version; b=l57prrSDt+1kH/NGPrSTRu/QqzgRBNtS6XpB6qA6/jsKKDbrsA6hVO6IVAjtoPbyX Y6PW3dbwrH32Qlnf5XFwmFPgS5D14Jr3SZXaZ4F4CRu9cGp7lINJK1hm7e9CBtDOTz tZSG0zinB6fWGVEl6oRUmSu73tIST0TKWFRmHuhA= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Thomas Huth , =?UTF-8?q?In=C3=A8s=20Varhol?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-arm@nongnu.org, Laurent Vivier , Samuel Tardieu , Arnaud Minier , Peter Maydell Subject: [PATCH v4 3/5] hw/arm : Create Bl475eMachineState Date: Sun, 14 Apr 2024 15:05:46 +0200 Message-ID: <20240414130604.182059-4-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> References: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.220; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1713100074921100009 Content-Type: text/plain; charset="utf-8" Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/b-l475e-iot01a.c | 44 +++++++++++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index d862aa43fc..2b570b3e09 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -2,8 +2,8 @@ * B-L475E-IOT01A Discovery Kit machine * (B-L475E-IOT01A IoT Node) * - * Copyright (c) 2023 Arnaud Minier - * Copyright (c) 2023 In=C3=A8s Varhol + * Copyright (c) 2024 Arnaud Minier + * Copyright (c) 2024 In=C3=A8s Varhol * * SPDX-License-Identifier: GPL-2.0-or-later * @@ -32,33 +32,51 @@ =20 /* B-L475E-IOT01A implementation is derived from netduinoplus2 */ =20 -static void b_l475e_iot01a_init(MachineState *machine) +#define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a") +OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A) + +typedef struct Bl475eMachineState { + MachineState parent_obj; + + Stm32l4x5SocState soc; +} Bl475eMachineState; + +static void bl475e_init(MachineState *machine) { + Bl475eMachineState *s =3D B_L475E_IOT01A(machine); const Stm32l4x5SocClass *sc; - DeviceState *dev; =20 - dev =3D qdev_new(TYPE_STM32L4X5XG_SOC); - object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + object_initialize_child(OBJECT(machine), "soc", &s->soc, + TYPE_STM32L4X5XG_SOC); + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); =20 - sc =3D STM32L4X5_SOC_GET_CLASS(dev); + sc =3D STM32L4X5_SOC_GET_CLASS(&s->soc); armv7m_load_kernel(ARM_CPU(first_cpu), - machine->kernel_filename, - 0, sc->flash_size); + machine->kernel_filename, 0, sc->flash_size); } =20 -static void b_l475e_iot01a_machine_init(MachineClass *mc) +static void bl475e_machine_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); static const char *machine_valid_cpu_types[] =3D { ARM_CPU_TYPE_NAME("cortex-m4"), NULL }; mc->desc =3D "B-L475E-IOT01A Discovery Kit (Cortex-M4)"; - mc->init =3D b_l475e_iot01a_init; + mc->init =3D bl475e_init; mc->valid_cpu_types =3D machine_valid_cpu_types; =20 /* SRAM pre-allocated as part of the SoC instantiation */ mc->default_ram_size =3D 0; } =20 -DEFINE_MACHINE("b-l475e-iot01a", b_l475e_iot01a_machine_init) +static const TypeInfo bl475e_machine_type[] =3D { + { + .name =3D TYPE_B_L475E_IOT01A, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(Bl475eMachineState), + .class_init =3D bl475e_machine_init, + } +}; + +DEFINE_TYPES(bl475e_machine_type) --=20 2.43.2 From nobody Fri May 17 05:35:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer2=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=telecom-paris.fr ARC-Seal: i=1; a=rsa-sha256; t=1713100069; cv=none; d=zohomail.com; s=zohoarc; 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Sun, 14 Apr 2024 15:06:19 +0200 (CEST) Received: from zproxy1.enst.fr ([IPv6:::1]) by localhost (zproxy1.enst.fr [IPv6:::1]) (amavis, port 10026) with ESMTP id iCvsSfLUBIkY; Sun, 14 Apr 2024 15:06:19 +0200 (CEST) Received: from inesv-Inspiron-3501.enst.fr (unknown [IPv6:2a04:8ec0:0:124::190c]) by zproxy1.enst.fr (Postfix) with ESMTPSA id D8B20C062F; Sun, 14 Apr 2024 15:06:18 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.10.3 zproxy1.enst.fr C61B1C0593 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=telecom-paris.fr; s=A35C7578-1106-11E5-A17F-C303FDDA8F2E; t=1713099979; bh=sz1BGVmIACYlzwd9H/duf2WENPV2B8VnvMAZo+SigIc=; h=From:To:Date:Message-ID:MIME-Version; b=Mg7NunSapCeRs1cXkmGq8kjGwlHxvFfjfCbWPIXhrV0xTNLXSl+AOThzuaVZgU2zt JW7w7hPVa2DUQU3JHM4QZKkIP/yEQqo6iNqQDx7LgmccIhir500poBEeif8y0dy7cv rhznQYxp8nibKkjjUNZXM1G1SI4yQNXGjukR7NRE= X-Virus-Scanned: amavis at enst.fr From: =?UTF-8?q?In=C3=A8s=20Varhol?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Thomas Huth , =?UTF-8?q?In=C3=A8s=20Varhol?= , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , qemu-arm@nongnu.org, Laurent Vivier , Samuel Tardieu , Arnaud Minier , Peter Maydell Subject: [PATCH v4 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A Date: Sun, 14 Apr 2024 15:05:47 +0200 Message-ID: <20240414130604.182059-5-ines.varhol@telecom-paris.fr> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> References: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:660:330f:2::dc; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1713100070921100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++-- hw/arm/Kconfig | 1 + 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c index 2b570b3e09..6f0bf68ca6 100644 --- a/hw/arm/b-l475e-iot01a.c +++ b/hw/arm/b-l475e-iot01a.c @@ -27,10 +27,37 @@ #include "hw/boards.h" #include "hw/qdev-properties.h" #include "qemu/error-report.h" -#include "hw/arm/stm32l4x5_soc.h" #include "hw/arm/boot.h" +#include "hw/core/split-irq.h" +#include "hw/arm/stm32l4x5_soc.h" +#include "hw/gpio/stm32l4x5_gpio.h" +#include "hw/display/dm163.h" + +/* B-L475E-IOT01A implementation is inspired from netduinoplus2 and arduin= o */ =20 -/* B-L475E-IOT01A implementation is derived from netduinoplus2 */ +/* + * There are actually 14 input pins in the DM163 device. + * Here the DM163 input pin EN isn't connected to the STM32L4x5 + * GPIOs as the IM120417002 colors shield doesn't actually use + * this pin to drive the RGB matrix. + */ +#define NUM_DM163_INPUTS 13 + +static const int dm163_input[NUM_DM163_INPUTS] =3D { + 1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */ + 0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */ + 0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */ + 0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */ + 0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */ + 0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */ + 1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */ + 0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */ + 0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */ + 1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */ + 2 * GPIO_NUM_PINS + 3, /* RST_B (RST) PC3 */ + 2 * GPIO_NUM_PINS + 4, /* LAT_B (LAT) PC4 */ + 2 * GPIO_NUM_PINS + 5, /* SELBK (SB) PC5 */ +}; =20 #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a") OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A) @@ -39,12 +66,16 @@ typedef struct Bl475eMachineState { MachineState parent_obj; =20 Stm32l4x5SocState soc; + SplitIRQ gpio_splitters[NUM_DM163_INPUTS]; + DM163State dm163; } Bl475eMachineState; =20 static void bl475e_init(MachineState *machine) { Bl475eMachineState *s =3D B_L475E_IOT01A(machine); const Stm32l4x5SocClass *sc; + DeviceState *dev, *gpio_out_splitter; + int gpio, pin; =20 object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_STM32L4X5XG_SOC); @@ -53,6 +84,30 @@ static void bl475e_init(MachineState *machine) sc =3D STM32L4X5_SOC_GET_CLASS(&s->soc); armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0, sc->flash_size); + + if (object_class_by_name("dm163")) { + object_initialize_child(OBJECT(machine), "dm163", + &s->dm163, TYPE_DM163); + dev =3D DEVICE(&s->dm163); + qdev_realize(dev, NULL, &error_abort); + + for (unsigned i =3D 0; i < NUM_DM163_INPUTS; i++) { + object_initialize_child(OBJECT(machine), "gpio-out-splitters[*= ]", + &s->gpio_splitters[i], TYPE_SPLIT_IRQ); + gpio_out_splitter =3D DEVICE(&s->gpio_splitters[i]); + qdev_prop_set_uint32(gpio_out_splitter, "num-lines", 2); + qdev_realize(gpio_out_splitter, NULL, &error_fatal); + + qdev_connect_gpio_out(gpio_out_splitter, 0, + qdev_get_gpio_in(DEVICE(&s->soc), dm163_input[i])); + qdev_connect_gpio_out(gpio_out_splitter, 1, + qdev_get_gpio_in(dev, i)); + gpio =3D dm163_input[i] / GPIO_NUM_PINS; + pin =3D dm163_input[i] % GPIO_NUM_PINS; + qdev_connect_gpio_out(DEVICE(&s->soc.gpio[gpio]), pin, + qdev_get_gpio_in(DEVICE(gpio_out_splitter), 0)); + } + } } =20 static void bl475e_machine_init(ObjectClass *oc, void *data) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 893a7bff66..8431384402 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -468,6 +468,7 @@ config B_L475E_IOT01A default y depends on TCG && ARM select STM32L4X5_SOC + imply DM163 =20 config STM32L4X5_SOC bool --=20 2.43.2 From nobody Fri May 17 05:35:16 2024 Delivered-To: importer2@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=137.194.2.220; envelope-from=ines.varhol@telecom-paris.fr; helo=zproxy1.enst.fr X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @telecom-paris.fr) X-ZM-MESSAGEID: 1713100059427100001 Content-Type: text/plain; charset="utf-8" `test_dm163_bank()` Checks that the pin "sout" of the DM163 led driver outputs the values received on pin "sin" with the expected latency (depending on the bank). `test_dm163_gpio_connection()` Check that changes to relevant STM32L4x5 GPIO pins are propagated to the DM163 device. Signed-off-by: Arnaud Minier Signed-off-by: In=C3=A8s Varhol Acked-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/qtest/dm163-test.c | 192 +++++++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 5 + 2 files changed, 197 insertions(+) create mode 100644 tests/qtest/dm163-test.c diff --git a/tests/qtest/dm163-test.c b/tests/qtest/dm163-test.c new file mode 100644 index 0000000000..6f88ceef44 --- /dev/null +++ b/tests/qtest/dm163-test.c @@ -0,0 +1,192 @@ +/* + * QTest testcase for DM163 + * + * Copyright (C) 2024 Samuel Tardieu + * Copyright (C) 2024 Arnaud Minier + * Copyright (C) 2024 In=C3=A8s Varhol + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#define SIN 8 +#define DCK 9 +#define RST_B 10 +#define LAT_B 11 +#define SELBK 12 +#define EN_B 13 + +#define DEVICE_NAME "/machine/dm163" +#define GPIO_OUT(name, value) qtest_set_irq_in(qts, DEVICE_NAME, NULL, nam= e, \ + value) +#define GPIO_PULSE(name) = \ + do { = \ + GPIO_OUT(name, 1); = \ + GPIO_OUT(name, 0); = \ + } while (0) + + +static void rise_gpio_pin_dck(QTestState *qts) +{ + /* Configure output mode for pin PB1 */ + qtest_writel(qts, 0x48000400, 0xFFFFFEB7); + /* Write 1 in ODR for PB1 */ + qtest_writel(qts, 0x48000414, 0x00000002); +} + +static void lower_gpio_pin_dck(QTestState *qts) +{ + /* Configure output mode for pin PB1 */ + qtest_writel(qts, 0x48000400, 0xFFFFFEB7); + /* Write 0 in ODR for PB1 */ + qtest_writel(qts, 0x48000414, 0x00000000); +} + +static void rise_gpio_pin_selbk(QTestState *qts) +{ + /* Configure output mode for pin PC5 */ + qtest_writel(qts, 0x48000800, 0xFFFFF7FF); + /* Write 1 in ODR for PC5 */ + qtest_writel(qts, 0x48000814, 0x00000020); +} + +static void lower_gpio_pin_selbk(QTestState *qts) +{ + /* Configure output mode for pin PC5 */ + qtest_writel(qts, 0x48000800, 0xFFFFF7FF); + /* Write 0 in ODR for PC5 */ + qtest_writel(qts, 0x48000814, 0x00000000); +} + +static void rise_gpio_pin_lat_b(QTestState *qts) +{ + /* Configure output mode for pin PC4 */ + qtest_writel(qts, 0x48000800, 0xFFFFFDFF); + /* Write 1 in ODR for PC4 */ + qtest_writel(qts, 0x48000814, 0x00000010); +} + +static void lower_gpio_pin_lat_b(QTestState *qts) +{ + /* Configure output mode for pin PC4 */ + qtest_writel(qts, 0x48000800, 0xFFFFFDFF); + /* Write 0 in ODR for PC4 */ + qtest_writel(qts, 0x48000814, 0x00000000); +} + +static void rise_gpio_pin_rst_b(QTestState *qts) +{ + /* Configure output mode for pin PC3 */ + qtest_writel(qts, 0x48000800, 0xFFFFFF7F); + /* Write 1 in ODR for PC3 */ + qtest_writel(qts, 0x48000814, 0x00000008); +} + +static void lower_gpio_pin_rst_b(QTestState *qts) +{ + /* Configure output mode for pin PC3 */ + qtest_writel(qts, 0x48000800, 0xFFFFFF7F); + /* Write 0 in ODR for PC3 */ + qtest_writel(qts, 0x48000814, 0x00000000); +} + +static void rise_gpio_pin_sin(QTestState *qts) +{ + /* Configure output mode for pin PA4 */ + qtest_writel(qts, 0x48000000, 0xFFFFFDFF); + /* Write 1 in ODR for PA4 */ + qtest_writel(qts, 0x48000014, 0x00000010); +} + +static void lower_gpio_pin_sin(QTestState *qts) +{ + /* Configure output mode for pin PA4 */ + qtest_writel(qts, 0x48000000, 0xFFFFFDFF); + /* Write 0 in ODR for PA4 */ + qtest_writel(qts, 0x48000014, 0x00000000); +} + +static void test_dm163_bank(const void *opaque) +{ + const long bank =3D (uintptr_t) opaque; + const int width =3D bank ? 192 : 144; + + QTestState *qts =3D qtest_initf("-M b-l475e-iot01a"); + qtest_irq_intercept_out_named(qts, DEVICE_NAME, "sout"); + GPIO_OUT(RST_B, 1); + GPIO_OUT(EN_B, 0); + GPIO_OUT(DCK, 0); + GPIO_OUT(SELBK, bank); + GPIO_OUT(LAT_B, 1); + + /* Fill bank with zeroes */ + GPIO_OUT(SIN, 0); + for (int i =3D 0; i < width; i++) { + GPIO_PULSE(DCK); + } + /* Fill bank with ones, check that we get the previous zeroes */ + GPIO_OUT(SIN, 1); + for (int i =3D 0; i < width; i++) { + GPIO_PULSE(DCK); + g_assert(!qtest_get_irq(qts, 0)); + } + + /* Pulse one more bit in the bank, check that we get a one */ + GPIO_PULSE(DCK); + g_assert(qtest_get_irq(qts, 0)); + + qtest_quit(qts); +} + +static void test_dm163_gpio_connection(void) +{ + QTestState *qts =3D qtest_init("-M b-l475e-iot01a"); + qtest_irq_intercept_in(qts, DEVICE_NAME); + + g_assert_false(qtest_get_irq(qts, SIN)); + g_assert_false(qtest_get_irq(qts, DCK)); + g_assert_false(qtest_get_irq(qts, RST_B)); + g_assert_false(qtest_get_irq(qts, LAT_B)); + g_assert_false(qtest_get_irq(qts, SELBK)); + + rise_gpio_pin_dck(qts); + g_assert_true(qtest_get_irq(qts, DCK)); + lower_gpio_pin_dck(qts); + g_assert_false(qtest_get_irq(qts, DCK)); + + rise_gpio_pin_lat_b(qts); + g_assert_true(qtest_get_irq(qts, LAT_B)); + lower_gpio_pin_lat_b(qts); + g_assert_false(qtest_get_irq(qts, LAT_B)); + + rise_gpio_pin_selbk(qts); + g_assert_true(qtest_get_irq(qts, SELBK)); + lower_gpio_pin_selbk(qts); + g_assert_false(qtest_get_irq(qts, SELBK)); + + rise_gpio_pin_rst_b(qts); + g_assert_true(qtest_get_irq(qts, RST_B)); + lower_gpio_pin_rst_b(qts); + g_assert_false(qtest_get_irq(qts, RST_B)); + + rise_gpio_pin_sin(qts); + g_assert_true(qtest_get_irq(qts, SIN)); + lower_gpio_pin_sin(qts); + g_assert_false(qtest_get_irq(qts, SIN)); + + g_assert_false(qtest_get_irq(qts, DCK)); + g_assert_false(qtest_get_irq(qts, LAT_B)); + g_assert_false(qtest_get_irq(qts, SELBK)); + g_assert_false(qtest_get_irq(qts, RST_B)); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_data_func("/dm163/bank0", (void *)0, test_dm163_bank); + qtest_add_data_func("/dm163/bank1", (void *)1, test_dm163_bank); + qtest_add_func("/dm163/gpio_connection", test_dm163_gpio_connection); + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 36c5c13a7b..2c6fd4ebbb 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -207,6 +207,9 @@ qtests_stm32l4x5 =3D \ 'stm32l4x5_rcc-test', 'stm32l4x5_gpio-test'] =20 +qtests_dm163 =3D \ + ['dm163-test'] + qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-= dualtimer-test'] : []) + \ @@ -222,6 +225,8 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MICROBIT') ? ['microbit-test'] : [])= + \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') ? qtests_stm32l4x5 := []) + \ (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-= test'] : []) + \ + (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and + config_all_devices.has_key('CONFIG_DM163')? qtests_dm163 : []) + \ ['arm-cpu-features', 'boot-serial-test'] =20 --=20 2.43.2