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helo=lists.gnu.org; Received-SPF: pass client-ip=80.78.11.85; envelope-from=clement.mathieu--drif@eviden.com; helo=smarthost4.eviden.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @eviden.com) X-ZM-MESSAGEID: 1713801257212100007 Some variables struct fields and functions can be used for both slpte and flpte. We can modify certain identifiers to make them more generic. - slpte in IOMMUTLBEntry becomes pte and will be used for both FL and SL - VTD_SL_PT_LEVEL, VTD_SL_PT_PAGE_SIZE_MASK and VTD_SL_LEVEL_BITS can be renamed and considered as a common constants - vtd_iova_range_check becomes vtd_iova_sl_range_check because the range check depends on the translation type - vtd_do_iommu_translate now handles both FL and SL so we can rename slpte to pte - VTD_SL_PT_BASE_ADDR_MASK becomes VTD_PT_BASE_ADDR_MASK because the address offset within a 64bits word of a Scalable-Mode PASID Table Entry is the same for FL and SL. As a consequence, vtd_get_slpte_addr is also renamed to vtd_get_pte_addr. - vtd_is_last_slpte becomes vtd_is_last_slpte because the same bit is used for FL and SL. - vtd_slpt_level_page_mask becomes vtd_pt_level_page_mask - vtd_get_slpte becomes vtd_get_pte Signed-off-by: Cl=C3=A9ment Mathieu--Drif --- hw/i386/intel_iommu.c | 106 ++++++++++++++++----------------- hw/i386/intel_iommu_internal.h | 10 ++-- include/hw/i386/intel_iommu.h | 2 +- 3 files changed, 60 insertions(+), 58 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cc8e59674e..6f1364b3fd 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -259,15 +259,15 @@ static gboolean vtd_hash_remove_by_domain(gpointer ke= y, gpointer value, } =20 /* The shift of an addr for a certain level of paging structure */ -static inline uint32_t vtd_slpt_level_shift(uint32_t level) +static inline uint32_t vtd_pt_level_shift(uint32_t level) { assert(level !=3D 0); - return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS; + return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_LEVEL_BITS; } =20 -static inline uint64_t vtd_slpt_level_page_mask(uint32_t level) +static inline uint64_t vtd_pt_level_page_mask(uint32_t level) { - return ~((1ULL << vtd_slpt_level_shift(level)) - 1); + return ~((1ULL << vtd_pt_level_shift(level)) - 1); } =20 static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value, @@ -324,7 +324,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) =20 static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) { - return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; + return (addr & vtd_pt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K; } =20 /* Must be called with IOMMU lock held */ @@ -352,7 +352,7 @@ out: =20 /* Must be with IOMMU lock held */ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id, - uint16_t domain_id, hwaddr addr, uint64_t slp= te, + uint16_t domain_id, hwaddr addr, uint64_t pte, uint8_t access_flags, uint32_t level, uint32_t pasid) { @@ -360,7 +360,7 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, struct vtd_iotlb_key *key =3D g_malloc(sizeof(*key)); uint64_t gfn =3D vtd_get_iotlb_gfn(addr, level); =20 - trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id); + trace_vtd_iotlb_page_update(source_id, addr, pte, domain_id); if (g_hash_table_size(s->iotlb) >=3D VTD_IOTLB_MAX_SIZE) { trace_vtd_iotlb_reset("iotlb exceeds size limit"); vtd_reset_iotlb_locked(s); @@ -368,9 +368,9 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16= _t source_id, =20 entry->gfn =3D gfn; entry->domain_id =3D domain_id; - entry->slpte =3D slpte; + entry->pte =3D pte; entry->access_flags =3D access_flags; - entry->mask =3D vtd_slpt_level_page_mask(level); + entry->mask =3D vtd_pt_level_page_mask(level); entry->pasid =3D pasid; =20 key->gfn =3D gfn; @@ -685,32 +685,32 @@ static inline dma_addr_t vtd_ce_get_slpt_base(VTDCont= extEntry *ce) return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR; } =20 -static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw) +static inline uint64_t vtd_get_pte_addr(uint64_t pte, uint8_t aw) { - return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw); + return pte & VTD_PT_BASE_ADDR_MASK(aw); } =20 /* Whether the pte indicates the address of the page frame */ -static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level) +static inline bool vtd_is_last_pte(uint64_t pte, uint32_t level) { - return level =3D=3D VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MA= SK); + return level =3D=3D VTD_COMMON_PT_LEVEL || (pte & VTD_PT_PAGE_SIZE_MAS= K); } =20 -/* Get the content of a spte located in @base_addr[@index] */ -static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index) +/* Get the content of a pte located in @base_addr[@index] */ +static uint64_t vtd_get_pte(dma_addr_t base_addr, uint32_t index) { - uint64_t slpte; + uint64_t pte; =20 - assert(index < VTD_SL_PT_ENTRY_NR); + assert(index < VTD_PT_ENTRY_NR); =20 if (dma_memory_read(&address_space_memory, - base_addr + index * sizeof(slpte), - &slpte, sizeof(slpte), MEMTXATTRS_UNSPECIFIED)) { - slpte =3D (uint64_t)-1; - return slpte; + base_addr + index * sizeof(pte), + &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { + pte =3D (uint64_t)-1; + return pte; } - slpte =3D le64_to_cpu(slpte); - return slpte; + pte =3D le64_to_cpu(pte); + return pte; } =20 /* Given an iova and the level of paging structure, return the offset @@ -718,8 +718,8 @@ static uint64_t vtd_get_slpte(dma_addr_t base_addr, uin= t32_t index) */ static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level) { - return (iova >> vtd_slpt_level_shift(level)) & - ((1ULL << VTD_SL_LEVEL_BITS) - 1); + return (iova >> vtd_pt_level_shift(level)) & + ((1ULL << VTD_LEVEL_BITS) - 1); } =20 /* Check Capability Register to see if the @level of page-table is support= ed */ @@ -1016,7 +1016,7 @@ static inline uint64_t vtd_iova_limit(IntelIOMMUState= *s, } =20 /* Return true if IOVA passes range check, otherwise false. */ -static inline bool vtd_iova_range_check(IntelIOMMUState *s, +static inline bool vtd_iova_sl_range_check(IntelIOMMUState *s, uint64_t iova, VTDContextEntry *ce, uint8_t aw, uint32_t pasid) { @@ -1064,12 +1064,12 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, = uint32_t level) assert(level < VTD_SPTE_RSVD_LEN); /* * Zero level doesn't exist. The smallest level is VTD_SL_PT_LEVEL=3D1= and - * checked by vtd_is_last_slpte(). + * checked by vtd_is_last_pte(). */ assert(level); =20 if ((level =3D=3D VTD_SL_PD_LEVEL || level =3D=3D VTD_SL_PDP_LEVEL) && - (slpte & VTD_SL_PT_PAGE_SIZE_MASK)) { + (slpte & VTD_PT_PAGE_SIZE_MASK)) { /* large page */ rsvd_mask =3D vtd_spte_rsvd_large[level]; } else { @@ -1095,7 +1095,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDC= ontextEntry *ce, uint64_t access_right_check; uint64_t xlat, size; =20 - if (!vtd_iova_range_check(s, iova, ce, aw_bits, pasid)) { + if (!vtd_iova_sl_range_check(s, iova, ce, aw_bits, pasid)) { error_report_once("%s: detected IOVA overflow (iova=3D0x%" PRIx64 = "," "pasid=3D0x%" PRIx32 ")", __func__, iova, pasid); return -VTD_FR_ADDR_BEYOND_MGAW; @@ -1106,7 +1106,7 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VTDC= ontextEntry *ce, =20 while (true) { offset =3D vtd_iova_level_offset(iova, level); - slpte =3D vtd_get_slpte(addr, offset); + slpte =3D vtd_get_pte(addr, offset); =20 if (slpte =3D=3D (uint64_t)-1) { error_report_once("%s: detected read error on DMAR slpte " @@ -1137,17 +1137,17 @@ static int vtd_iova_to_slpte(IntelIOMMUState *s, VT= DContextEntry *ce, return -VTD_FR_PAGING_ENTRY_RSVD; } =20 - if (vtd_is_last_slpte(slpte, level)) { + if (vtd_is_last_pte(slpte, level)) { *slptep =3D slpte; *slpte_level =3D level; break; } - addr =3D vtd_get_slpte_addr(slpte, aw_bits); + addr =3D vtd_get_pte_addr(slpte, aw_bits); level--; } =20 - xlat =3D vtd_get_slpte_addr(*slptep, aw_bits); - size =3D ~vtd_slpt_level_page_mask(level) + 1; + xlat =3D vtd_get_pte_addr(*slptep, aw_bits); + size =3D ~vtd_pt_level_page_mask(level) + 1; =20 /* * From VT-d spec 3.14: Untranslated requests and translation @@ -1298,14 +1298,14 @@ static int vtd_page_walk_level(dma_addr_t addr, uin= t64_t start, =20 trace_vtd_page_walk_level(addr, level, start, end); =20 - subpage_size =3D 1ULL << vtd_slpt_level_shift(level); - subpage_mask =3D vtd_slpt_level_page_mask(level); + subpage_size =3D 1ULL << vtd_pt_level_shift(level); + subpage_mask =3D vtd_pt_level_page_mask(level); =20 while (iova < end) { iova_next =3D (iova & subpage_mask) + subpage_size; =20 offset =3D vtd_iova_level_offset(iova, level); - slpte =3D vtd_get_slpte(addr, offset); + slpte =3D vtd_get_pte(addr, offset); =20 if (slpte =3D=3D (uint64_t)-1) { trace_vtd_page_walk_skip_read(iova, iova_next); @@ -1328,12 +1328,12 @@ static int vtd_page_walk_level(dma_addr_t addr, uin= t64_t start, */ entry_valid =3D read_cur | write_cur; =20 - if (!vtd_is_last_slpte(slpte, level) && entry_valid) { + if (!vtd_is_last_pte(slpte, level) && entry_valid) { /* * This is a valid PDE (or even bigger than PDE). We need * to walk one further level. */ - ret =3D vtd_page_walk_level(vtd_get_slpte_addr(slpte, info->aw= ), + ret =3D vtd_page_walk_level(vtd_get_pte_addr(slpte, info->aw), iova, MIN(iova_next, end), level - 1, read_cur, write_cur, info); } else { @@ -1350,7 +1350,7 @@ static int vtd_page_walk_level(dma_addr_t addr, uint6= 4_t start, event.entry.perm =3D IOMMU_ACCESS_FLAG(read_cur, write_cur); event.entry.addr_mask =3D ~subpage_mask; /* NOTE: this is only meaningful if entry_valid =3D=3D true */ - event.entry.translated_addr =3D vtd_get_slpte_addr(slpte, info= ->aw); + event.entry.translated_addr =3D vtd_get_pte_addr(slpte, info->= aw); event.type =3D event.entry.perm ? IOMMU_NOTIFIER_MAP : IOMMU_NOTIFIER_UNMAP; ret =3D vtd_page_walk_one(&event, info); @@ -1384,11 +1384,11 @@ static int vtd_page_walk(IntelIOMMUState *s, VTDCon= textEntry *ce, dma_addr_t addr =3D vtd_get_iova_pgtbl_base(s, ce, pasid); uint32_t level =3D vtd_get_iova_level(s, ce, pasid); =20 - if (!vtd_iova_range_check(s, start, ce, info->aw, pasid)) { + if (!vtd_iova_sl_range_check(s, start, ce, info->aw, pasid)) { return -VTD_FR_ADDR_BEYOND_MGAW; } =20 - if (!vtd_iova_range_check(s, end, ce, info->aw, pasid)) { + if (!vtd_iova_sl_range_check(s, end, ce, info->aw, pasid)) { /* Fix end so that it reaches the maximum */ end =3D vtd_iova_limit(s, ce, info->aw, pasid); } @@ -1869,7 +1869,7 @@ static bool vtd_do_iommu_translate(VTDAddressSpace *v= td_as, PCIBus *bus, VTDContextEntry ce; uint8_t bus_num =3D pci_bus_num(bus); VTDContextCacheEntry *cc_entry; - uint64_t slpte, page_mask; + uint64_t pte, page_mask; uint32_t level, pasid =3D vtd_as->pasid; uint16_t source_id =3D PCI_BUILD_BDF(bus_num, devfn); int ret_fr; @@ -1890,13 +1890,13 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, =20 cc_entry =3D &vtd_as->context_cache_entry; =20 - /* Try to fetch slpte form IOTLB, we don't need RID2PASID logic */ + /* Try to fetch pte form IOTLB, we don't need RID2PASID logic */ if (!rid2pasid) { iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); if (iotlb_entry) { - trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, + trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, iotlb_entry->domain_id); - slpte =3D iotlb_entry->slpte; + pte =3D iotlb_entry->pte; access_flags =3D iotlb_entry->access_flags; page_mask =3D iotlb_entry->mask; goto out; @@ -1968,20 +1968,20 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, return true; } =20 - /* Try to fetch slpte form IOTLB for RID2PASID slow path */ + /* Try to fetch pte form IOTLB for RID2PASID slow path */ if (rid2pasid) { iotlb_entry =3D vtd_lookup_iotlb(s, source_id, pasid, addr); if (iotlb_entry) { - trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte, + trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->pte, iotlb_entry->domain_id); - slpte =3D iotlb_entry->slpte; + pte =3D iotlb_entry->pte; access_flags =3D iotlb_entry->access_flags; page_mask =3D iotlb_entry->mask; goto out; } } =20 - ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &slpte, &level, + ret_fr =3D vtd_iova_to_slpte(s, &ce, addr, is_write, &pte, &level, &reads, &writes, s->aw_bits, pasid); if (ret_fr) { vtd_report_fault(s, -ret_fr, is_fpd_set, source_id, @@ -1989,14 +1989,14 @@ static bool vtd_do_iommu_translate(VTDAddressSpace = *vtd_as, PCIBus *bus, goto error; } =20 - page_mask =3D vtd_slpt_level_page_mask(level); + page_mask =3D vtd_pt_level_page_mask(level); access_flags =3D IOMMU_ACCESS_FLAG(reads, writes); vtd_update_iotlb(s, source_id, vtd_get_domain_id(s, &ce, pasid), - addr, slpte, access_flags, level, pasid); + addr, pte, access_flags, level, pasid); out: vtd_iommu_unlock(s); entry->iova =3D addr & page_mask; - entry->translated_addr =3D vtd_get_slpte_addr(slpte, s->aw_bits) & pag= e_mask; + entry->translated_addr =3D vtd_get_pte_addr(pte, s->aw_bits) & page_ma= sk; entry->addr_mask =3D ~page_mask; entry->perm =3D access_flags; return true; diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index cbc4030031..8d27b1c15b 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -518,22 +518,24 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_PASID_ENTRY_SLPTPTR (~0xfffULL) =20 /* Paging Structure common */ -#define VTD_SL_PT_PAGE_SIZE_MASK (1ULL << 7) +#define VTD_SM_PASID_ENTRY_PTPTR (~0xfffULL) +#define VTD_PT_PAGE_SIZE_MASK (1ULL << 7) +#define VTD_PT_ENTRY_NR 512 +#define VTD_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(a= w)) +#define VTD_COMMON_PT_LEVEL 1 /* Bits to decide the offset for each level */ -#define VTD_SL_LEVEL_BITS 9 +#define VTD_LEVEL_BITS 9 =20 /* Second Level Paging Structure */ #define VTD_SL_PML4_LEVEL 4 #define VTD_SL_PDP_LEVEL 3 #define VTD_SL_PD_LEVEL 2 #define VTD_SL_PT_LEVEL 1 -#define VTD_SL_PT_ENTRY_NR 512 =20 /* Masks for Second Level Paging Entry */ #define VTD_SL_RW_MASK 3ULL #define VTD_SL_R 1ULL #define VTD_SL_W (1ULL << 1) -#define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(= aw)) #define VTD_SL_IGN_COM 0xbff0000000000000ULL #define VTD_SL_TM (1ULL << 62) =20 diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 7fa0a695c8..b9a01556ec 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -152,7 +152,7 @@ struct VTDIOTLBEntry { uint64_t gfn; uint16_t domain_id; uint32_t pasid; - uint64_t slpte; + uint64_t pte; uint64_t mask; uint8_t access_flags; }; --=20 2.44.0