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([156.19.246.23]) by smtp.gmail.com with ESMTPSA id h17-20020a170902f55100b001e49428f327sm12531642plf.176.2024.04.24.16.44.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Apr 2024 16:45:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1714002303; x=1714607103; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=JlF9yvG1tLc13jMw+Ez3fV/BsqlR5r0EuFKx522bnZo=; b=Xf4Jx93BGQgaFgNC/2KdpdvncCH8K2VWWRnLThuKSUsp8jrijtqb5abO6g0FWdUecn yn1PG5HdMI+9IGZxOrz3883zXh7tUN0rlfAYzyZxxWWXRWbgeBQ6NIEOeOK6yWzU8cWs E4d2l3g7pC5DkTMXTRbmntayJ+StbHhE9oq1/RrvzuQmNAg5FA5l4vohbNIZ5MyilgDM SUipHFXPI0GfAyJ67D+qYtfDhMLEehQt5xODcPQtAD52/nzP69eA1yuFsY1V3ooY+kda qiz8yoFfbU/nxdbrM3/3Hw8xLQ501Ql94ZHynI5upp7NwmhcQqv9kcenPcevNxabxxEp q+Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714002303; x=1714607103; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JlF9yvG1tLc13jMw+Ez3fV/BsqlR5r0EuFKx522bnZo=; b=AL3tsF2NhyTQYuP5EOe4W+DSkNVR7uPkx+L0ITLR+SapMDD/CoZ8RA84iz+r1AjtA8 UBxt1LeKnuWKX2Xe3KtbAY++eKken/hVkC75SdhoqlX1CSOeZxDkCR55haFd4KMdGErg tmD1TKf/J2JxddizPA+BbCKS33yrlBEEQ8FO4X09rZYLPZRQpz6wF4Tl0XKgj2Jzdkpc o1WF7RCkublggV8ISbtOYWOs7K/oXE+QwibxceKUhK0u6251SVrS+8yKcA+zvVvGAWln wzNY4DHrWrrU4pNzrgz9mOg9k40Ss1ZXyVpvnYo/2nzxfPVRtxaeCyyypkz9zg6wOjlJ DAhQ== X-Gm-Message-State: AOJu0YzAvPoEr8wOALjPyEj/gBfYih9ggxe6YqubrtaIkbDU7PyYdENh 02IZgOm9ibS+temZjrvyd3kdldS0poVntn9zYpcZ8FNEEdkTjZOnZ5sNunhFicFp6IeC6b8DBky d X-Google-Smtp-Source: AGHT+IFCvRXg8dHDLiD1M+vNfxcUv15yZDg6K9YTTm84+xR8pv7OsZzhnrvTmZcJb4TyhlXDxowtGw== X-Received: by 2002:a17:903:22ca:b0:1e7:b6f4:2d75 with SMTP id y10-20020a17090322ca00b001e7b6f42d75mr5699216plg.6.1714002302734; Wed, 24 Apr 2024 16:45:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/5] target/alpha: Split out gen_pc_disp Date: Wed, 24 Apr 2024 16:44:35 -0700 Message-Id: <20240424234436.995410-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240424234436.995410-1-richard.henderson@linaro.org> References: <20240424234436.995410-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1714002409541100003 Content-Type: text/plain; charset="utf-8" Prepare for pcrel by not modifying cpu_pc before use, in the case of JSR. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/translate.c | 41 ++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index c1a55e5153..86402d96d5 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -252,6 +252,11 @@ static void st_flag_byte(TCGv val, unsigned shift) tcg_gen_st8_i64(val, tcg_env, get_flag_ofs(shift)); } =20 +static void gen_pc_disp(DisasContext *ctx, TCGv dest, int32_t disp) +{ + tcg_gen_movi_i64(dest, ctx->base.pc_next + disp); +} + static void gen_excp_1(int exception, int error_code) { TCGv_i32 tmp1, tmp2; @@ -263,7 +268,7 @@ static void gen_excp_1(int exception, int error_code) =20 static DisasJumpType gen_excp(DisasContext *ctx, int exception, int error_= code) { - tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + gen_pc_disp(ctx, cpu_pc, 0); gen_excp_1(exception, error_code); return DISAS_NORETURN; } @@ -427,14 +432,12 @@ static DisasJumpType gen_store_conditional(DisasConte= xt *ctx, int ra, int rb, =20 static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp) { - uint64_t dest =3D ctx->base.pc_next + disp; - - if (translator_use_goto_tb(&ctx->base, dest)) { + if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) { tcg_gen_goto_tb(idx); - tcg_gen_movi_i64(cpu_pc, dest); + gen_pc_disp(ctx, cpu_pc, disp); tcg_gen_exit_tb(ctx->base.tb, idx); } else { - tcg_gen_movi_i64(cpu_pc, dest); + gen_pc_disp(ctx, cpu_pc, disp); tcg_gen_lookup_and_goto_ptr(); } } @@ -442,7 +445,7 @@ static void gen_goto_tb(DisasContext *ctx, int idx, int= 32_t disp) static DisasJumpType gen_bdirect(DisasContext *ctx, int ra, int32_t disp) { if (ra !=3D 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); + gen_pc_disp(ctx, ctx->ir[ra], 0); } =20 /* Notice branch-to-next; used to initialize RA with the PC. */ @@ -1091,7 +1094,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, = int palcode) } =20 /* Allow interrupts to be recognized right away. */ - tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + gen_pc_disp(ctx, cpu_pc, 0); return DISAS_PC_UPDATED_NOCHAIN; =20 case 0x36: @@ -1138,19 +1141,17 @@ static DisasJumpType gen_call_pal(DisasContext *ctx= , int palcode) #else { TCGv tmp =3D tcg_temp_new(); - uint64_t exc_addr =3D ctx->base.pc_next; - uint64_t entry =3D ctx->palbr; + uint64_t entry; =20 + gen_pc_disp(ctx, tmp, 0); if (ctx->tbflags & ENV_FLAG_PAL_MODE) { - exc_addr |=3D 1; + tcg_gen_ori_i64(tmp, tmp, 1); } else { - tcg_gen_movi_i64(tmp, 1); - st_flag_byte(tmp, ENV_FLAG_PAL_SHIFT); + st_flag_byte(tcg_constant_i64(1), ENV_FLAG_PAL_SHIFT); } - - tcg_gen_movi_i64(tmp, exc_addr); tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr)); =20 + entry =3D ctx->palbr; entry +=3D (palcode & 0x80 ? 0x2000 + (palcode - 0x80) * 64 : 0x1000 + palcode * 64); @@ -2344,9 +2345,13 @@ static DisasJumpType translate_one(DisasContext *ctx= , uint32_t insn) /* JMP, JSR, RET, JSR_COROUTINE. These only differ by the branch prediction stack action, which of course we don't implement. */ vb =3D load_gpr(ctx, rb); - tcg_gen_andi_i64(cpu_pc, vb, ~3); if (ra !=3D 31) { - tcg_gen_movi_i64(ctx->ir[ra], ctx->base.pc_next); + tmp =3D tcg_temp_new(); + tcg_gen_andi_i64(tmp, vb, ~3); + gen_pc_disp(ctx, ctx->ir[ra], 0); + tcg_gen_mov_i64(cpu_pc, tmp); + } else { + tcg_gen_andi_i64(cpu_pc, vb, ~3); } ret =3D DISAS_PC_UPDATED; break; @@ -2908,7 +2913,7 @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) gen_goto_tb(ctx, 0, 0); break; case DISAS_PC_STALE: - tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next); + gen_pc_disp(ctx, cpu_pc, 0); /* FALLTHRU */ case DISAS_PC_UPDATED: tcg_gen_lookup_and_goto_ptr(); --=20 2.34.1