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Mon, 29 Apr 2024 12:28:10 -0700 (PDT) From: Atish Patra Date: Mon, 29 Apr 2024 12:28:04 -0700 Subject: [PATCH 1/3] target/riscv: Save counter values during countinhibit update MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20240429-countinhibit_fix-v1-1-802ec1e99133@rivosinc.com> References: <20240429-countinhibit_fix-v1-0-802ec1e99133@rivosinc.com> In-Reply-To: <20240429-countinhibit_fix-v1-0-802ec1e99133@rivosinc.com> To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Atish Patra , palmer@dabbelt.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, bin.meng@windriver.com, dbarboza@ventanamicro.com, alistair.francis@wdc.com X-Mailer: b4 0.13-dev-f0463 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer2=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer2=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer2=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc-com.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1714418948746100003 Currently, if a counter monitoring cycle/instret is stopped via mcountinhibit we just update the state while the value is saved during the next read. This is not accurate as the read may happen many cycles after the counter is stopped. Ideally, the read should return the value saved when the counter is stopped. Thus, save the value of the counter during the inhibit update operation and return that value during the read if corresponding bit in mcountihibit is set. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 - target/riscv/csr.c | 32 ++++++++++++++++++++------------ target/riscv/machine.c | 1 - 3 files changed, 20 insertions(+), 14 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3b1a02b9449a..09bbf7ce9880 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -153,7 +153,6 @@ typedef struct PMUCTRState { target_ulong mhpmcounter_prev; /* Snapshort value of a counter in RV32 */ target_ulong mhpmcounterh_prev; - bool started; /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigge= r */ target_ulong irq_overflow_left; } PMUCTRState; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 726096444fae..68ca31aff47d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -929,17 +929,11 @@ static RISCVException riscv_pmu_read_ctr(CPURISCVStat= e *env, target_ulong *val, =20 if (get_field(env->mcountinhibit, BIT(ctr_idx))) { /* - * Counter should not increment if inhibit bit is set. We can't re= ally - * stop the icount counting. Just return the counter value written= by - * the supervisor to indicate that counter was not incremented. + * Counter should not increment if inhibit bit is set. Just return= the + * current counter value. */ - if (!counter->started) { - *val =3D ctr_val; - return RISCV_EXCP_NONE; - } else { - /* Mark that the counter has been stopped */ - counter->started =3D false; - } + *val =3D ctr_val; + return RISCV_EXCP_NONE; } =20 /* @@ -1973,9 +1967,23 @@ static RISCVException write_mcountinhibit(CPURISCVSt= ate *env, int csrno, =20 /* Check if any other counter is also monitoring cycles/instructions */ for (cidx =3D 0; cidx < RV_MAX_MHPMCOUNTERS; cidx++) { - if (!get_field(env->mcountinhibit, BIT(cidx))) { counter =3D &env->pmu_ctrs[cidx]; - counter->started =3D true; + if (get_field(env->mcountinhibit, BIT(cidx)) && (val & BIT(cidx)))= { + /* + * Update the counter value for cycle/instret as we can't stop= the + * host ticks. But we should show the current value at this mo= ment. + */ + if (riscv_pmu_ctr_monitor_cycles(env, cidx) || + riscv_pmu_ctr_monitor_instructions(env, cidx)) { + counter->mhpmcounter_val =3D get_ticks(false) - + counter->mhpmcounter_prev + + counter->mhpmcounter_val; + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + counter->mhpmcounterh_val =3D get_ticks(false) - + counter->mhpmcounterh_prev= + + counter->mhpmcounterh_val; + } + } } } =20 diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 76f2150f78b5..3e0f2dd2ce2a 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -328,7 +328,6 @@ static const VMStateDescription vmstate_pmu_ctr_state = =3D { VMSTATE_UINTTL(mhpmcounterh_val, PMUCTRState), VMSTATE_UINTTL(mhpmcounter_prev, PMUCTRState), VMSTATE_UINTTL(mhpmcounterh_prev, PMUCTRState), - VMSTATE_BOOL(started, PMUCTRState), VMSTATE_END_OF_LIST() } }; --=20 2.34.1